JP3145988B2 - Data S / P conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data S / P (serial-parallel) conversion circuit for converting serial data into parallel data.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a circuit configuration of a conventional data serial / parallel (S / P) conversion circuit. The data S / P conversion circuit shown in FIG.
2 ⁿ which are cascaded in the order driven by the same clock signal CLK with the serial data input to N as an input.
D flip-flops (F / F) FF2 ⁿ , FF
^{2 n-1, ..., FF2} 1, and FF2 ^0, D flip-flop ^{FF2 n, FF 2n-1,} ..., FF2 1, FF2 0 each output Q of
The 2 ⁿ selectors but connected to the input 1 41-
^{2 n, 41-2 n-1,} ..., 41-2 1, and 41-2 ^0, selector ^{41-2 n, 41-2 n-1,} ..., 41-2 1, 41-
Each of the 2 ⁰ outputs O is connected to an input D and 2 ⁿ D 0
Flip-flops 42-2 ⁿ , 42-2 ^n-1 ,..., 42-
2 ¹ , 42-2 ⁰ and the D flip-flop 42-2
^{n, 42-2 n-1, ...} , 42-2 1, 42-2 0 each output Q of
Are the parallel outputs PO2 ⁿ , PO2 ⁿ⁻¹ ,.
From 2 ¹ , PO 2 ⁰ , 2 ⁿ , 2 ⁿ⁻¹ ,
.., Are output as the second and first bit data.

In the above configuration, the D flip-flop 42
-2ⁿ, 42-2^n-1, ..., 42-2 ¹, 42-2⁰Is D
Flip-flop FF2ⁿ, FF2^n-1, ..., FF2¹,
FF2⁰And common clock signal CLK to clock input
It is connected. Selector 41-2ⁿ, 41-2^n-1,
…, 41-2¹, 41-2⁰Input 0 is D flip-flop
Rop 42-2ⁿ, 42-2^n-1, ..., 42-2¹, 42
-2⁰Are connected respectively. 2ⁿ Dividing power
The counter 43 outputs the clock signal CLK to 2ⁿ Divide and count
Decoder 44 is 2ⁿ The output of the frequency dividing counter 43 is decoded.
Do 2ⁿ ‘1’ level signal is output every clock cycle
Press the selector 41-2ⁿ, 41-2^n-1, ..., 41-
2¹, 41-2⁰Is output to the select input S. selector
41-2ⁿ, 41-2^n-1, ..., 41-2¹, 41-2
⁰Is the input 1 when the select input S is at the ‘1’ level.
Signal at the ‘0’ level, the signal at input 0
Output to

[0004]

[0004] As shown in FIG. 4, a conventional parallel data 1 → 2 ⁿ output in which the phases of parallel data are aligned.
In the data S / P conversion circuit, the number of F / Fs used increases as the number of parallels (2 ⁿ ) increases. As the number of F / Fs increases, the clock (CLK) skew between the F / Fs also increases, so that it is difficult to guarantee the hold time and there is a possibility of racing (FIG. 4A). The increase in the number of parallels complicates the logic of the parallel conversion counter and decoder, and increases the path delay of the latch enable pulse of the parallel data. Therefore, when the CLK speed is high, the signal line in FIG. There was a risk of malfunction due to a critical path.

[0005] The present invention has been developed to solve the problem of the prior art circuit.
An object of the present invention is to provide a data S / P conversion circuit that reduces skew and prevents formation of a critical path when the CLK speed is high.

[0006]

According to a first aspect of the present invention, an input clock signal is frequency-divided and supplied to a timing adjustment storage means of an output stage as a clock signal. First storage means for outputting a clock signal of a unit of stages, and X secondly connected second storage means for shifting input serial data by X stages (X is an integer of 2 or more) according to the input clock signal And X third storage means for holding the outputs of the X second storage means at the same timing in accordance with the input clock signal, and outputting the outputs of the X third storage means at the same timing. A plurality of 1 / X serial-to-parallel conversion units, each of which is held and output to the next-stage unit, and connected to n stages (n is a natural number), 1 / ⁿ serial - characterized by performing parallel conversion, further, said third memory means
Is synchronized with the clock signal supplied from the first storage means.
First data holding means operating in response to an input clock signal;
And second data holding means operating in synchronization with the signal
It is characterized by being.

The invention according to claim 2 is characterized in that each of the storage means is constituted by using a flip-flop. The invention according to claim 3 is 1 /
The X serial-parallel conversion unit is a シ リ ア ル serial-parallel conversion unit that performs シ リ ア ル serial-parallel conversion.

[0008] The invention according to claim 4 provides the first data.
Data holding means is configured using the selector, and the second data
That the holding means is configured using flip-flops.
It is characterized by.

According to the present invention, when X is 2, for example, a plurality of 1 → 2 S / P (serial-parallel) conversion units are provided, and by connecting these in multiple stages, the CLK skew is reduced and the CLK speed is reduced. , A 1 → 2 ⁿ data S / P conversion circuit which prevents the formation of a critical path in the case where the value is high can be realized.

[0010]

Embodiments of a data S / P conversion circuit according to the present invention will be described below with reference to the drawings. FIG. 1 shows an internal configuration diagram of one embodiment of a 1 → 2 S / P conversion unit which converts a serial signal into a 2-bit parallel signal, which is a basic configuration of a data S / P conversion circuit according to the present invention.

The 1 → 2 S / P conversion unit includes D flip-flops FF2 and FF1 for shifting a serial data input (SDIN) by a CLK input, and a toggle flip-flop T1 ( In FIG. 1, as an example, a clock terminal is used as an input, and a negative output of a D flip-flop is connected to an input D so that a positive output is configured as a toggle output PCLK.)
2, S1, parallel conversion flip-flop FF'2, F
F'1 and retiming flip-flops P1 and P2 for changing parallel data to 1/2 frequency CLK. In the selectors S2 and S1 operating in the same manner as described with reference to FIG. 4, the input 1 receives the output Q of the D flip-flops FF2 and FF1, and the input 0 receives the D
The output Q of the flip-flops FF'2 and FF'1 is connected to the select input S, and the output Q of the toggle flip-flop T1 is connected to the select input S. Further, selectors S2 and S
1 are output from the flip-flops FF'2,
Connected to D input of FF'1.

The outputs Q of the flip-flops FF'2 and FF'1 are respectively connected to the inputs D of the flip-flops P2 and P1.
Is input to The flip-flops FF'2 and FF'1 operate using CLK as a clock signal. The flip-flops P2 and P1 operate using PCLK as a clock signal,
The output Q of the flip-flop P2 repeats data corresponding to the second bit of the input serial data as a parallel output PO2, and the output Q of the flip-flop P1 is
Data corresponding to the first bit of the input serial data is repeatedly output as a parallel output PO1.

The operation of the internal configuration of FIG. 1 will be described below with reference to the timing chart of FIG. All operations are based on the rising edge of the CLK input. Also, the serial data input S
DIN includes serial data 1-1, 1-2, 2-1 and
2-2, 3-1, 3-2, 4-1, 4-2,... Are sequentially input.

When the serial data input SDIN is FF2, F
The output of the flip-flop FF2 is shifted by the flip-flop FF'2 at the timing when the output FCLK of the toggle F / F (T1) is "1".
Is latched by the flip-flop FF'1. PC
If LK is '0', flip-flops FF'2, F
F′1 holds the previous value, so the flip-flop FF ′
2, the output change point of FF'1 is always synchronized with the falling edge of PCLK. Flip-flop FF'2 output, FF'1
The output is latched at the rising edge of PCLK by flip-flops P2 and P1, and output to the outside as outputs PO2 and PO1. Also, PCLK is output to the outside.

FIG. 3 shows a 1 → 2 ⁿ data S / P conversion circuit using the above 1 → 2 S / P conversion unit. FIG.
As shown in FIG.
The input CLK associated with N is changed from 1 to 2 every S / P conversion process.
The S / P conversion unit divides the frequency by two, outputs the data to the next two 1 → 2 S / P conversion units together with the two parallel data PO1 and PO2, and performs multistage connection. The 1 → 2 ⁿ data S / P conversion circuit shown in FIG. 3 performs 16-bit serial / parallel conversion, and has fifteen 1 → 2 S / P conversion units 3 having the same configuration as that shown in FIG.
1-1, 32-1, 32-2, 33-1 to 34-4, 3
4-1 to 34-8.

As shown in FIG. 3, the following effects can be obtained by adopting a 1 → 2 S / P conversion unit multistage connection configuration.

Focusing on the fan-out of the PCLK output of the 1 → 2 S / P conversion unit, the number of F / F · CLK inputs connected to PCLK is always a constant value (the number of inputs 14 ( = 4 (in the own circuit) +5 (next stage circuit) × 2 (number of next stage units)), and there is no CLK output having a large fan-out even if the parallel number (2 ⁿ ) increases. , It is possible to prevent racing due to an increase in CLK skew.

Also, since the CLK frequency is reduced to 毎 every time the S / P conversion process is performed and the 2 ⁿ frequency ^dividing counter and the decoder are not required, the parallel data is latched by forming a critical path. -It is possible to prevent a malfunction caused by jumping of the enable pulse.

As another embodiment of the present invention, the 1 → 2 S / P conversion unit constituting the S / P conversion circuit is changed to a 1 → X S / P conversion unit (X is an integer of 2 or more). Is also possible. For example, when a 1 → 3 S / P conversion unit is used, a 1 → 3 ⁿ S / P conversion circuit can be created.

[0020]

As described above, according to the present invention,
Data S / S that reduces the CLK skew compared to the prior art and prevents the formation of a critical path when the CLK speed is high
A P conversion circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a configuration of a data S / P conversion unit which is a basic configuration unit of a data S / P conversion circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a configuration of an embodiment of a data S / P conversion circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a configuration of a conventional data S / P conversion circuit.

[Explanation of symbols]

31-1, 32-1 to 32-2, 33-1 to 33-4
34-1 to 34-8 ... 1 → 2 S / P conversion unit FF1, FF2, FF'1, FF'2, T1 ... flip-flop S1, S2 ... selector

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-11-98101 (JP, A) JP-A-3-26107 (JP, A) JP-A-63-46833 (JP, A) JP-A-1- 311622 (JP, A) JP-A-1-194533 (JP, A) JP-A-3-97329 (JP, A) JP-A-6-268623 (JP, A) JP-A-9-55667 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 9/00

Claims (4)

(57) [Claims] A first storage unit that divides an input clock signal and supplies it as a clock signal to a timing adjustment storage unit of an output stage, and outputs the same as a clock signal of a next unit; X stages (X is an integer of 2 or more) shifted in accordance with the input clock signal, X second storage units connected in cascade, and outputs of the X second storage units according to the input clock signal X pieces of third storage means which respectively hold at the same timing, and X pieces of timing adjustment storage which hold the outputs of the X pieces of third storage means at the same timing and output to the next unit means and, 1 / X serial composed - parallel conversion unit, a plurality, n stages (n is a natural number) will be connected, serial 1 / X ⁿ - and characterized by performing parallel conversion
And the third storage means is supplied from the first storage means
First data holding means operating in synchronization with a clock signal
And second data operating in synchronization with the input clock signal
Data comprising: holding means.
S / P conversion circuit. 2. The data S / P conversion circuit according to claim 1, wherein each of said storage means is constituted by using a flip-flop. 3. The data S / P converter according to claim 1, wherein the 1 / X serial-parallel conversion unit is a シ リ ア ル serial-parallel conversion unit that performs シ リ ア ル serial-parallel conversion. circuit. 4. The data S / P converter according to claim 1, wherein the first data holding means is constituted by using a selector, and the second data holding means is constituted by using a flip-flop. circuit.