JPH06224746A - Synchronous counter circuit - Google Patents

Abstract

PURPOSE:To improve the available highest frequency by latching each output signal from a ripple down-counter with a counter output at a lower-order by required bits. CONSTITUTION:A most significant bit output QN from an asynchronous ripple down-counter 1 is latched by a 1st stage D FF latch circuit 2-1 based on an output QN-2 lower by two bits, and latched by a circuit 2-2 based on an output QN-3 lower by one bit than the output QN-2. The similar operation is executed by latch circuits 2-1-2-(N-2), an UP output is outputted from a final stage latch circuit 2-(N-1) and the entire circuit acts like a synchronous UP counter. Through the constitution above, a delay time by one stage of the FF being a component of the counter circuit is remarkably smaller than that of plural D FFs, exclusive OR circuits or OR circuits operated at the edge of the same clock and the available highest frequency is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous counter circuit used in a semiconductor integrated circuit which operates at high speed.

[0002]

2. Description of the Related Art Conventionally, as a synchronous counter circuit,
A configuration as shown in FIG. 7 is known. In this conventional example, several gates including exclusive OR circuits 112, 113, 114 and OR circuits 123, 124 are provided between a plurality of D-flip-flops 101-104 which operate at the same clock signal CK edge. It has a configuration with a circuit interposed,
Count outputs Q1 to Q4 are output from the Q outputs of the D-flip-flops 101 to 104.

[0003]

By the way, in the synchronous counter circuit having the above-described structure, the maximum operating frequency is set between the delay time of one D-flip-flop and each D-flip-flop. However, there is a problem that the delay time of these gate circuits increases as the number of higher bits increases.

The present invention has been made in order to solve the above problems in the conventional synchronous counter circuit, and an object thereof is to provide a synchronous counter circuit capable of improving the operating speed as much as possible. .

[0005]

In order to solve the above-mentioned problems, the present invention latches an asynchronous down counter circuit and each count output signal of the down counter circuit by a 2-bit lower count output signal. The latch circuit of the first stage, the intermediate latch circuit which latches the output of the latch circuit of the preceding stage with the count output signal which is 1 bit lower than the latch circuit of the preceding stage, and the output of the latch circuit of the preceding stage by the input clock signal of the down counter circuit The latch circuit at the final stage of latching constitutes a synchronous up counter circuit, and the asynchronous down counter circuit is replaced with an asynchronous up counter circuit to constitute a synchronous down counter circuit.

In the synchronous up-counter circuit or the down-counter circuit thus constructed, the count output signal of the asynchronous down-counter circuit or the up-counter circuit is latched by the count output signal of 2 bits before in the latch circuit of the first stage. Then, the operation of latching the output of the latch circuit of the first stage with the count output signal of one bit before in the intermediate latch circuit is repeated, and finally, the input clock signal of the down counter circuit or the up counter circuit in the latch circuit of the final stage. The output of the latch circuit at the previous stage is latched with. By performing this operation for all the bits, a synchronous up counter circuit operation or down counter circuit operation can be obtained.

As described above, the conventional synchronous counter circuit has a structure in which several gate circuits including an exclusive OR circuit are interposed between D-flip-flops which operate at the same clock signal edge. Compared to
Since the synchronous counter circuit according to the present invention is configured as described above, the maximum operating frequency is determined by the delay time of two stages of flip-flops forming the asynchronous counter circuit. Therefore, by configuring the delay time for one flip-flop to be smaller than the delay time of several gate circuits including an exclusive OR circuit or an OR circuit,
The maximum operating frequency can be improved.

[0008]

EXAMPLES Next, examples will be described. FIG. 1 is a block diagram showing one bit of a basic embodiment of a synchronous counter circuit according to the present invention. In the figure, reference numeral 1 is an asynchronous down counter circuit, and the count output Q _N of the most significant bit is latched by a count output Q _N-2 two bits before in a latch circuit 2-1 and The output is latched by the count output Q _N-3 one bit before in the latch circuit 2-2 in the next stage. Hereinafter, the latch circuits that repeatedly perform the same operation are cascade-connected, and in the final stage latch circuit 2- (N-1), the output of the previous stage latch circuit 2- (N-2) is input to the down counter circuit 1. It is configured to be latched by the clock signal CK. By providing such a latch circuit configuration for all bits, a synchronous up counter circuit is configured.

As described above, the synchronous up-counter circuit thus constructed has the asynchronous down-counter circuit 1
The maximum operating frequency can be improved by making the delay time for one stage of the flip-flops that composes the above-mentioned smaller than the delay time of the gate circuit interposed between the conventional flip-flops.

Further, by replacing the asynchronous down counter circuit with an asynchronous up counter circuit, a synchronous down counter circuit which can be operated at a higher speed than the conventional one can be constructed.

Next, a specific embodiment of the present invention will be described with reference to FIG. This embodiment constitutes a synchronous up counter circuit. In the figure, 11 to 14 are D-flip-flops each having an XQ output (inverted output of the Q output) connected to a D input and performing a toggle operation. Clock signals to these D-flip-flops 11 to 14 are D-flip-flops. −
The flip-flop 11 is supplied from the clock signal CK input terminal, and the D-flip-flops 12 to 14 are respectively supplied from the Q outputs of the D-flip-flops 11 to 13 to form the ripple down counter circuit 10. .

The Q output of the D-flip-flop 11 of the least significant bit of the down counter circuit 10 becomes the output U1 of the first bit of the synchronous up counter circuit as it is and the D bit of the second bit of the down counter circuit 10. The Q output (a) of the flip-flop 12 is connected to the D input of the D-flip-flop 42 which outputs the output U2 from the Q output. The clock signal of the D-flip-flop 42 is supplied from the clock signal CK input terminal. Therefore, the output timing of the output U2 is
It coincides with the timing of the output U1.

Next, the Q output (a) of the third bit D-flip-flop 13 of the down counter circuit 10 is connected to the D input of the D-flip-flop 33. And this D
-The output U1 as the clock signal of the flip-flop 33
Is input, and its Q output (c) is output U3 D
Connected to the D input of flip-flop 43. And
The clock signal of the D-flip-flop 43 is also supplied from the clock signal CK input terminal.

Further, the Q output (D) of the fourth bit D-flip-flop 14 of the down counter circuit 10 is connected to the D input of the D-flip-flop 24, and the clock signal of this D-flip-flop 24 is D-flip flop 12
Is supplied from the Q output (a), and the Q output (e) is connected to the D input of the D-flip-flop 34. The output U1 is input as the clock signal of the D-flip-flop 34, and the Q output (f) of the D-flip-flop 34 outputs the output U4 from the Q output and is supplied from the clock signal CK input terminal. D operated by clock signal
It is connected to the D input of the flip-flop 44 and constitutes a synchronous up counter circuit.

Next, the operation of the synchronous up-counter circuit thus constructed will be described with reference to the timing chart shown in FIG. First, when the reset signal CL becomes “H” level and the clock signal CK is supplied, the down counter circuit 10 changes from “0000” to “11”.
11 "and" 1110 "are started to count down (see waveforms d, a, a, and U1), and the count output of the down counter circuit 10 is changed by two stages before in order to convert the down count signal into an up count signal. The D output of the D-flip-flop 14 is repeatedly latched by the Q output of the D-flip-flop, and is finally latched by the input clock signal CK. -In the flip-flop 24, the Q output (a) of the second bit D-flip-flop 12 is latched, and further the Q output (e) of the D-flip-flop 24 is
The D-flip-flop 34 latches with the Q output of the D-flip-flop 11 of the first bit. Finally, the Q output (F) of the D-flip-flop 34 is latched by the clock signal CK which is the clock input of the D-flip-flop 11 of the first bit of the down counter circuit 10.

In this way, the down counter circuit 1
The first bit is U1, the second bit is A → U2, the third bit is A → U → U3, and the fourth bit is E → O → CA → U4. All of them should be synchronized with the input clock signal CK at the end. And the up-count operation is performed.

In the synchronous up-counter circuit having such a configuration, even when the number of stages is increased, the timing critical portion is changed only by the delay of two D-flip-flops. Therefore, a multi-bit synchronous up-counter circuit that can operate at high speed can be configured as long as the circuit scale is allowed.

Next, another specific embodiment is shown in FIG.
This embodiment constitutes a synchronous down counter circuit, and its operation timing is shown in FIG. The difference of the configuration of this embodiment from the embodiment shown in FIG. 2 is that the ripple down counter circuit 10 of the embodiment shown in FIG. 2 is replaced with a ripple up counter circuit 50, and all D-flip-flops 51 to 54 ,. The point is that 64, 73, 74, 82, 83, 84 are configured to be preset rather than reset. With this configuration, a synchronous down counter circuit that performs the same operation as that of the embodiment shown in FIG. 2 can be obtained.

FIG. 6 is a diagram showing a configuration example in which the ripple down counter circuit 10 in the embodiment shown in FIG. 2 is changed to a synchronous down counter circuit 90. As in this configuration example, the counter portion operates without being limited to the ripple counter circuit, but in the case of this configuration example, the maximum operating frequency is determined by the synchronous down counter circuit 90. There is no merit.

Similarly, even if the ripple up counter circuit 50 in the embodiment shown in FIG. 4 is changed to a synchronous up counter circuit, the same operation is performed.

[0021]

As described above on the basis of the embodiments,
According to the present invention, the counting operation can be performed at a frequency higher than the frequency at which the conventional synchronous counter circuit can operate, and the maximum frequency that can be used in the same device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing one bit of a basic embodiment of a synchronous counter circuit according to the present invention.

FIG. 2 is a block diagram showing a specific embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a block diagram showing another specific example of the present invention.

5 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 6 is a block configuration diagram showing a configuration example in which a part of the configuration of the embodiment shown in FIG. 2 is changed.

FIG. 7 is a block diagram showing a configuration example of a conventional synchronous counter circuit.

[Explanation of symbols]

1 Asynchronous down counter circuit 2-1, 2-2, ... 2- (N-1) latch circuit 10 Ripple down counter circuit 11 to 14, 24, 33, 34, 42, 43, 44 D-flip-flop 50 ripple up counter circuit

Claims (2)

[Claims] 1. An asynchronous down counter circuit, a first-stage latch circuit for latching each count output signal of the down counter circuit with a 2-bit lower count output signal, and an output of a preceding latch circuit from a preceding latch circuit. Synchronous type characterized by comprising an intermediate latch circuit for latching a 1-bit lower count output signal and a final stage latch circuit for latching the output of the preceding latch circuit with the input clock signal of the down counter circuit Up counter circuit. 2. An asynchronous up-counter circuit, a first-stage latch circuit that latches each count output signal of the up-counter circuit with a 2-bit lower-order count output signal, and an output of the previous-stage latch circuit from a previous-stage latch circuit. Synchronous type characterized by comprising an intermediate latch circuit for latching a 1-bit lower count output signal and a final-stage latch circuit for latching the output of the preceding latch circuit with the input clock signal of the up-counter circuit Down counter circuit.