KR19990005465A - Test circuit of semiconductor chip - Google Patents

Abstract

The present invention relates to a test circuit of a semiconductor chip that can be performed by converting the operation and the test of the chip according to the test and operation mode signal input from the outside, the second by the test clock signal input through the first input terminal A delay unit for delaying the operation / test mode signal input through the input terminal; First synchronizing means for synchronizing the operation / test clock signal with the operation clock signal in accordance with the test clock signal; Second synchronizing means for synchronizing the test clock signal with the operation clock signal by the operation clock signal input through the third input terminal; And an operation clock signal input to the one input terminal and a test clock signal input to the type force terminal through the first synchronization means by the output signal of the second synchronization means input to the selection terminal. A first and a second multiplexer for outputting to a second output stage, respectively.

Description

Test circuit of semiconductor chip

The present invention relates to a test circuit of a semiconductor chip, and more particularly to a test circuit of a semiconductor chip that can be performed by converting the operation and test of the chip with each other according to a test and an operation mode signal input from the outside.

In general, the test circuit for the chip was published in 1990 by IEEE std. Various proposals have been made according to the standard test method established by 1149. 1 The most widely used test circuit is the boundary scan method, which is intended to be compatible with test control signals and other manufacturing chips such as data myth TTL and CMOS. . In case of testing by boundary scan method, it is controlled by separate test clock rather than normal pulse of operation clock signal. Therefore, circuits should be designed to allow the test source to enter the test state from the normal operating state and vice versa to convert the source of the clock from the operating clock to the test clock and vice versa.

However, in the conventional test circuit as described above, a problem occurs when the circuit in the test state of the chip is converted from the operation clock to the test clock, and the conversion of the clock signal is determined by an external control signal. If the control signal is not synchronized with the operation clock, an unwanted clock pulse may occur, resulting in an uncertain or incorrect result of the circuit.

Therefore, the present invention is to solve the above problems, the test circuit of the semiconductor chip that can reduce the test cost by stably converting the operation clock signal and the test clock signal of the chip by the test and operation mode signal to each other The purpose is to provide.

1 is a test circuit diagram of a semiconductor chip according to an embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

10: first synchronization means 20: delay unit

30: second synchronizing means 40, 50: first and second multiplexers

The test circuit of the semiconductor chip of the present invention for achieving the above object includes a delay unit for delaying the operation / test mode signal input through the second input terminal by the test clock signal input through the first input terminal; First synchronizing means for synchronizing the operation / test clock signal with the operation clock signal in accordance with the test clock signal; Second synchronizing means for synchronizing the test clock signal with the operation clock signal by the operation clock signal input through the third input terminal; And an operation clock signal input to the one input terminal and a test clock signal input to the type force terminal through the first synchronization means by the output signal of the second synchronization means input to the selection terminal. A first and a second multiplexer for outputting to a second output stage, respectively.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1, in the test circuit of the semiconductor chip of the present invention, the operation / test mode signal S / TMD input through the input terminal IN3 by the test clock signal TCLK input through the input terminal IN2. A delay unit 10 for delaying the delay signal, first synchronization means 10 for synchronizing the operation / test clock signal S / TMD with the operation clock signal SCLK according to the test clock signal TCLK, and an input terminal. Second synchronization means 30 for synchronizing the test clock signal TCLK with the operation clock signal SCLK by the operation clock signal / SCLK inverted through IN1 and inputted to the selection terminal SL. The operation clock signal SCLK input to the one input terminal A by the output signal of the second synchronization means 30 and the test clock signal input to the type force terminal B through the first synchronization means 20 ( TCLK) to obtain the first and second multiplexers 40 and 50 for outputting to the first and second output terminals OUT1 and OUT2 through the output terminal X roll, respectively. Compared.

The delay unit 10 includes first delay means 11 for firstly delaying the operation / test mode signal S / TMD by the test clock signal / TCLK inverted through the inverter IV11, and operation / Second delay means 12 for secondarily delaying the test mode signal S / TMD.

The first delay unit 11 includes a flip-flop 11-1 and a clock terminal CLK having a clock terminal CLK connected to the output terminal of the inverter IV11 and an input terminal D connected to the input terminal IN2. Is connected to the output terminal of the inverter IV11, and the input terminal D is composed of a flip-flop 11-2 connected to the output terminal Q of the flip-flop 11-1.

The second delay means 12 has one input terminal connected to the input terminal IN3, and the exclusive force gate connected to the output terminal Q of the flip-flop 11-2 of the first delay means 11 is connected to the input terminal IN3. (12-1) is provided.

The first synchronizing means 20 has one input terminal connected to an input terminal IN2, and a type force terminal connected to an output terminal of the delay gate 10 connected to the output terminal of the exclusive noar gate 12-1. Equipped.

The second synchronizing means 30 includes a flip-flop 31-1 having a clock terminal CLK connected to an output terminal of the inverter IV31, an input terminal D connected to an input terminal IN2, and a clock terminal CLK. Is connected to the output terminal of the inverter IV31, and the input terminal D is composed of a flip-flop 31-2 connected to the output terminal Q of the flip-flop 31-1.

The operation of the test circuit of the semiconductor chip of the present invention having the structure as described above is as follows.

First, when the operation / test clock signal S / TMD in the low state is input through the input terminal IN3 to operate the chip, the second synchronizing means 30 transmits the test clock signal TCLK to the operation clock signal SCLK. After synchronization, the synchronous signal is input to the select terminals SL of the first and second multiplexers 40 and 50, respectively, and the first multiplexer 40 then operates the operation clock signal SCLK to operate the chip. ) Is selected and output through the output terminal OUT1, and likewise, the second multiplexer 50 also selects the operation clock signal SCLK and outputs it through the output terminal OUT2 to operate the chip.

Next, when the operation / test clock signal S / TMD in the high state is input through the input terminal IN3 to test the chip, the delay unit 10 delays the operation / test clock signal S / TMD so as to delay the operation / test clock signal S / TMD. The first gate is input to one input terminal of the AND gate 20-1 of the synchronization unit 20, and the AND gate 20-1 of the first synchronization unit 20 is directly input to the type force terminal through the input terminal IN2. The first and second multiplexers are configured to logic-end the operation / test clock signal S / TMD and the signal input from the delay unit 10 to synchronize the operation / test clock signal S / TMD synchronized with the operation clock signal SCLK. Output as (40, 50).

Subsequently, the first multiplexer 40 selects the test clock signal TCLK to test the chip and outputs it through the output terminal OUT1, and likewise, the second multiplexer 50 also tests the test clock signal TCLK to test the chip. Select) and output it through the output terminal (OUT2).

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, in the test circuit of the semiconductor chip of the present invention, the internal control signal for converting the clock source is synchronized with the operation clock signal input from the outside, thereby converting the chip from the operating state to the test mode or vice versa. It provides an effect that can solve the problem that can be caused by unwanted clock pulse that can occur.

Claims (6)

A delay unit for delaying the operation / test mode signal input through the second input terminal by the test clock signal input through the first input terminal; First synchronizing means for synchronizing the operation / test clock signal with an operation clock signal in accordance with the test clock signal; Second synchronization means for synchronizing the test clock signal with the operation clock signal by the operation clock signal input through a third input terminal; And an operation clock signal input to one input terminal by an output signal of the second synchronization means input to the selection terminal. And first and second multiplexers for selecting the test clock signal input to the type force terminal through the first synchronizing means and outputting the test clock signal to the first and second output terminals, respectively. . 2. The apparatus of claim 1, wherein the delay unit comprises: first delay means for firstly delaying the operation / test mode signal by the test clock signal inverted through an inverter; And second delay means for secondarily delaying the operation / test mode signal. 3. The apparatus of claim 2, wherein the first delay unit comprises: a first flip flop having a clock terminal connected to an output terminal of the inverter and an input terminal connected to an input terminal; And a second flip flop having a clock terminal connected to an output terminal of the inverter and an input terminal connected to an output terminal of the flip flop. The test circuit according to claim 2, wherein the second delay means includes an exclusive noar gate having one input terminal connected to the input terminal and a type force terminal connected to the output terminal of the first delay means. The test circuit of claim 1, wherein the first synchronizing means comprises an end gate having one input terminal connected to the first input terminal and a type force terminal connected to an output terminal of the delay unit. 2. The apparatus of claim 1, wherein the second synchronizing means comprises: a first flip-flop having a clock terminal connected to an output terminal of the inverter and an input terminal connected to the first input terminal; And a second flip-flop having a clock terminal connected to an output terminal of the inverter and an input terminal connected to an output terminal of the first flip-flop.