CN110912549A

CN110912549A - Serial-parallel conversion circuit, driving method thereof and display panel

Info

Publication number: CN110912549A
Application number: CN201911234249.8A
Authority: CN
Inventors: 王志东; 周丽佳; 张俊瑞; 朱学辉; 何宗泽
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2019-12-05
Filing date: 2019-12-05
Publication date: 2020-03-24

Abstract

The application discloses a serial-parallel conversion circuit, a driving method thereof and a display panel, which are used for prolonging data latching time, increasing time sequence redundancy to ensure correct data transmission, relieving tension of time sequences, reducing difficulty of time sequence design and enhancing stability of high-frequency data transmission. An embodiment of the present application provides a serial-parallel conversion circuit, including: the device comprises a sampling pulse signal generating module and a plurality of data latching modules; the number of the data latch modules is equal to the number of data bits needing parallel transmission; the sampling pulse signal generating module is provided with a plurality of output ends which are correspondingly coupled with the control ends of the data latching modules one by one; the sampling pulse signal generation module is used for: dividing an input clock signal according to a reset signal, generating a plurality of sampling pulse signals and respectively outputting the sampling pulse signals to each data latch module which is coupled with the sampling pulse signals; each data latch module is used for: and latching and outputting the data signal in the input serial data signal according to the sampling pulse signal and the reset signal.

Description

Serial-parallel conversion circuit, driving method thereof and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a serial-parallel conversion circuit, a driving method thereof, and a display panel.

Background

Currently, the data transmission mode includes serial data transmission and parallel data transmission, the serial data transmission is to transmit the code elements forming data and characters bit by bit according to time sequence, and the parallel data transmission is to transmit the data and character code elements of fixed number of bits to the receiving end at the same time. Serial-to-parallel conversion is a technique for accomplishing conversion between these two transmission modes. The serial-parallel conversion circuit in the prior art utilizes a plurality of triggers to form a shift register in series for serial-parallel conversion. The serial-to-parallel conversion circuit shown in fig. 1 includes four flip-flops 1 connected in series, the input terminal of the first flip-flop 1 inputs a serial data signal SI, the input terminals D of the remaining flip-flops 1 are connected to the output terminal O of the previous flip-flop 1, the control terminal C of the flip-flop 1 inputs a clock signal CLK, the reset signal terminal R of the flip-flop inputs a reset signal RST, and the output terminals of the flip-flop 1 output sampling data O0, O1, O2, and O3. Fig. 2 shows a timing diagram of the serial-to-parallel conversion circuit shown in fig. 1, all flip-flops 1 in fig. 1 are controlled by one clock pulse, each time a clock signal triggering edge arrives, all stored data is shifted to the right by one bit, and as shown in fig. 2, when a fourth clock arrives, sampling data of four flip-flops are output together, so that the purpose of serial-to-parallel conversion is achieved. However, the design that a plurality of flip-flops are connected in series and controlled by one clock pulse requires that the sampling data must be output in the fourth clock, the data stabilization period available for reading of each group of conversion data is only one clock cycle, and data conversion errors are more prone to occur during high-frequency data transmission.

In summary, when serial data is converted into parallel data, the serial-to-parallel conversion circuit provided in the prior art only has a time of one clock cycle to output the parallel data, and has no sufficient timing redundancy, which increases the complexity of timing design and the possibility of data conversion errors during high-frequency data transmission, thereby causing system function failure.

Disclosure of Invention

The embodiment of the application provides a serial-parallel conversion circuit, a driving method thereof and a display panel, which are used for prolonging data latching time, increasing time sequence redundancy to ensure correct data transmission, relieving tension of time sequences, reducing difficulty of time sequence design and enhancing stability of high-frequency data transmission.

An embodiment of the present application provides a serial-to-parallel conversion circuit, where the serial-to-parallel conversion circuit includes: the device comprises a sampling pulse signal generating module and a plurality of data latching modules;

the number of the data latch modules is equal to the number of data bits needing parallel transmission; the sampling pulse signal generating module is provided with a plurality of output ends which are correspondingly coupled with the control ends of the data latching modules one by one;

the sampling pulse signal generation module is used for: dividing an input clock signal according to a reset signal, generating a plurality of sampling pulse signals and respectively outputting the sampling pulse signals to each data latch module which is coupled with the sampling pulse signals;

each data latch module is used for: and latching and outputting a data signal in the input serial data signal according to the sampling pulse signal and the reset signal.

The serial-to-parallel conversion circuit provided by the embodiment of the application divides a clock signal by using a sampling pulse signal generation module to generate a plurality of different sampling pulse signals which are respectively output to each data latch module. And each data latch module inputs a serial data signal, and the data latch modules latch the input serial data signals under the control of the sampling pulse signals, namely different data latch modules latch the input serial data signals under the control of different sampling pulse signals. Therefore, different data latch modules are not controlled by the same clock signal any more, and current data cannot be changed when latched in each data latch module before new data is written in under the control of different sampling pulse signals.

Optionally, the data latch module includes: the first NAND gate is connected with the first transmission gate;

the input end of the first transmission gate is used for receiving the serial data signal, the first control end of the first transmission gate and the second control end of the second transmission gate are used for receiving the sampling pulse signal, and the second control end of the first transmission gate and the first control end of the second transmission gate are used for receiving an inverted signal opposite to the sampling pulse signal; the output end of the first transmission gate is coupled with the first input end of the first NAND gate;

the second input end of the first nand gate is used for receiving the reset signal, and the output end of the first nand gate is coupled with the input end of the first not gate;

the output end of the first NOT gate is coupled with the input end of the second transmission gate, and the output end of the second transmission gate is coupled with the first input end of the first NAND gate;

the output end of the first NOT gate is used for outputting the serial data signal.

According to the serial-parallel conversion circuit provided by the embodiment of the application, when the sampling pulse signal is at a high level, data is written into the data latch module, and when the sampling pulse signal is at a low level, the written data is latched in the data latch module until the sampling pulse signal is changed to be at the high level again, new data is written into the data latch module. The current data is latched in the data latch block without change until new data is written to the data latch block. Compared with the prior art that different triggers use the same clock for control and only one clock period is reserved for outputting latched data, the serial-parallel conversion circuit provided by the embodiment of the application can prolong the time for latching the data under the control of the sampling pulse signal, so that the serial-parallel conversion circuit provided by the embodiment of the application has enough time sequence redundancy to ensure the correct output of the data, the difficulty of time sequence design can be reduced, and the stability of high-frequency data transmission is improved.

Optionally, the sampling pulse signal generating module includes: the device comprises a starting module, a high-low level conversion module, an alternative data selection module and a plurality of cascaded combinational logic modules;

the input end of the starting module is used for receiving the clock signal; the reset signal end of the starting module is used for receiving the reset signal, and the output end of the starting module is coupled with the first input end of the alternative data selection module; the starting module is used for: generating a starting signal according to the clock signal and the reset signal and outputting the starting signal;

the reset signal end of the high-low level conversion module is configured to receive the reset signal, the input end of the high-low level conversion module is coupled to the output end of any one of the combinational logic modules except the combinational logic module at the last stage, the output end of the high-low level conversion module is coupled to the control end of the alternative data selection module, and the high-low level conversion module is configured to: generating and outputting a level switching signal according to the sampling pulse signal and a reset signal;

a second input terminal of the one-of-two data selection module is coupled to an output terminal of the last stage of the combinational logic module, and the one-of-two data selection module is configured to: according to the level switching signal, selectively outputting the starting signal or the sampling pulse signal as a segmentation control signal;

the clock signal end of the combinational logic module is used for receiving the clock signal; the input end of the first-stage combinational logic module is coupled with the output end of the alternative data selection module, and the input ends of the other combinational logic modules except the first-stage combinational logic module are coupled with the output end of the last-stage combinational logic module; the output end of the combinational logic module is coupled with the control end of the data latch module;

the first level of the combinational logic module is configured to: selecting and outputting a pulse sampling or continuous low level signal of the clock signal as the sampling pulse signal according to the clock signal and the division control signal output by the alternative data selection module; the other combinational logic modules except the first-level combinational logic module are used for: selecting a pulse sampling or continuous low level signal of the clock signal to be output as the sampling pulse signal according to the clock signal and the sampling pulse signal output by the combinational logic module at the previous stage;

the number of the combinational logic modules is equal to the number of the data latch modules.

Optionally, the starting module includes: the first NAND gate, the second NAND gate, the first AND gate and the second NOT gate;

a first input terminal of the first or gate is configured to receive the clock signal, a second input terminal of the first or gate is coupled to an output terminal of the second not gate, and an output terminal of the first or gate is coupled to a first input terminal of the second not gate;

a second input end of the second nand gate and a second input end of the first and gate are used for receiving reset signals, and an output end of the second nand gate is coupled with an input end of the second not gate and an input end of the first and gate;

the output end of the first and gate is coupled to the first input end of the alternative data selection module, and the output end of the first and gate is used for outputting the starting signal.

Optionally, the high-low level conversion module includes: a first nor gate, a third nor gate, and a fourth nor gate;

a first input terminal of the first nor gate is used for receiving the reset signal; a second input terminal of the first nor gate is coupled to an output terminal of any one of the combinational logic blocks except the combinational logic block of the last stage; a third input of the first NOR gate is coupled to an output of the third NOR gate; an output of the first NOR gate is coupled to inputs of the third NOR gate and the fourth NOR gate;

the output end of the fourth not gate is used for outputting the level switching signal;

the alternative data selection module comprises: a first selector;

a first input terminal of the first selector is coupled with an output terminal of the starting module;

the second input end of the first selector is coupled with the output end of the combinational logic module at the last stage;

a control terminal of the first selector is coupled with an output terminal of the fourth not gate;

the output end of the first selector is coupled with the input end of the first-stage combinational logic module and is used for outputting the division control signal.

Optionally, the combinatorial logic module comprises: a first module and a second module;

the clock signal ends of the first module and the second module are used for receiving the clock signal;

the input end of the first module is coupled with the output end of the alternative data selection module or the output end of the second module in the upper-stage combinational logic module;

the input end of the second module is coupled with the output end of the first module, and the output end of the second module is coupled with the control end of the data latch module; the output end of the second module in the last stage of the combinational logic module is coupled with the second input end of the alternative data selection module;

the first module is used for selectively outputting the clock signal or the continuous low level signal;

the second module is used for selectively outputting an inverted signal or a continuous low level signal of the clock signal.

Optionally, the combinational logic blocks of odd-numbered stages comprise a first block and the combinational logic blocks of even-numbered stages comprise a second block;

the input end of the first module is coupled with the output end of the alternative data selection module or the output end of the second module at the upper stage; the output end of the first module is coupled with the control end of the data latch module; the first module is used for selectively outputting the clock signal or the continuous low level signal;

the input end of the second module is coupled with the output end of the first module at the upper stage, and the output end of the second module is coupled with the control end of the data latch module; the second module is used for selectively outputting an inverted signal or a continuous low level signal of the clock signal;

and the output end of the second module at the last stage is coupled with the second input end of the alternative data selection module.

In the serial-to-parallel conversion circuit provided by the embodiment of the application, the combinational logic modules at odd-numbered stages include a first module, the combinational logic modules at even-numbered stages include a second module, and the sampling pulse signal generation module can increase the number of bits of data parallel transmission under the condition that the number of the first module and the second module is not changed.

Optionally, the first module comprises: a second or gate, a second selector, a fifth not gate, and a sixth not gate;

the second module includes: a third or gate, a third selector, and a seventh not gate;

a first input terminal of the second or gate is configured to receive the dividing control signal or the sampling pulse signal, and an output terminal of the second or gate is coupled to a control terminal of the second selector;

a first input terminal of the second selector is grounded, a second input terminal of the second selector is used for receiving the clock signal, and an output terminal of the second selector is coupled with a second input terminal of the second or gate and an input terminal of the fifth not gate; an output of the second selector is to: when the control end of the second selector inputs a low-level signal, the low-level signal is selected to be output, and when the control end of the second selector inputs a high-level signal, the clock signal is selected to be output;

an output of the fifth not gate is coupled to an input of the sixth not gate;

an output end of the sixth not gate is coupled with an input end of the third or gate, and an output end of the sixth not gate is used for selectively outputting the clock signal or the continuous low level signal; when the output end of the first module is coupled with the control end of the data latch module, the output end of the sixth not gate is coupled with the control end of the data latch module;

an output terminal of the third or gate is coupled to a control terminal of the third selector;

a first input terminal of the third selector is configured to receive a high level signal, a second input terminal of the third selector is configured to receive the clock signal, and an output terminal of the third selector is coupled to an input terminal of the seventh not gate; an output of the third selector is to: the high-level signal is selected to be output when the control end of the third selector inputs a low-level signal, and the clock signal is selected to be output when the control end of the third selector inputs a high-level signal;

an output terminal of the seventh not gate is coupled to the control terminal of the data latch module and the second input terminal of the third or gate; and the output end of the seventh NOT gate is used for selecting and outputting an inverted signal or a continuous low level signal of the clock signal.

The driving method of the serial-parallel conversion circuit provided by the embodiment of the application comprises the following steps:

inputting a clock signal and a reset signal to the sampling pulse signal generation module, controlling the sampling pulse signal generation module to divide the clock signal according to the reset signal, generating a plurality of sampling pulse signals, and outputting the sampling pulse signals to each data latch module which is coupled;

and inputting the reset signal, the sampling pulse signal and the serial data signal to the data latch module, and controlling the data latch module to latch and output the data signal in the input serial data signal according to the sampling pulse signal and the reset signal.

In the driving method of the serial-to-parallel conversion circuit provided by the embodiment of the application, the sampling pulse signal generation module is used for dividing the clock signal to generate a plurality of different sampling pulse signals, and the sampling pulse signals are respectively output to the data latch modules. And each data latch module inputs a serial data signal, and the data latch modules latch the input serial data signals under the control of the sampling pulse signals, namely different data latch modules latch the input serial data signals under the control of different sampling pulse signals. Therefore, different data latch modules are not controlled by the same clock signal any more, and current data cannot be changed when latched in each data latch module before new data is written in under the control of different sampling pulse signals.

The display panel provided by the embodiment of the application comprises the serial-parallel conversion circuit provided by the embodiment of the application.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art serial-to-parallel conversion circuit;

FIG. 2 is a timing diagram of the serial-to-parallel conversion circuit provided in FIG. 1;

fig. 3 is a schematic structural diagram of a serial-to-parallel conversion circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a data latch module according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of a sampling pulse signal generating module according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of another sampling pulse signal generation module according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a first logic combination module according to an embodiment of the present application;

fig. 8 is a timing diagram of a serial-to-parallel conversion circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another sampling pulse signal generation module according to an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another first logic combination module according to an embodiment of the present disclosure;

fig. 11 is a timing diagram of a sampling pulse signal generating module according to an embodiment of the present application;

fig. 12 is a schematic diagram of a driving method of a serial-to-parallel conversion circuit according to an embodiment of the present application.

Detailed Description

An embodiment of the present application provides a serial-to-parallel conversion circuit, as shown in fig. 3, the serial-to-parallel conversion circuit includes: a sampling pulse signal generating module 2 and a plurality of data latch modules 3;

the number of the data latch modules 3 is equal to the number of data bits needing parallel transmission; the sampling pulse signal generating module 2 is provided with a plurality of output ends which are correspondingly coupled with the control ends of the data latch modules one by one;

the sampling pulse signal generation module 2 is configured to: dividing an input clock signal CLK according to a reset signal RST, generating a plurality of sampling pulse signals CLK-S, and respectively outputting the sampling pulse signals CLK-S to each coupled data latch module 3;

each of the data latch modules 3 is configured to: and latching and outputting the data signal in the input serial data signal SI according to the sampling pulse signal CLK-S and the reset signal RST.

The serial-to-parallel conversion circuit shown in fig. 3 provided in the embodiment of the present application is exemplified by including 4 data latch modules 3, where the 4 data latch modules 3 are respectively: latch1, latch2, latch3, and latch 4. In FIG. 3, the sampling pulse signal generating module 2 receives the clock signal CLK and the reset signal RST, and divides the input clock signal CLK according to the reset signal RST to generate four sampling pulse signals CLK-S0, CLK-S1, CLK-S2, and CLK-S3. The control terminal C of latch1 receives CLK-S0, the control terminal C of latch2 receives CLK-S1, the control terminal C of latch3 receives CLK-S2, and the control terminal C of latch4 receives CLK-S3. The input terminals S of the latch1, the latch2, the latch3, and the latch4 all receive the same serial data signal SI, the reset signal terminals of the latch1, the latch2, the latch3, and the latch4 receive a reset signal, and the data latch modules 3 latch and output data signals that need to be latched among the input serial data signals SI under the control of the reset signal RST and the different sampling pulse signals CLK-S. The output terminals of latch1, latch2, latch3 and latch4 output signals of Q1, Q2, Q3 and Q4, respectively.

Optionally, as shown in fig. 4, the data latch module includes: a first transmission gate 31, a second transmission gate 32, a first nand gate 33, and a first not gate 34;

an input terminal of the first transmission gate 31 is configured to receive the serial data signal SI, a first control terminal of the first transmission gate 31 and a second control terminal of the second transmission gate 32 are configured to receive the sampling pulse signal CLK-S, and a second control terminal of the first transmission gate 31 and a first control terminal of the second transmission gate 32 are configured to receive an inverted signal CLK-SN opposite to the sampling pulse signal; an output of the first transmission gate 31 is coupled to a first input of the first nand gate 33;

a second input of the first nand gate 33 is configured to receive the reset signal RST, and an output of the first nand gate 33 is coupled to an input of the first not gate 34;

the output of the first not-gate 34 is coupled to the input of the second transmission gate 32, and the output of the second transmission gate 32 is coupled to the first input of the first nand gate 33;

the output of the first not gate 34 is used to output the serial data signal Q.

It should be noted that the serial data signal SI received by the input terminal of the first transmission gate includes the serial data signal Q at the output terminal of the first not gate.

As shown in fig. 4, when the sampling pulse signal CLK-S is a high level signal, the first transmission gate 31 is turned on, the second transmission gate 32 is turned off, and the serial data signal SI is written from the input terminal of the first transmission gate 31. When the sampling pulse signal CLK-S is a low level signal, the first transmission gate 31 is closed, the second transmission gate 32 is opened, and the input data is latched by the latch module, until the sampling pulse signal CLK-S is again a high level, the first transmission gate 31 is opened, the second transmission gate 32 is closed, and new data is written.

In specific implementation, when the reset signal RST is a high-level signal, if the input serial data signal SI is a high-level signal, and after the first transmission gate 31 is opened, the output end of the first nand gate 33 is at a low level, the output end of the first not gate 34 is at a high level, and after the first transmission gate 31 is closed and the second transmission gate 32 is opened, the input of the second transmission gate 32 is input and outputs a high-level signal, the output end of the first nand gate 33 is at a low level, and the output end of the first not gate 34 is at a high level, before the sampling pulse signal CLK-S is at a high level again, the second transmission gate is continuously opened, and the input high-level data is latched. If the input serial data signal SI is a low level signal, after the first transmission gate 31 is turned on, the output end of the first nand gate 33 is at a high level, the output end of the first not gate 34 is at a low level, after the first transmission gate 31 is turned off and the second transmission gate 32 is turned on, the input of the second transmission gate 32 outputs a low level signal, the output end of the first nand gate 33 is at a high level, the output end of the first not gate 34 is at a low level, before the sampling pulse signal CLK-S is again at a high level, the second transmission gate is continuously turned on, and the input low level signal data is latched.

According to the serial-parallel conversion circuit provided by the embodiment of the application, when the sampling pulse signal is at a high level, data is written into the data latch module, and when the sampling pulse signal is at a low level, the written data is latched in the data latch module until the sampling pulse signal is changed to be at the high level again, new data is written into the data latch module. The current data is latched in the data latch block without change until new data is written to the data latch block. Compared with the prior art that different triggers use the same clock for control, and only one clock period of time is reserved for outputting latched data, the serial-parallel conversion circuit provided by the embodiment of the application can prolong the time for latching data under the control of a sampling pulse signal, and the time for latching data can last for a plurality of clock periods, so that the serial-parallel conversion circuit provided by the embodiment of the application has enough time sequence redundancy to ensure the correct output of the data, the difficulty of time sequence design can be reduced, and the stability of high-frequency data transmission is improved.

Optionally, as shown in fig. 5, the sampling pulse signal generating module includes: the system comprises a starting module 21, a high-low level conversion module 22, an alternative data selection module 23 and a plurality of cascaded combinational logic modules 24;

the input end of the starting module 21 is used for receiving the clock signal CLK; the reset signal terminal of the start module 21 is configured to receive the reset signal RST, and the output terminal of the start module 21 is coupled to the first input terminal of the one-of-two data selecting module 23; the starting module 21 is configured to: generating and outputting a starting signal EN according to the clock signal CLK and the reset signal RST;

the reset signal terminal of the high-low level shift module 22 is configured to receive the reset signal RST, the input terminal of the high-low level shift module 22 is coupled to the output terminal of any one of the combinational logic modules 24 except the first combinational logic module 24 of the last stage, the output terminal of the high-low level shift module 22 is coupled to the control terminal of the one-of-two data selection module 23, and the high-low level shift module 22 is configured to: generating and outputting a level switching signal shift according to the sampling pulse signal CLK-S and a reset signal RST;

a second input terminal of the one-of-two data selection module 23 is coupled to an output terminal of the last stage of the combinational logic module 24; the alternative data selection module 23 is configured to: according to the level switching signal shift, selecting and outputting the starting signal EN or the sampling pulse signal CLK-S as a dividing control signal;

the clock signal terminal of the combinational logic module 24 is used for receiving the clock signal CLK; the input end of the first stage of the combinational logic module 24 is coupled to the output end of the alternative data selection module 23, and the input ends of the other combinational logic modules 24 except the first stage of the combinational logic module 24 are coupled to the output end of the last stage of the combinational logic module 24; the output terminal of the combinational logic block 24 is coupled to the control terminal of the data latch block;

the first level of the combinatorial logic module 24 is to: selecting and outputting a pulse sampling or continuous low level signal of the clock signal CLK as the sampling pulse signal CLK-S according to the clock signal CLK and the division control signal output by the alternative data selection module; the remaining combinational logic modules 24 other than the first level combinational logic module 24 are configured to: according to the clock signal CLK and the sampling pulse signal CLK-S output by the combinational logic module 24 of the previous stage, selecting to output a pulse sampling or continuous low level signal of the clock signal CLK as the sampling pulse signal CLK-S;

the number of combinational logic blocks 24 is equal to the number of data latch blocks.

In fig. 5, taking the example that the sampling pulse signal generating module outputs four sampling signals, the input terminal of the high-low level converting module 22 is coupled to the output terminal of the combinational logic module in the third stage, and of course, in specific implementation, the input terminal of the high-low level converting module 22 may also be coupled to the output terminal of the combinational logic module in the first stage or the combinational logic module in the second stage.

Optionally, as shown in fig. 5, the starting module 21 includes: a first or gate 211, a second nand gate 212, a first and gate 214, and a second not gate 213;

a first input of the first or gate 211 is configured to receive the clock signal CLK, a second input of the first or gate 211 is coupled to an output of the second not gate 213, and an output of the first or gate 211 is coupled to a first input of the second nand gate 212;

a second input of the second nand gate 212 and a second input of the first and gate 214 are configured to receive a reset signal RST, and an output of the second nand gate 212 is coupled to an input of the second not gate 213 and an input of the first and gate 214;

the output end of the first and gate 214 is coupled to the first input end of the one-out-of-two data selecting module 23, and the output end of the first and gate 214 is used for outputting the enable signal EN.

The starting module generates a starting signal of the current moment according to the clock signal, the reset signal and the signal output by the output end of the second NOT gate at the previous moment, and outputs the starting signal of the current moment.

Specifically, when the clock signal CLK signal received by the first input terminal of the first or gate 211 is a low level signal, the reset signal RST received by the second input terminals of the second nand gate 212 and the first and gate 214 is a low level signal, and the signal received by the second input terminal of the first or gate 211 is a low level signal (no input), the output terminal of the first or gate 211 outputs a low level signal, the output terminal of the second nand gate 212 outputs a high level signal, the output terminal of the second not gate 213 outputs a low level signal, and the enable signal EN output by the output terminal of the first and gate 214 is a low level signal.

When the reset signal RST changes to a high level and the clock signal CLK signal changes to a low level, that is, the signal received by the first input terminal of the first or gate 211 is a low level signal, the signals received by the second nand gate 212 and the second input terminal of the first and gate 214 are high level signals, and the signal received by the second input terminal of the first or gate 211 is a low level signal, the output terminal of the first or gate 211 outputs a low level signal, the output terminal of the second nand gate 212 outputs a high level signal, the output terminal of the second not gate 213 outputs a low level signal, and the enable signal EN output by the output terminal of the first and gate 214 changes from the low level signal to the high level signal.

Then, when the first high level of the clock signal CLK arrives, that is, the signal received by the first input terminal of the first or gate 211 is a high level signal, the signals received by the second input terminals of the second nand gate 212 and the first and gate 214 are high level signals, the signal received by the second input terminal of the first or gate 211 is a low level signal, the output terminal of the first or gate 211 outputs a high level signal, the output terminal of the second nand gate 212 outputs a low level signal, the output terminal of the second not gate 213 outputs a high level signal, and the enable signal EN output by the output terminal of the first and gate 214 changes from the high level signal to the low level signal.

When the reset signal RST maintains a high level signal and the output end of the second not gate 213 outputs a high level signal, no matter the clock signal input by the first or gate 211 is a high level signal or a low level signal, the output end of the first or gate 211 outputs a high level signal, the output end of the second nand gate 212 outputs a low level signal, the output end of the second not gate 213 outputs a high level signal, and the enable signal EN output by the output end of the first and gate 214 is a low level signal.

Optionally, as shown in fig. 5, the high-low level conversion module 22 includes: a first nor gate 221, a third nor gate 222, and a fourth nor gate 223;

a first input terminal of the first nor gate 221 is configured to receive the reset signal; a second input terminal of the first nor gate 221 is coupled to an output terminal of any of the combinational logic blocks 24 except the combinational logic block 24 of the last stage; a third input of the first nor gate 221 is coupled to an output of the third nor gate 222; an output of the first nor gate 221 is coupled to inputs of the third and fourth not

gates

222 and 223;

an output terminal of the fourth not gate 223 is configured to output the level switching signal shift;

the alternative data selection module 23 includes: a first selector 231;

a first input of the first selector 231 is coupled to an output of the start-up module 21;

a second input terminal of the first selector 231 is coupled to an output terminal of the last stage of the combinational logic module 24;

a control terminal of the first selector 231 is coupled to an output terminal of the fourth not gate 223;

an output terminal of the first selector 231 is coupled to an input terminal of the combinational logic block 24 of the first stage, and is used for outputting the division control signal.

It should be noted that the first nor gate 221 is a nor gate controlled by the reset signal RST, when the reset signal RST is at a low level, the reset signal is active, regardless of the signals input to the second input terminal and the third input terminal of the first nor gate 221, the output of the first nor gate 221 is at a high level, when the reset signal RST is at a high level, the reset signal is inactive, at this time, the first nor gate 221 has the same function as a nor gate having only two input terminals, and the signal output by the first nor gate 221 is controlled by the signals input to the second input terminal and the third input terminal thereof.

In specific implementation, when the serial-parallel conversion circuit is started, the reset signal RST is at a low level, that is, the first input terminal of the first nor gate 221 receives a low level signal, the signals received by the second input terminal and the third input terminal of the first nor gate 221 are at a low level (no input), the output terminal of the first nor gate 221 outputs a high level signal, the output terminals of the third nor gate 222 and the fourth not gate 223 output a low level signal, and the first selector 231 transfers the start signal EN to the first-stage combinational logic module 24 under the control of the low level switching signal Shift to control the generation of the sampling pulse signal CLK-S. When the level Shift signal Shift is at a high level, the first selector 231 transfers the output signal CLK-S3 of the last stage combinational logic block 24 back to the first stage combinational logic block 24 to enable the generation of the subsequent sampling pulse signal.

It should be noted that, when the serial-parallel conversion circuit is started, the reset signal RST is at a low level, the level switching signal Shift is at a low level, and the third input terminal of the first nor gate 221 is at a low level, and then, when the reset signal RST is at a high level and the sampling pulse signal CLK-S at the high level is input to the second input terminal of the first nor gate 221, the third output terminal of the first nor gate 221 outputs a low level signal, the output terminals of the third nor gate 222 and the fourth not gate 223 output high level signals, and the level switching signal Shift changes from the low level to the high level, and unless the reset signal RST changes to the low level again, the level switching signal Shift will keep at the high level all the time to control the first selector 231 to transfer the output signal CLK-S3 of the last-stage combinational logic block 24 back to the first-stage combinational logic block 24.

It should be noted that, in fig. 5, taking CLK-S1 as an example of the control signal for the first nor gate 221 in the high-low level switching module, in the implementation, it is only necessary to control the level switching signal Shift to be switched from low level to high level before the first CLK-S3 signal is transmitted back to the first selector 231, so that it is also possible to sample CLK-S0 or CLK-S2 as the signal received by the second input terminal of the first nor gate 221. That is, in the implementation, the output terminal of the first nor gate 221 may be coupled to the output terminal of any combinational logic block 24 except the first combinational logic block 24 of the last stage.

In specific implementation, the clock signal is divided, so that a pulse sampling signal corresponding to a high-level signal can be obtained in each clock cycle, a pulse sampling signal corresponding to a low-level signal can be obtained in each clock cycle, and certainly, pulse sampling signals corresponding to a high level and a low level respectively can be obtained in each clock cycle.

Next, taking an example of obtaining a pulse sampling signal corresponding to a low-level signal of a clock signal in each clock cycle, a sampling pulse signal generating module provided in the embodiment of the present application is exemplified.

Optionally, as shown in fig. 6, the combinational logic module 24 includes: a first module A and a second module B;

the clock signal terminals C of the first module A and the second module B are used for receiving the clock signal CLK;

the input end IN of the first module a is coupled to the output end of the alternative data selection module 23 or the output end OUT of the second module B IN the combinational logic module 24 at the previous stage;

the input end IN of the second module B is coupled with the output end OUT of the first module A, and the output end OUT of the second module B is coupled with the control end of the data latch module; the output end OUT of the second block B in the last stage of the combinational logic block 24 is coupled to the second input end of the one-OUT-of-two data selection block 23;

the first module A is used for selectively outputting the clock signal CLK or continuously outputting a low level signal;

the second module B is used for selectively outputting an inverted signal or a continuous low level signal of the clock signal CLK.

I.e. the signal output by the output of the second module B is taken as the sampling pulse signal CLK-S.

Optionally, as shown in fig. 7, the first module a includes: a second or gate 241, a second selector 242, a fifth not gate 243, and a sixth not gate 244;

the second module B includes: a third or gate 245, a third selector 246, and a seventh not gate 247;

a first input terminal of the second or gate 241 is configured to receive the dividing control signal or the sampling pulse signal, and an output terminal of the second or gate 241 is coupled to a control terminal of the second selector 242;

a first input terminal of the second selector 242 is connected to the ground GND, a second input terminal of the second selector 242 is configured to receive the clock signal CLK, and an output terminal of the second selector 242 is coupled to a second input terminal of the second or gate 241 and an input terminal of the fifth not gate 243; the output of the second selector 242 is configured to: a low level signal is selected to be output when a low level signal is input to the control terminal of the second selector 242, and the clock signal CLK is selected to be output when a high level signal is input to the control terminal of the second selector 242;

an output of the fifth not gate 243 is coupled to an input of the sixth not gate 244;

an output terminal of the sixth not gate 244 is coupled to an input terminal of the third or gate 245, and an output terminal of the sixth not gate is used for selectively outputting the clock signal CLK or the continuous low level signal;

an output terminal of the third or gate 245 is coupled to a control terminal of the third selector 246;

a first input terminal of the third selector 246 is configured to receive a high-level signal VDD, a second input terminal of the third selector 246 is configured to receive the clock signal CLK, and an output terminal of the third selector 246 is coupled to an input terminal of the seventh not gate 247; the output of the third selector 246 is for: the high-level signal VDD is selected to be output when the control terminal of the third selector 246 inputs a low-level signal, and the clock signal CLK is selected to be output when the control terminal of the third selector 246 inputs a high-level signal;

an output terminal of the seventh not gate 247 is coupled to a control terminal of the data latch module and a second input terminal of the third or gate 245; the output terminal of the seventh not gate 247 is used for selectively outputting the inverted signal or the continuous low level signal of the clock signal CLK.

When the combination logic module shown in fig. 7 is included in the sampling pulse signal generating module shown in fig. 6 and the structure of the data latch module is shown in fig. 4, a timing diagram corresponding to the serial-parallel conversion circuit is shown in fig. 8. Specifically, obtaining the first pulse sampling signal corresponding to the low level signal of the clock signal will be described with reference to fig. 6, 7, and 8.

When the serial-parallel conversion circuit is activated, the reset signal RST is at a low level, the clock signal CLK is at a low level, the level switching signal Shift is at a low level, the input end of the first-stage combinational logic module inputs the activation signal EN, which is also at a low level, that is, the first input end of the second or gate 241 receives a low level signal, the second input end of the second or gate 241 receives a low level signal (no input), the control end of the second selector 242 receives a low level signal, the second selector 242 selects to output a low level signal, after passing through the fifth not gate 243 and the sixth not gate 244, the output end of the sixth not gate 244 outputs a low level signal, the first input end of the third or gate 245 receives a low level signal, the second input end of the third or gate 245 receives a low level signal (no input), the third selector 246 receives a low level signal, the third selector 246 selects to output a high level signal VDD, the output terminal of the sixth not gate 244 outputs a low level signal, and the output terminals of the remaining combinational logic blocks all output low level signals.

When the reset signal RST changes to a high level, the clock signal CLK changes to a low level, the enable signal EN changes to a high level, the level Shift signal Shift changes to a low level, the first input terminal of the second or gate 241 receives a high level signal, the second input terminal of the second or gate 241 receives a low level signal, the control terminal of the second selector 242 receives a high level signal, the second selector 242 selects the output clock signal, and after passing through the fifth not gate 243 and the sixth not gate 244, before the first high level of the clock signal CLK arrives, the output terminal of the sixth not gate 244 outputs a low level signal, the first input terminal of the third or gate 245 receives a low level signal, the second input terminal of the third or gate 245 receives a low level signal, the third selector 246 selects to output a high level signal VDD, the output terminal of the sixth not gate 244 outputs a low level signal, and the output terminals of the remaining combinational logic blocks all output low level signals. When the first high level of the clock signal CLK arrives, since the transition of the enable signal EN is delayed compared to the transition of the clock signal CLK, the output terminal of the sixth not gate 244 outputs a high level signal, the first input terminal of the third or gate 245 receives a high level signal, the second input terminal of the third or gate 245 receives a low level signal, the third selector 246 receives a high level signal, the third selector 246 selects to output the clock signal CLK, the output terminal of the sixth not gate 244 outputs an inverted signal of the clock signal CLK, that is, outputs a low level signal, and the output terminals of the remaining combinational logic blocks all output a low level signal.

When the reset signal RST is kept at a high level, after the first high level of the clock signal CLK comes, the enable signal EN changes to a low level, the level Shift signal Shift changes to a low level, the first input terminal of the second or gate 241 receives a low level signal, the second input terminal of the second or gate 241 receives a high level signal, the control terminal of the second selector 242 receives a high level signal, the second selector 242 selects to output the clock signal CLK, after passing through the fifth not gate 243 and the sixth not gate 244, the output terminal of the sixth not gate 244 outputs the clock signal CLK, that is, a high signal is output, a first input terminal of the third or gate 245 receives a high signal, a second input terminal of the third or gate 245 receives a low signal, the third selector 246 receives a high signal, the third selector 246 selects the output clock signal CLK, an output terminal of the sixth not gate 244 outputs a low signal, and output terminals of the remaining combinational logic blocks all output a low signal.

When the reset signal RST is kept at a high level, the clock signal CLK changes from a high level to a low level, the enable signal EN is kept at a low level, the level Shift signal Shift is at a low level, the first input terminal of the second or gate 241 receives a low level signal, the second input terminal of the second or gate 241 receives a high level signal, the control terminal of the second selector 242 receives a high level signal, the second selector 242 selects to output the clock signal CLK, after passing through the fifth not gate 243 and the sixth not gate 244, the output terminal of the sixth not gate 244 outputs the clock signal CLK, the first input terminal of the third or gate 245 receives a low level signal, the second input terminal of the third or gate 245 receives a high level signal, the third selector 246 selects to output the clock signal CLK, the output terminal of the sixth not gate 244 outputs a high level signal, and the output terminals of the remaining combinational logic blocks all output low level signals, therefore, the sampling pulse signal generation module divides the clock signal to obtain pulse samples corresponding to the low level of the clock signal in one clock cycle.

And the signal output by the second module B of the last-stage combinational logic module returns to the input end of the first module B of the first-stage combinational logic module through the first selector, and the clock signal CLK is continuously divided to obtain the next group of sampling pulse signals. The data buffer module latches the input serial data D0, D1, D2, D3, D4, D5 and the like in sequence under the control of the sampling pulse signal CLK-S, and outputs 4-bit data in parallel, wherein each data can be buffered in the data buffer module for four clock cycles.

It should be noted that, when data to be transmitted is data in a k-bit format, where k is a positive integer, in the serial-to-parallel conversion circuit provided in the embodiment of the present application, each data may buffer k clock cycles in the data buffer module. Therefore, the serial-parallel conversion circuit provided by the embodiment of the application can prolong the time for latching data under the control of the sampling pulse signal, so that the serial-parallel conversion circuit provided by the embodiment of the application has enough time sequence redundancy to ensure the correct output of the data, the difficulty of time sequence design can be reduced, and the stability of high-frequency data transmission is improved.

Next, taking an example of obtaining pulse sampling signals respectively corresponding to a high-level signal and a low-level signal of a clock signal in each clock cycle, a sampling pulse signal generating module provided in the embodiment of the present application is exemplified.

Alternatively, as shown in FIG. 9, the combinational logic blocks 24 of odd-numbered stages comprise a first block A, and the combinational logic blocks 24 of even-numbered stages comprise a second block B;

the input end IN of the first module a is coupled to the output end of the alternative data selection module 23 or the output end OUT of the second module B at the previous stage; the output end OUT of the first module A is coupled with the control end of the data latch module; the first module A is used for selectively outputting the clock signal CLK or continuously outputting a low level signal;

an input end IN of the second module B is coupled with an output end OUT of the first module A at the previous stage, and the output end OUT of the second module B is coupled with a control end of the data latch module; the second module B is used for selectively outputting an inverted signal or a continuous low level signal of the clock signal CLK;

the output terminal OUT of the second block B in the last stage is coupled to the second input terminal of the one-of-two data selecting block 23.

Optionally, as shown in fig. 10, the first module a includes: a second or gate 241, a second selector 242, a fifth not gate 243, and a sixth not gate 244; the second module B includes: a third or gate 245, a third selector 246, and a seventh not gate 247; the connection relationship of the elements in the first module a in fig. 10 is the same as the connection relationship of the elements in the first module a in fig. 7, the connection relationship of the elements in the second module B in fig. 10 is the same as the connection relationship of the elements in the second module B in fig. 7, and the connection relationship of the elements in the first module a and the second module B and the principle of the first module a and the second module B are not repeated herein.

When it is required to obtain pulse sampling signals corresponding to a high level signal and a low level signal of a clock signal respectively in each clock cycle as shown in fig. 10, an output terminal of the sixth not gate 244 in the first block a needs to be coupled to a control terminal of the data latch module in addition to an output terminal of the third or gate 245, and an output terminal of the sixth not gate 244 outputs a sampling pulse signal CLK-S to the data latch module connected thereto. The sampling pulse signal generation modules shown in FIG. 9 and FIG. 10 are coupled to the 8 data latch modules, and divide the clock signal into 8 sampling pulse signals, which are CLK-S0, CLK-S1, CLK-S2, CLK-S3, CLK-S4, CLK-S5, CLK-S6 and CLK-S7. In FIG. 9, the control signal of the second input terminal of the first NOR gate 221 in the high-low level shift module 22 is CLK-S3, but the control signal of the second input terminal of the first NOR gate 221 may be any one of CLK-S0, CLK-S1, CLK-S2, CLK-S3, CLK-S4, CLK-S5, and CLK-S6.

The sampling pulse signal generation module shown in fig. 9 and 10 divides the clock signal to obtain the timing chart of the pulse sampling signal corresponding to the high level signal and the low level signal of the clock signal in each clock cycle as shown in fig. 11.

It should be noted that the total number of the first module and the second module in the sampling pulse signal generating module shown in fig. 6 and 7 is the same as the total number of the first module and the second module in the sampling pulse signal generating module shown in fig. 9 and 10, but the sampling pulse signal generating module shown in fig. 6 and 7 generates pulse samples of one clock signal in one clock cycle, and the sampling pulse signal generating module shown in fig. 9 and 10 generates pulse samples of two clock signals in one clock cycle, so that the sampling pulse signal generating module shown in fig. 9 and 10 can increase the number of bits of data parallel transmission without changing the number of the first module and the second module.

Based on the same inventive concept, an embodiment of the present application further provides a driving method of a serial-to-parallel conversion circuit, as shown in fig. 12, the method includes:

s101, inputting a clock signal CLK and a reset signal RST to the sampling pulse signal generation module, controlling the sampling pulse signal generation module to divide the clock signal CLK according to the reset signal RST, generating a plurality of sampling pulse signals CLK-S and outputting the sampling pulse signals CLK-S to each coupled data latch module;

s102, inputting the reset signal RST, the sampling pulse signal CLK-S and the serial data signal SI to the data latch module, and controlling the data latch module to latch and output the data signal in the input serial data signal SI according to the sampling pulse signal CLK-S and the reset signal RST.

Optionally, when the sampling pulse signal generating module includes a starting module, a high-low level converting module, an alternative data selecting module, and a plurality of cascaded combinational logic modules, inputting a clock signal CLK and a reset signal RST to the sampling pulse signal generating module, specifically including:

inputting a clock signal CLK to the input end of the starting module and the clock signal end of the combinational logic module, and inputting a reset signal RST to the reset signal ends of the starting module and the high-low level conversion module;

the high-low level conversion module further inputs a sampling pulse signal CLK-S output by a combinational logic module except the last-stage combinational logic module, a start signal is input at a first input end of the alternative data selection module, a sampling pulse signal CLK-S output by the last-stage combinational logic module is input at a second input end of the alternative data selection module, the sampling pulse signal generation module is controlled to divide the clock signal CLK according to the reset signal RST, a plurality of sampling pulse signals CLK-S are generated and output to each coupled data latch module, and the method specifically includes:

the control starting module generates a starting signal EN according to a clock signal CLK and a reset signal RST and outputs the starting signal EN;

controlling a high-low level module to generate and output a level switching signal shift according to the sampling pulse signal CLK-S and the reset signal RST;

controlling an alternative data selection module to selectively output the start signal EN or the sampling pulse signal CLK-S as a segmentation control signal according to the level switching signal shift;

controlling a first-stage combinational logic module to select and output a pulse sampling or continuous low-level signal of a clock signal CLK as the sampling pulse signal CLK-S according to the clock signal CLK and a division control signal;

and controlling the other combinational logic modules except the first-stage combinational logic module to select pulse sampling or continuous low-level signals of the output clock signal CLK as the sampling pulse signals CLK-S according to the clock signal CLK and the sampling pulse signals CLK-S output by the last-stage combinational logic module.

It should be noted that the components of each element in the start module, the high-low level conversion module, the alternative data selection module, and the combinational logic module, and the working principle of each module under the control of the reset signal and the clock signal have been described in detail in the specific embodiment of the serial-parallel conversion circuit, and are not described herein again.

Optionally, when the data latch module includes a first transmission gate, a second transmission gate, a first nand gate, and a first not gate, the method specifically includes inputting the reset signal RST and the serial data signal SI to the data latch module:

inputting the serial data signal SI to an input terminal of the first transmission gate, inputting the sampling pulse signal CLK-S to a first control terminal of the first transmission gate and a second control terminal of the second transmission gate, inputting an inversion signal CLK-SN opposite to the sampling pulse signal to a second control terminal of the first transmission gate and a first control terminal of the second transmission gate, and inputting the reset signal RST to a second input terminal of the first nand gate;

according to the sampling pulse signal CLK-S and the reset signal RST, controlling the data latch module to latch and output the data signal in the input serial data signal SI, specifically including:

inputting a high-level reset signal RST to a second input end of the first NAND gate, inputting a high-level sampling pulse signal CLK-S to a first control end of the first transmission gate through a second control end of the second transmission gate, and controlling the first transmission gate to be opened and the second transmission gate to be closed so as to control the serial data signal SI to be written from the input end of the first transmission gate;

the second input end of the first NAND gate is input with a high-level reset signal RST, the first control end of the first transmission gate is input with a low-level sampling pulse signal CLK-S through the second control end of the second transmission gate, and the first transmission gate is controlled to be closed and the second transmission gate is controlled to be opened so as to control the input data to be latched by the latch module.

It should be noted that the connection relationship and the operation principle of each element in the data latch module have been described in detail in the specific embodiment of the serial-to-parallel conversion circuit, and are not described herein again.

The embodiment of the application provides a display panel, which comprises a serial-parallel conversion circuit provided by the embodiment of the application.

To sum up, in the serial-to-parallel conversion circuit and the driving method thereof and the display panel provided in the embodiments of the present application, the sampling pulse signal generation module is used to divide the clock signal, so as to generate a plurality of different sampling pulse signals, which are respectively output to the data latch modules. And each data latch module inputs a serial data signal, and the data latch modules latch the input serial data signals under the control of the sampling pulse signals, namely different data latch modules latch the input serial data signals under the control of different sampling pulse signals. Therefore, different data latch modules are not controlled by the same clock signal any more, and current data cannot be changed when latched in each data latch module before new data is written in under the control of different sampling pulse signals.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A serial-to-parallel conversion circuit, the serial-to-parallel conversion circuit comprising: the device comprises a sampling pulse signal generating module and a plurality of data latching modules;

2. The serial-to-parallel conversion circuit according to claim 1, wherein the data latch module comprises: the first NAND gate is connected with the first transmission gate;

3. The serial-to-parallel conversion circuit according to claim 1, wherein the sampling pulse signal generation module comprises: the device comprises a starting module, a high-low level conversion module, an alternative data selection module and a plurality of cascaded combinational logic modules;

the input end of the starting module is used for receiving the clock signal, the reset signal end of the starting module is used for receiving the reset signal, and the output end of the starting module is coupled with the first input end of the alternative data selection module; the starting module is used for: generating a starting signal according to the clock signal and the reset signal and outputting the starting signal;

4. The serial-to-parallel conversion circuit of claim 3, wherein the start-up module comprises: the first NAND gate, the second NAND gate, the first AND gate and the second NOT gate;

5. The serial-to-parallel conversion circuit of claim 3, wherein the high-low level conversion module comprises: a first nor gate, a third nor gate, and a fourth nor gate;

the alternative data selection module comprises: a first selector;

6. The serial-to-parallel conversion circuit according to any one of claims 3 to 5, wherein the combinational logic module comprises: a first module and a second module;

7. The serial-to-parallel conversion circuit of any one of claims 3 to 5, wherein the combinational logic blocks of odd-numbered stages comprise a first block, and the combinational logic blocks of even-numbered stages comprise a second block;

8. The serial-to-parallel conversion circuit according to claim 6 or 7, wherein the first module comprises: a second or gate, a second selector, a fifth not gate, and a sixth not gate;

the second module includes: a third or gate, a third selector, and a seventh not gate; a first input terminal of the second or gate is configured to receive the dividing control signal or the sampling pulse signal, and an output terminal of the second or gate is coupled to a control terminal of the second selector;

an output of the fifth not gate is coupled to an input of the sixth not gate;

9. A driving method of a serial-to-parallel conversion circuit according to any one of claims 1 to 8, the method comprising:

10. A display panel comprising the serial-to-parallel conversion circuit according to any one of claims 1 to 8.