CN113539156B - Serial-parallel conversion circuit, driving method thereof, mode latch circuit and display device - Google Patents
Serial-parallel conversion circuit, driving method thereof, mode latch circuit and display device Download PDFInfo
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- CN113539156B CN113539156B CN202010307417.8A CN202010307417A CN113539156B CN 113539156 B CN113539156 B CN 113539156B CN 202010307417 A CN202010307417 A CN 202010307417A CN 113539156 B CN113539156 B CN 113539156B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses a serial-parallel conversion circuit and a driving method thereof, a mode latch circuit and a display device, wherein the serial-parallel conversion circuit comprises a sampling pulse signal generating module and a plurality of signal latch modules, and the sampling pulse signal generating module is provided with a plurality of output ends which are connected with the control ends of the signal latch modules in a one-to-one correspondence manner; the sampling pulse signal generation module is used for generating a plurality of sampling pulse signals under the control of the clock signal and the enabling signal and outputting the sampling pulse signals to the control end of the corresponding signal latch module respectively; the signal latching module is used for latching and outputting serial input signals received by the input end of the signal latching module under the control of the reset signals and the corresponding sampling pulse signals. The serial-parallel conversion circuit has enough time sequence redundancy and is suitable for the stability of high-frequency signal transmission.
Description
Technical Field
The invention relates to the technical field of display, in particular to a serial-parallel conversion circuit, a driving method thereof and a display device.
Background
In some driving circuits of display devices, in the prior art, mode signals are latched through a shift register, an additional counter is required to control the latching of the mode signals, and latch dislocation phenomenon easily occurs under high-frequency operation, so that the overall function of the circuit is invalid, and the stability of the circuit is insufficient.
Disclosure of Invention
In view of the above-described drawbacks or shortcomings in the related art, it is desirable to provide a serial-parallel conversion circuit, a driving method thereof, a mode latch circuit, and a display device.
In a first aspect, the present invention provides a serial-parallel conversion circuit comprising: the sampling pulse signal generation module is provided with a plurality of output ends which are connected with the control ends of the signal latch modules in a one-to-one correspondence manner;
the sampling pulse signal generation module is used for generating a plurality of sampling pulse signals under the control of a clock signal and an enabling signal and outputting the sampling pulse signals to the control end of the corresponding signal latch module respectively;
the signal latching module is used for latching and outputting a serial input signal received by the input end of the signal latching module under the control of a reset signal and the corresponding sampling pulse signal.
Preferably, the sampling pulse signal generating module comprises a starting module and a plurality of cascaded sampling pulse signal generators;
the input end of the starting module is used for receiving the clock signal, the enabling input end of the starting module is used for receiving the enabling signal, and the starting module is used for generating a starting signal according to the clock signal and the enabling signal and outputting the starting signal to the control end of the corresponding signal latching module as a sampling pulse signal;
The clock signal end of the sampling pulse signal generator is used for receiving the clock signal, the input end of the sampling pulse signal generator at the first stage receives the starting signal, the input ends of the sampling pulse signal generators except the sampling pulse signal generator at the first stage are connected with the output end of the sampling pulse signal generator at the last stage, and the output end of the sampling pulse signal generator is connected with the control end of the corresponding signal latching module.
Preferably, the starting module comprises a first or gate, a first nand gate, a first and gate and a first not gate;
the first input end of the first OR gate is used for receiving the clock signal, the first input end of the first OR gate is connected with the output end of the first NOT gate, and the output end of the first OR gate is connected with the first input end of the first NAND gate;
the second input end of the first NAND gate and the first input end of the first AND gate are used for receiving the enabling signal, and the output end of the first NAND gate is connected with the input end of the first NAND gate and the second input end of the first AND gate;
the output end of the first AND gate is used for outputting the starting signal.
Preferably, the sampling pulse signal generator includes: a first module and a second module;
the clock signal terminals of the first module and the second module are used for receiving the clock signals;
the input end of the first module is connected with the output end of the starting module or the output end of the second module in the upper stage sampling pulse signal generator, and the output end of the first module is connected with the input end of the second module;
the output end of the second module is connected with the control end of the corresponding signal latch module;
the first module is used for selectively outputting the clock signal or the continuous low level signal;
the second module is used for selectively outputting an inverted signal or a continuously low level signal of the clock signal.
Preferably, the sampling pulse signal generator of the odd-numbered stage includes a first module, and the sampling pulse signal generator of the even-numbered stage includes a second module;
the clock signal terminals of the first module and the second module are used for receiving the clock signals;
the input end of the first module is connected with the output end of the starting module or the output end of the second module at the upper stage, and the output end of the first module is connected with the control end of the corresponding signal latch module;
The input end of the second module is connected with the output end of the first module at the previous stage, and the output end of the second module is connected with the control end of the corresponding signal latch module;
the first module is used for selectively outputting the clock signal or the continuous low level signal;
the second module is used for selectively outputting an inverted signal or a continuously low level signal of the clock signal.
Preferably, the first module includes: a second or gate, a first selector, a second not gate, and a third not gate;
the first input end of the second OR gate is connected with the output end of the starting module or the output end of the second module at the upper stage, and the output end of the second OR gate is connected with the control end of the first selector;
the first input end of the first selector is grounded, the second input end of the first selector is used for receiving the clock signal, the output end of the first selector is connected with the second input end of the second OR gate and the input end of the second NOT gate, and the output end of the first selector is used for: selecting and outputting a continuous low-level signal when a low-level signal is input to the control end of the first selector, and selecting and outputting the clock signal when a high-level signal is input to the control end of the first selector;
The output end of the second NOT gate is connected with the input end of the third NOT gate;
the output end of the third NOT gate is used for selectively outputting the clock signal or the continuous low level signal.
Preferably, the second module includes: a third or gate, a second selector, and a fourth not gate;
the first input end of the third OR gate is connected with the output end of the first module of the previous stage, and the output end of the third OR gate is connected with the control end of the second selector;
the first input end of the second selector is used for receiving a high-level signal, the second input end of the second selector is used for receiving the clock signal, the output end of the second selector is connected with the input end of the fourth NOT gate, and the output end of the second selector is used for: selecting and outputting the high-level signal when the low-level signal is input to the control end of the second selector, and selecting and outputting the clock signal when the high-level signal is input to the control end of the second selector;
the output end of the fourth NOT gate is connected with the second input end of the third OR gate and the control end of the corresponding signal latch module, and the output end of the fourth NOT gate is used for selectively outputting the reverse signal or the continuous low level signal of the clock signal.
Preferably, the signal latch module includes: a first transmission gate, a second NAND gate, and a fifth NAND gate;
the input end of the first transmission gate is used for receiving the serial input signal, the first control end of the first transmission gate and the second control end of the second transmission gate are used for receiving the sampling pulse signal, the second control end of the first transmission gate and the first control end of the second transmission gate are used for receiving a reverse signal opposite to the sampling pulse signal, and the output end of the first transmission gate and the first input end of the second NAND gate;
the second input end of the second NAND gate is used for receiving the reset signal, and the output end of the second NAND gate is connected with the input end of the fifth NAND gate;
the output end of the fifth NOT gate is connected with the input end of the second transmission gate, and the output end of the second transmission gate is connected with the first input end of the second NOT gate;
the output end of the fifth NOT gate is used for outputting the serial input signal.
In a second aspect, the present invention provides a driving method of a serial-parallel conversion circuit, the method comprising:
inputting a clock signal and an enabling signal to a sampling pulse signal generating module, generating a plurality of sampling pulse signals according to the clock signal and the enabling signal, and outputting the sampling pulse signals to a control end of a corresponding signal latching module;
And inputting the corresponding sampling pulse signal, reset signal and serial input signal to the signal latch module, and controlling the signal latch module to latch and output the serial input signal according to the sampling pulse signal and the reset signal.
In a third aspect, the present invention provides a mode latch circuit comprising a serial-to-parallel conversion circuit as described above and a mode decoder, the output of each signal latch module of the serial-to-parallel conversion circuit being connected to an input of the mode decoder.
In a fourth aspect, the present invention provides a display device including: a serial-parallel conversion circuit as described above, or a mode latch circuit as described above.
The beneficial effects of the scheme are as follows: the serial-parallel conversion circuit utilizes the sampling pulse signal generation module to carry out logic operation to generate a plurality of sampling pulse signals, the sampling pulse signals are respectively output to each signal latching module, the signal latching module latches serial input signals received by the input end of the signal latching module under the control of sampling pulses, the serial input signals are not realized by a shift register, the dislocation phenomenon is avoided, the sufficient time sequence redundancy is realized, and the serial-parallel conversion circuit is suitable for the stability of high-frequency signal transmission;
Correspondingly, the mode latch circuit can latch mode signals in sequence through each signal latch module and read in the mode decoder, can finish the reading of the mode signals under high frequency, is easier to switch between modes, can leave more time for the configuration of the working state of the subsequent circuit after the mode is selected, and is suitable for the display drive circuit with the multi-mode working state.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a prior art mode selection module;
FIG. 2 is a schematic diagram of a generation module of the latch signal CK_MODE in FIG. 1;
FIG. 3 is a timing diagram of the mode selection module shown in FIG. 1;
fig. 4 is a schematic structural diagram of a serial-parallel conversion circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a sampling pulse signal generating module according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a start module according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a sampling pulse signal generator according to an embodiment of the present invention;
FIG. 8 is a timing diagram of the sample pulse signal generator illustrated in FIG. 7;
fig. 9 is a schematic structural diagram of a signal latch module according to an embodiment of the present invention;
FIG. 10 is a timing diagram of a serial-parallel conversion circuit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of another structure of a sampling signal generator according to an embodiment of the present invention;
FIG. 12 is another timing diagram of a serial-parallel conversion circuit according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a mode latch circuit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
Fig. 1 is a schematic diagram of a prior art mode selection module, including a 12bit shift register of 12D flip-flops (DFFs) and 6 latches (latches) for latching a serial input signal. The mode signal relates to only the first 6 DFFs of the 12bit shift register, and the remaining 6 DFFs are used for the subsequent latching of the address signal and the data signal, and the mode signal will be described herein, so only the first 6 DFFs will be described in detail.
Fig. 2 is a schematic diagram of a generation module of the MODE latch signal ck_mode in fig. 1, which is composed of a 4-bit MODE 16 counter, two inverters, a two-input and gate, and a three-input and gate, and ck_mode is active when the counter reaches 6 (i.e. q3q2q1q0=0110) for controlling the MODE signal latch.
Fig. 3 is a timing chart of the MODE selection module shown in fig. 1, in which serial input signals SI are sequentially input into D0-D5, ck_mode is generated when the counter counts to 6, and D0-D5 stored in shift registers sr_1 to sr_6 are simultaneously latched and sent to a MODE signal decoder for subsequent processing, but because shift registers themselves shift when receiving clock signals, in actual use, when D0-D5 stored in sr_1 to sr_6 need to be latched in high frequency operation, ck_mode signals generated by the counter cannot reach Latch control signals within 1 period, and when shift registers have shifted for a new time, MODE signal latching is shifted. Meanwhile, because the mode signal, the address and the data signals are latched and processed by adopting the same shift register, the latching of the mode signal can be unstable, and unexpected change of the mode can be caused when burrs are generated in the circuit, so that the overall function of the circuit is wrong.
In order to solve the above problems, an embodiment of the present invention provides a serial-parallel conversion circuit. As shown in fig. 4, the serial-parallel conversion circuit provided by the embodiment of the invention includes: the sampling pulse signal generation module 1 and the plurality of signal latch modules 2, wherein the sampling pulse signal generation module 1 is provided with a plurality of output ends which are connected with the control ends of the signal latch modules 2 in a one-to-one correspondence manner;
the sampling pulse signal generating module 1 is used for generating a plurality of sampling pulse signals under the control of a clock signal and an enabling signal and outputting the sampling pulse signals to the control end of the corresponding signal latching module 2 respectively;
the signal latch module 2 is configured to latch and output a serial input signal SI received at an input terminal thereof under control of a reset signal and a corresponding sampling pulse signal.
As shown in fig. 4, this embodiment provides a serial-parallel conversion circuit including 6 signal latch modules 2, the 6 signal latch modules being respectively: latch1, latch2, latch3, latch4, latch5, and latch6; the sampling pulse signal generating module 1 receives the clock signal SCLK and the enable signal SCS, generates a plurality of sampling pulse signals m_clk through logic operation, and in this embodiment, corresponds to 6 signal latch modules, and the sampling pulse generating module generates 6 sampling pulse signals m_clk0, m_clk1, m_clk2, m_clk3, m_clk4 and m_clk5. The control terminal C of Latch1 receives M_Clk0, the control terminal C of Latch2 receives M_Clk1, the control terminal C of Latch3 receives M_Clk2, the control terminal C of Latch4 receives M_Clk3, the control terminal C of Latch5 receives M_Clk4, and the control terminal C of Latch6 receives M_Clk5. The input ends of Latch1, latch2, latch3, latch4, latch5 and Latch6 receive the same serial input signal SI, the reset signal ends of Latch1, latch2, latch3, latch4, latch5 and Latch6 receive the reset signal, and each signal Latch module 2 latches the serial input signal SI received by the input ends thereof under the control of the reset signal and different sampling pulse signals M_Clk and outputs the latched serial input signal SI. The signals output by the output ends of Latch1, latch2, latch3, latch4, latch5 and Latch6 are respectively Q1, Q2, Q3, Q4, Q5 and Q6.
Further, as shown in fig. 5, the sampling pulse signal generating module 1 includes a starting module 11 and a plurality of cascaded sampling pulse signal generators 12;
the input end of the starting module 11 is used for receiving a clock signal SCLK, the enabling input end of the starting module 11 is used for receiving an enabling signal SCS, the starting module 11 is used for generating a starting signal START according to the clock signal SCLK and the enabling signal SCS, and the starting signal START is output to the control end of the corresponding signal Latch module 2 (Latch 1 in the embodiment) as a sampling pulse signal M_Clk0;
the clock signal SCLK end of the sampling pulse signal generator 12 is used for receiving the clock signal SCLK, the input end IN of the first stage sampling pulse signal generator 12 receives the START signal START, the input ends IN of the rest sampling pulse signal generators 12 except the first stage sampling pulse signal generator 12 are connected with the output end of the previous stage sampling pulse signal generator 12, and the output end of the sampling pulse signal generator 12 is connected with the control end of the corresponding signal latch module 2;
the number of sampling pulse signal generators 12 is 1 less than the number of signal latch modules 2.
As shown in fig. 5, the preferred sampling pulse signal generating module 1 includes a starting module 11 and 5 sampling pulse signal generators 12, where the 5 sampling pulse signal generators 12 are respectively a sampling pulse signal generator 1, a sampling pulse signal generator 2, a sampling pulse signal generator 3, a sampling pulse signal generator 4 and a sampling pulse signal generator 5, the output end of the starting signal 11 is connected with the control end of Latch1, the output end of the sampling pulse signal generator 1 is connected with the control end of Latch2, the output end of the sampling pulse signal generator 2 is connected with the control end of Latch3, the output end of the sampling pulse signal generator 3 is connected with the control end of Latch4, the output end of the sampling pulse signal generator 4 is connected with the control end of Latch5, and the output end of the sampling pulse signal generator 5 is connected with the control end of Latch 6.
Further, the starting module 11 includes a first or gate 111, a first nand gate 112, a first not gate 113, and a first and gate 114;
a first input terminal of the first or gate 111 is configured to receive the clock signal SCLK, the first input terminal of the first or gate 111 is connected to the output terminal of the first not gate 113, and the output terminal of the first or gate 111 is connected to the first input terminal of the first nand gate 112;
the second input terminal of the first nand gate 112 and the first input terminal of the first and gate 114 are used for receiving the enabling signal SCS, and the output terminal of the first nand gate 112 is connected with the input terminal of the first nor gate 113 and the second input terminal of the first and gate 114;
the output of the first AND gate 114 is used for outputting a START signal START, and is also used as a sampling pulse signal M_Clk0.
As shown in the timing chart of the START-up module in fig. 6, when the clock signal SCLK is a low level signal, the enable signal SCS is a low level signal, that is, the first input terminal of the first or gate 111 receives the low level signal, the second input terminal of the first nand gate 112 and the first input terminal of the first and gate 114 receive the low level signal, the second input terminal of the first or gate 111 receives the low level signal (no input), the output terminal of the first or gate 111 outputs the low level signal, the output terminal of the first nand gate 112 outputs the high level signal, the output terminal of the first not gate 113 outputs the low level signal, and the START signal START (multiplexed into the sampling pulse signal m_clk0) output by the output terminal of the first and gate 114 is the low level signal.
When the enable signal SCS is switched from a low level signal to a high level signal and the clock signal SCLK is a low level signal, that is, the first input terminal of the first or gate 111 receives the low level signal, the second input terminal of the first nand gate 112 and the first input terminal of the first and gate 114 receive the high level signal, the second input terminal of the first or gate 111 receives the low level signal, the output terminal of the first or gate 111 outputs the low level signal, the output terminal of the first nand gate 112 outputs the high level signal, the output terminal of the first not gate 113 outputs the low level signal, and the START signal START output by the output terminal of the first and gate 114 is changed from the low level signal to the high level signal.
Then, when the first high level signal of the clock signal SCLK comes, that is, the first input terminal of the first or gate 111 receives the high level signal, the second input terminal of the first nand gate 112 and the first input terminal of the first and gate 114 receive the high level signal, the second input terminal of the first or gate 111 receives the high level signal, the output terminal of the first or gate 111 outputs the high level signal, the output terminal of the first nand gate 112 outputs the low level signal, the output terminal of the first nor gate 113 outputs the high level signal, and the START signal START output by the output terminal of the first and gate 114 is changed from the high level signal to the low level signal, so that the subsequent sampling pulse signal generator STARTs to operate.
When the enable signal SCS maintains the high level signal and the output terminal of the first not gate 113 outputs the high level signal, the output terminal of the first or gate 111 outputs the high level signal, the output terminal of the first nand gate 112 outputs the low level signal, the output terminal of the first not gate 113 outputs the high level signal, and the START signal START output by the output terminal of the first and gate 114 is the low level signal, regardless of whether the clock signal input by the first or gate 111 is the high level signal or the low level signal.
As an alternative embodiment, the sampling pulse signal generator 12 includes: a first module a and a second module B;
the clock signal SCLK ends of the first module A and the second module B are used for receiving the clock signal SCLK;
the input end of the first module A is connected with the output end of the starting module 11 or the output end of the second module B in the upper-stage sampling pulse signal generator 12, and the output end of the first module A is connected with the input end of the second module B;
the output end of the second module B is connected with the control end of the corresponding signal latch module 2;
the first module A is used for selecting an output clock signal SCLK or a continuous low level signal;
the second module B is configured to select an inverted signal or a continuously low signal of the output clock signal SCLK.
I.e. the signal output by the output end of the starting module and the signal output by the output end of the second module B are used as sampling pulse signals m_clk.
Optionally, the first module a includes: a second or gate 121, a first selector 122, a second not gate 123, and a third not gate 124;
the first input end of the second or gate 121 is connected with the output end of the starting module 11 or the output end of the upper-stage second module B, and the output end of the second or gate 121 is connected with the control end of the first selector 122;
a first input terminal of the first selector 122 is grounded GND, a second input terminal of the first selector 122 is configured to receive the clock signal SCLK, an output terminal of the first selector 122 is connected to a second input terminal of the second or gate 121 and an input terminal of the second not gate 123, and an output terminal of the first selector 122 is configured to: selecting and outputting a continuous low level signal when a low level signal is input to the control terminal of the first selector 122, and selecting and outputting a clock signal SCLK when a high level signal is input to the control terminal of the first selector 122;
the output of the second NOT gate 123 is connected to the input of the third NOT gate 124;
the output of the third not gate 124 is used to select the output clock signal SCLK or the continuously low signal.
Further, the second module B includes: a third or gate 125, a second selector 126, and a fourth not gate 127;
The first input end of the third or gate 125 is connected with the output end of the first module a of the previous stage, and the output end of the third or gate 125 is connected with the control end of the second selector 126;
a first input terminal of the second selector 126 is configured to receive a high level signal, a second input terminal of the second selector 126 is configured to receive a clock signal SCLK, an output terminal of the second selector 126 is connected to an input terminal of the fourth not gate 127, and an output terminal of the second selector 126 is configured to: selecting and outputting a high level signal when a low level signal is input to the control terminal of the second selector 126, and selecting and outputting a clock signal SCLK when a high level signal is input to the control terminal of the second selector 126;
the output end of the fourth not gate 127 is connected to the second input end of the third or gate 125 and the control end of the corresponding signal latch module 2, and the output end of the fourth not gate 127 is used for selecting the inverted signal or the continuous low level signal of the output clock signal SCLK.
As shown in fig. 7, the structure of each sampling pulse signal generator includes a first module a and a second module B, and refers to a timing chart as shown in fig. 8. When the input end IN of the first sampling pulse signal device receives the START signal START, the output of the second or gate 121 is changed from low level to high level, so that the output of the first selector 122 is switched from the ground GND to the clock signal SCLK, and when the SCLK signal is changed to high level, the output of the first selector 122 obtains the pulse signal M through the second not gate 123 and the third not gate 124; similarly, when the sampling pulse signal M is transferred to the third or gate 125, the third or gate 125 is enabled to output a high level, the output of the second selector 126 is controlled to switch from the high level VDD to the clock signal SCLK, and when the SCLK signal is a low level signal, the output of the second selector 126 obtains the pulse signal OUT through the fourth not gate 127.
Further, as shown in fig. 9, the signal latch module 2 includes: a first transmission gate 21, a second transmission gate 22, a second nand gate 23, and a fifth nor gate 24;
the input end of the first transmission gate 21 is used for receiving a serial input signal SI, the first control end of the first transmission gate 21 and the second control end of the second transmission gate 22 are used for receiving sampling pulse signals, the second control end of the first transmission gate 21 and the first control end of the second transmission gate 22 are used for receiving reverse signals opposite to the sampling pulse signals, and the output end of the first transmission gate 21 and the first input end of the second nand gate 23;
the second input end of the second nand gate 23 is used for receiving a reset signal, and the output end of the second nand gate 23 is connected with the input end of the fifth nand gate 24;
the output end of the fifth NOT gate 24 is connected with the input end of the second transmission gate 22, and the output end of the second transmission gate 22 is connected with the first input end of the second NOT gate 23;
the output of the fifth not gate 24 is for outputting the serial input signal SI.
When the sampling pulse signal m_clk is a high level signal, the first transmission gate 21 is turned on, the second transmission gate 22 is turned off, and the serial input signal SI is written from the input terminal of the first transmission gate 21. When the sampling pulse signal m_clk is a low level signal, the first transmission gate 21 is turned off, the second transmission gate 22 is turned on, and the input signal is latched by the signal latch module until the sampling pulse signal m_clk is a high level signal again, the first transmission gate 21 is turned on, and the second transmission gate 32 is turned off, and a new signal is written.
The structure of the signal latch module is shown in fig. 9, and the timing diagram corresponding to the serial-parallel conversion circuit is shown in fig. 10. When the serial-parallel conversion circuit is started, the enable signal SCS is low, the clock signal SCLK is low, the input end of the sampling pulse signal generator 1 inputs the START signal START, the START signal START is also low, that is, the first input end of the second or gate 121 receives the low signal, the second input end of the second or gate 121 receives the low signal (no input), the control end of the first selector 122 receives the low signal, the first selector 122 selectively outputs the low signal, the output end of the third not gate 124 outputs the low signal after passing through the second not gate 123 and the third not gate 124, the first input end of the third or gate 125 receives the low signal, the second input end of the third or gate 125 receives the low signal (no input), the second selector 126 selectively outputs the high signal VDD, the output end of the fourth not gate 127 outputs the low signal, and the output ends of the remaining sampling pulse signal generators all output the low signal.
When the enable signal SCS goes high, the clock signal SCLK goes low, the START signal START (pulse sampling signal m_clk 0) goes high, the first input terminal of the second or gate 121 of the sampling pulse signal generator 1 receives the high signal, the second input terminal of the second or gate 121 receives the low signal, the control terminal of the first selector 122 receives the high signal, the first selector 122 selects to output the clock signal, after passing through the second not gate 123 and the third not gate 124, the output terminal of the third not gate 124 outputs the low signal before the first high level of the clock signal SCLK comes, the first input terminal of the third or gate 125 receives the low signal, the second selector 126 selects to output the high signal VDD, the output terminal of the fourth not gate 127 outputs the low signal, and the output terminals of the remaining sampling pulse signal generators all output the low signal.
When the first high level of the clock signal SCLK arrives, since the transition of the START signal START (pulse sampling signal m_clk0) is delayed compared to the transition of the clock signal SCLK, the output terminal of the third not gate 124 of the sampling pulse signal generator 1 outputs a high level signal, the first input terminal of the third or gate 125 receives the high level signal, the second input terminal of the third or gate 125 receives the low level signal, the second selector 126 receives the high level signal, the second selector 126 selects the output clock signal SCLK, the output terminal of the fourth not gate 127 outputs the inverse signal of the clock signal SCLK, i.e. outputs the low level signal, and the output terminals of the remaining sampling pulse signal generators all output the low level signal.
When the enable signal SCS remains at a high level, the START signal START (pulse sampling signal m_clk0) changes to a low level after the first high level of the clock signal SCLK arrives, the first input terminal of the second or gate 121 of the sampling pulse signal generator 1 receives the low level signal, the second input terminal of the second or gate 121 receives the high level signal, the control terminal of the first selector 122 receives the high level signal, the first selector 122 selects the output clock signal SCLK, the output terminal of the third or gate 124 outputs the clock signal SCLK after passing through the second or gate 123 and the third or gate 124, i.e., outputs the high level signal, the first input terminal of the third or gate 125 receives the high level signal, the second input terminal of the third or gate 125 receives the low level signal, the second selector 126 selects the output clock signal SCLK, the output terminal of the fourth or gate 127 outputs the low level signal, and the output terminals of the remaining sampling pulse signal generators all output the low level signal.
When the enable signal SCS is kept at a high level, the clock signal SCLK is changed from a high level to a low level, the START signal START (pulse sampling signal m_clk0) is kept at a low level, the first input terminal of the second or gate 121 of the sampling pulse signal generator 1 receives the low level signal, the second input terminal of the second or gate 121 receives the high level signal, the control terminal of the first selector 122 receives the high level signal, the first selector 122 selects the output clock signal SCLK, after passing through the second not gate 123 and the third not gate 124, the output terminal of the third not gate 124 outputs the clock signal SCLK, the first input terminal of the third or gate 125 receives the low level signal, the second input terminal of the third or gate 125 receives the high level signal, the second selector 126 selects the output clock signal SCLK, the output terminal of the fourth not gate 127 outputs the high level signal, and the output terminals of the remaining sampling pulse signal generators all output the low level signal, so that the sampling pulse signal generating module obtains a pulse corresponding to the low level of the clock signal in one clock cycle.
As an alternative embodiment, the sampling pulse signal generator 12 of the odd-numbered stage includes a first module a, and the sampling pulse signal generator 12 of the even-numbered stage includes a second module B;
The clock signal SCLK ends of the first module A and the second module B are used for receiving the clock signal SCLK;
the input end of the first module A is connected with the output end of the starting module 11 or the output end of the upper-stage second module B, and the output end of the first module A is connected with the control end of the corresponding signal latching module 2;
the input end of the second module B is connected with the output end of the first module A of the previous stage, and the output end of the second module B is connected with the control end of the corresponding signal latch module 2;
the first module A is used for selecting an output clock signal SCLK or a continuous low level signal;
the second module B is configured to select an inverted signal or a continuously low signal of the output clock signal SCLK.
For example, the sampling pulse signal generator 1, the sampling pulse signal generator 3, and the sampling pulse signal generator 3 are the first module a, and the sampling pulse signal generator 2 and the sampling pulse signal generator 4 are the second module B.
Alternatively, as shown in fig. 11, the first module a includes: a second or gate 121, a first selector 122, a second not gate 123, and a third not gate 124; the second module B includes: a third or gate 125, a second selector 126, and a fourth not gate 127; the connection relationship between the elements in the first module a in fig. 11 is the same as the connection relationship between the elements in fig. 7, and the connection relationship between the elements in the second module B in fig. 11 is the same as the connection relationship between the elements in the second module B in fig. 7, and the connection relationship between the elements in the first module a and the second module B and the principle of the first module a and the second module B are not described here again.
As shown in fig. 11, when a pulse sampling signal corresponding to a high level signal and a low level signal of a clock signal is required to be obtained in each clock cycle, the output end of the third not gate 124 in the first module a needs to be connected to the control end of the signal latch module in addition to the output end of the third or gate 125 in the second module B, and the output end of the third not gate 124 in the first module a outputs the sampling pulse signal m_clk to the signal latch module connected thereto. Referring to fig. 5 and 11, the sampling pulse signal generating module is connected to 6 signal latching modules, and generates 6 sampling pulse signals, which are m_clk0, m_clk1, m_clk2, m_clk3, m_clk4, and m_clk5, from the clock signal.
The sampling pulse signal generating module shown in fig. 7 generates pulse samples of one clock signal in one clock period, the sampling pulse signal generating module shown in fig. 11 generates pulse samples of two clock signals in one clock period, and the timing diagram of the sampling pulse signal generating module shown in fig. 11 is shown in fig. 12.
In a second aspect, an embodiment of the present invention further provides a driving method of a serial-parallel conversion circuit, the method including:
The sampling pulse signal generation module 1 is input with a clock signal SCLK and an enabling signal SCS, a plurality of sampling pulse signals are generated according to the clock signal SCLK and the enabling signal SCS, and the sampling pulse signals are output to the control end of the corresponding signal latch module 2;
the signal latch module 2 is input with a corresponding sampling pulse signal, a reset signal and a serial input signal SI, and the signal latch module 2 is controlled to latch and output the serial input signal SI according to the sampling pulse signal and the reset signal.
According to the driving method of the serial-parallel conversion circuit, the sampling pulse signal generating module is used for generating a plurality of different sampling pulse signals and outputting the different sampling pulse signals to each signal latching module. The serial input signals are input to each signal latch module, the serial input signals received by the input ends of the signal latch modules are latched under the control of sampling pulse signals, namely, different signal latch modules latch the input serial input signals under the control of different sampling pulse signals, namely, different signal latch modules are controlled by different sampling pulse signals, so that the current signals cannot change when the current signals are latched in each signal latch module under the control of different sampling pulse signals before new signals are written in, and therefore, the serial-parallel conversion circuit provided by the embodiment of the invention has enough time sequence redundancy to ensure the correct output of data, the difficulty of time sequence design can be reduced, and the stability of high-frequency data transmission is improved.
In a third aspect, as shown in fig. 13, the present invention provides a mode latch circuit, including the above serial-to-parallel conversion circuit and a mode decoder, wherein the output terminal of each signal latch module 2 of the serial-to-parallel conversion circuit is connected to the input terminal of the mode decoder.
Referring to the timing chart illustrated in fig. 10, the START module generates the START signal START (i.e., m_clk0) as a START pulse, triggers the subsequent sampling pulse signal generator to operate and sequentially generates the signals m_clk1 to m_clk5, the START signal START and the signals m_clk1 to m_clk5 are used as control signals of the signal latch module, and the serial input signal SI includes the mode signals D0 to D5 to be sequentially latched, which is independent of the shift register implementation, so that no dislocation phenomenon occurs, and meanwhile, since the mode signals D0 to D5 are sequentially latched and read into the mode decoder, more time is left for configuring the operating state of the subsequent circuit after the selection mode, for example, the D0 and D1 signals can be used for configuring the operating state of the subsequent circuit.
The mode latch circuit provided by the embodiment has higher time sequence redundancy, is suitable for completing the reading of the mode signal under high frequency, is easier to switch between modes, and is suitable for a display drive circuit with a multi-mode working state.
In a fourth aspect, an embodiment of the present invention further provides a display apparatus, including: a serial-parallel conversion circuit as described above, or a mode latch circuit as described above.
In the scheme, the serial-parallel conversion circuit utilizes the sampling pulse signal generation module to carry out logic operation to generate a plurality of sampling pulse signals, the sampling pulse signals are respectively output to each signal latching module, the signal latching module latches the serial input signal SI received by the input end of the signal latching module under the control of the sampling pulse, the serial-parallel conversion circuit is realized independently of a shift register, the dislocation phenomenon is avoided, the sufficient time sequence redundancy is realized, and the serial-parallel conversion circuit is suitable for the stability of high-frequency signal transmission;
correspondingly, the mode latch circuit can latch mode signals in sequence through each signal latch module and read in the mode decoder, can finish the reading of the mode signals under high frequency, is easier to switch between modes, can leave more time for the configuration of the working state of the subsequent circuit after the mode is selected, and is suitable for the display drive circuit with the multi-mode working state.
The above description is only illustrative of the preferred embodiments of the present invention and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in the present invention is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present invention (but not limited to) having similar functions are replaced with each other.
Claims (10)
1. A serial-to-parallel conversion circuit, comprising: the sampling pulse signal generation module is provided with a plurality of output ends which are connected with the control ends of the signal latch modules in a one-to-one correspondence manner;
the sampling pulse signal generation module is used for generating a plurality of sampling pulse signals under the control of a clock signal and an enabling signal and outputting the sampling pulse signals to the control end of the corresponding signal latch module respectively; the sampling pulse signal generation module comprises a starting module and a plurality of cascaded sampling pulse signal generators;
The input end of the starting module is used for receiving the clock signal, the enabling input end of the starting module is used for receiving the enabling signal, and the starting module is used for generating a starting signal according to the clock signal and the enabling signal and outputting the starting signal to the control end of the corresponding signal latching module as a sampling pulse signal;
the clock signal end of the sampling pulse signal generator is used for receiving the clock signal, the input end of the sampling pulse signal generator at the first stage receives the starting signal, the input ends of the sampling pulse signal generators except the sampling pulse signal generator at the first stage are connected with the output end of the sampling pulse signal generator at the previous stage, and the output end of the sampling pulse signal generator is connected with the control end of the corresponding signal latching module;
the signal latching module is used for latching and outputting a serial input signal received by the input end of the signal latching module under the control of a reset signal and the corresponding sampling pulse signal.
2. The serial-to-parallel conversion circuit of claim 1, wherein the start-up module comprises a first or gate, a first nand gate, a first and gate, and a first not gate;
The first input end of the first OR gate is used for receiving the clock signal, the first input end of the first OR gate is connected with the output end of the first NOT gate, and the output end of the first OR gate is connected with the first input end of the first NAND gate;
the second input end of the first NAND gate and the first input end of the first AND gate are used for receiving the enabling signal, and the output end of the first NAND gate is connected with the input end of the first NAND gate and the second input end of the first AND gate;
the output end of the first AND gate is used for outputting the starting signal.
3. The serial-parallel conversion circuit according to claim 1, wherein the sampling pulse signal generator comprises: a first module and a second module;
the clock signal terminals of the first module and the second module are used for receiving the clock signals;
the input end of the first module is connected with the output end of the starting module or the output end of the second module in the upper stage sampling pulse signal generator, and the output end of the first module is connected with the input end of the second module;
the output end of the second module is connected with the control end of the corresponding signal latch module;
The first module is used for selectively outputting the clock signal or the continuous low level signal;
the second module is used for selectively outputting an inverted signal or a continuously low level signal of the clock signal.
4. The serial-to-parallel conversion circuit of claim 1, wherein the sampling pulse signal generator of an odd stage comprises a first module and the sampling pulse signal generator of an even stage comprises a second module;
the clock signal terminals of the first module and the second module are used for receiving the clock signals;
the input end of the first module is connected with the output end of the starting module or the output end of the second module at the upper stage, and the output end of the first module is connected with the control end of the corresponding signal latch module;
the input end of the second module is connected with the output end of the first module at the previous stage, and the output end of the second module is connected with the control end of the corresponding signal latch module;
the first module is used for selectively outputting the clock signal or the continuous low level signal;
the second module is used for selectively outputting an inverted signal or a continuously low level signal of the clock signal.
5. The serial-parallel conversion circuit according to claim 3 or 4, wherein the first module comprises: a second or gate, a first selector, a second not gate, and a third not gate;
the first input end of the second OR gate is connected with the output end of the starting module or the output end of the second module at the upper stage, and the output end of the second OR gate is connected with the control end of the first selector;
the first input end of the first selector is grounded, the second input end of the first selector is used for receiving the clock signal, the output end of the first selector is connected with the second input end of the second OR gate and the input end of the second NOT gate, and the output end of the first selector is used for: selecting and outputting a continuous low-level signal when a low-level signal is input to the control end of the first selector, and selecting and outputting the clock signal when a high-level signal is input to the control end of the first selector;
the output end of the second NOT gate is connected with the input end of the third NOT gate;
the output end of the third NOT gate is used for selectively outputting the clock signal or the continuous low level signal.
6. The serial-to-parallel conversion circuit of claim 5, wherein the second module comprises: a third or gate, a second selector, and a fourth not gate;
The first input end of the third OR gate is connected with the output end of the first module of the previous stage, and the output end of the third OR gate is connected with the control end of the second selector;
the first input end of the second selector is used for receiving a high-level signal, the second input end of the second selector is used for receiving the clock signal, the output end of the second selector is connected with the input end of the fourth NOT gate, and the output end of the second selector is used for: selecting and outputting the high-level signal when the low-level signal is input to the control end of the second selector, and selecting and outputting the clock signal when the high-level signal is input to the control end of the second selector;
the output end of the fourth NOT gate is connected with the second input end of the third OR gate and the control end of the corresponding signal latch module, and the output end of the fourth NOT gate is used for selectively outputting the reverse signal or the continuous low level signal of the clock signal.
7. The serial-parallel conversion circuit of claim 1, wherein the signal latching module comprises: a first transmission gate, a second NAND gate, and a fifth NAND gate;
the input end of the first transmission gate is used for receiving the serial input signal, the first control end of the first transmission gate and the second control end of the second transmission gate are used for receiving the sampling pulse signal, the second control end of the first transmission gate and the first control end of the second transmission gate are used for receiving a reverse signal opposite to the sampling pulse signal, and the output end of the first transmission gate and the first input end of the second NAND gate;
The second input end of the second NAND gate is used for receiving the reset signal, and the output end of the second NAND gate is connected with the input end of the fifth NAND gate;
the output end of the fifth NOT gate is connected with the input end of the second transmission gate, and the output end of the second transmission gate is connected with the first input end of the second NOT gate;
the output end of the fifth NOT gate is used for outputting the serial input signal.
8. A driving method of the serial-parallel conversion circuit according to any one of claims 1 to 7, characterized in that the method comprises:
inputting a clock signal and an enabling signal to a sampling pulse signal generating module, generating a plurality of sampling pulse signals according to the clock signal and the enabling signal, and outputting the sampling pulse signals to a control end of a corresponding signal latching module;
and inputting the corresponding sampling pulse signal, reset signal and serial input signal to the signal latch module, and controlling the signal latch module to latch and output the serial input signal according to the sampling pulse signal and the reset signal.
9. A mode latch circuit comprising a serial-to-parallel conversion circuit as claimed in any one of claims 1 to 7 and a mode decoder, the output of each signal latch module of the serial-to-parallel conversion circuit being connected to an input of the mode decoder.
10. A display device comprising the serial-parallel conversion circuit of any one of claims 1-7.
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| CN110912549A (en) * | 2019-12-05 | 2020-03-24 | 京东方科技集团股份有限公司 | Serial-parallel conversion circuit, driving method thereof and display panel |
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| US6392456B1 (en) * | 1999-01-12 | 2002-05-21 | Hyundai Electronics Industries Co., Ltd. | Analog mixed digital DLL |
| JP2002202764A (en) * | 2000-12-21 | 2002-07-19 | Renei Kagi Kofun Yugenkoshi | Data driver circuit of thin-film transistor liquid crystal display |
| CN104658508A (en) * | 2015-03-24 | 2015-05-27 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving circuit and display device |
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