JP2002202764A - Data driver circuit of thin-film transistor liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of occupancy on a chip and to reduce cost by decreasing circuit elements, specially, digital-analog conversion elements. SOLUTION: This circuit comprises a latch circuit, which individually holds serial data according to timing pulses and outputs latch serial data, a level shifter which is connected to the latch circuit, hold the latch serial data at high voltage, and outputs the high-voltage serial data, a digital-analog converter which is connected to the level shifter and converts the high-voltage serial data into an analog signal, a sample and hold circuit, which is connected to the digital-analog converter and samples and holds the analog signal, a shift register which is connected to the sample and hold circuit, generates a pulse signal according to the timing pulses, and controls the sample and hold circuit with the pulse signal to sample the analog signal; and an output buffer which is connected to the sample and hold circuit and buffers the output of the sample and hold circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data driver circuit for a liquid crystal display, and more particularly to a data driver circuit for a thin film transistor liquid crystal display.

[0002]

2. Description of the Related Art A general thin film transistor is used, for example, for manufacturing a contact type image sensor (CIS) such as a facsimile (FAX machine) and a scanner (Scanner) and other various electronic devices, and a general thin film transistor flat panel. This flat display is also applied to the manufacture of displays.
D), a flat display such as an organic light emitting diode (OLED).

A thin film transistor liquid crystal display mainly comprises a thin film transistor element and a flat display element. The thin film transistor element is composed of a large number of thin film transistors and is arranged in a matrix system. Each corresponds to one pixel electrode. The above-mentioned thin film transistor mainly includes a gate (Gate) formed on an insulating substrate and a gate dielectric layer (Gate).
Dielectric), a channel layer, and a source / drain stack. The thin film transistor is used as a switching element of a flat display unit.

FIG. 1 is a block diagram showing a data driver circuit of a conventional thin film transistor liquid crystal display. The data driver circuit of the thin film transistor liquid crystal display includes a shift register 10 and a latch circuit 14.
, Level shifter 16 and digital-to-analog converter 18
And an output buffer 20. If 300 channel6
Taking a bit data driver as an example, the structure of the prior art requires the number of unit elements calculated as follows. The shift register 10 needs to connect 100 registers, and the latch circuit 14 has 300 channels × 6.
bit × 2 latch devices are required, and multiplying by 2 is 1
This is because one set is used for sampling and one set is used for holding. The level shifter 16 requires 300 channel × 6 bit level shift elements. Digital-to-analog converter 18
Requires a resistor group and 300 sets of multiplexers, each set of multiplexers has 128 + 64 + 32
+ 16 + 8 + 4 + 2 = 254 MOS transistors and 128
This requires 128 connections, but these 128 connections must traverse the entire chip. Output buffer 2
0 requires 300 output buffer elements.

[0005]

As can be seen from the above, the data driver of the thin film transistor liquid crystal display according to the prior art requires a large number of circuit elements. Because it occupies most of the area, the cost was very high.

Accordingly, an object of the present invention is to reduce the number of circuit elements, and in particular, to reduce the area occupied on a chip by reducing the number of circuit elements of a digital-to-analog converter.
It is an object of the present invention to provide a new thin film transistor liquid crystal display data driver circuit that can reduce the cost.

[0007]

In order to solve the above problems and achieve the desired object, a data driver circuit for a thin film transistor liquid crystal display according to the present invention comprises a latch circuit, a level shifter, a digital-to-analog converter,
It comprises a sampling and holding circuit, a shift register, and an output buffer. The data driver circuit of the thin film transistor liquid crystal display individually latches serial data based on a timing pulse by a latch circuit, and then outputs latched serial data.The level shifter is electrically connected to the latch circuit.
The latch serial data is set to a high voltage, and high-voltage serial data is output. Digital-to-analog converter
The sampling and holding circuit is electrically connected to the level shifter and converts high-voltage serial data into an analog signal. The sampling and holding circuit is for electrically sampling and holding the analog signal. The shift register is electrically connected to the sampling and holding circuit. At this time, the shift register uses a pulse signal generated based on the timing pulse to control each channel (ch).
The sampling and holding circuit of an annel is controlled to sequentially sample an analog signal. The output buffer is electrically connected to the sampling and holding circuit and buffers the output of the sampling and holding circuit.

According to a preferred embodiment, the sampling and holding circuit has a first switch having a first end and a second end, a first switch having a first end and a second end, and the first end being the first end of the first switch. A second switch electrically connected to the analog signal and a first end and a second end;
A first capacitor having a first end electrically connected to a second end of the first switch and a second end grounded (or electrically connected to a fixed level power supply); a first end and a second end; A third terminal having a first end electrically connected to the first end of the first capacitor and a second end electrically connected to the output buffer;
A switch, a first end and a second end, wherein the first end is a second end.
A second terminal electrically connected to the second terminal of the switch and having the second terminal grounded (or electrically connected to a fixed level power supply);
A second end of the second capacitor, the first end being electrically connected to the first end of the second capacitor;
A fourth switch having an end electrically connected to the output buffer, wherein the pulse signal alternately opens and closes two sets of the first switch and the fourth switch and the second switch and the third switch. Things.

According to a preferred embodiment, the output buffer comprises:
An operational amplifier including a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the non-inverting input terminal is electrically connected to a second terminal of the fourth switch, and the inverting input terminal is electrically connected to an output terminal. Things. In the sampling / holding circuit according to the preferred embodiment, the fourth switch of each channel is closed, the second switch and the third switch are opened, and the first switch of each channel is turned on at the sampling / holding phase at the first time point. Then, the circuit is sequentially closed and then opened by the output pulse of the shift register, and the potential data of the analog signal is sequentially stored in the first capacitor of each channel. Sampling at the second time
During the holding phase, the first switch and the fourth switch of each channel are used.
The switch is opened, the third switch is closed, and the second switch of each channel is opened after being sequentially closed by the output pulse of the shift register, and the potential data of the analog signal is sequentially stored in the second capacitor of each channel. . At the same time, the first capacitor outputs the previously stored potential data of the analog signal to the output buffer.

In summary, in the data driver circuit of the thin film transistor liquid crystal display of the present invention,
The channel Channel of each display includes a set of shift registers, a set of sampling and holding circuits,
Only one set of output buffers is provided, and a small number of one to several sets of latch circuits, a level shifter,
As will be understood from the above, the present invention can reduce the number of circuit elements, can significantly reduce the chip area, and can reduce the cost because only a digital-to-analog converter is required.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a preferred embodiment based on a data driver circuit of a thin film transistor liquid crystal display according to the present invention.
, The latch circuit 30 individually latches the data by the timing pulse and outputs latch serial data. The level shifter 32 is electrically connected to the latch circuit 30, and the latch serial data can be set to a high voltage by the level shifter 32. For example, the level shifter 32 is composed of a transistor, and uses a transistor characteristic to increase an input latch serial data voltage. Then, the level shifter 32
Are electrically connected to a digital-to-analog converter 34, which causes the digital-to-analog converter 34 to convert high-voltage serial data into an analog signal. Since the sampling and holding circuit 50 is electrically connected to the digital-to-analog converter 34, the analog signal can be sampled and held, and the shift register 36 is electrically connected to the sampling and holding circuit 50. The shift register 36 controls the sampling / holding circuit 50 based on a pulse signal that generates a timing pulse, and performs sampling on an analog signal. Finally, the analog signal after being sampled or held is output through an output buffer 60 that buffers the output of the sampling and holding circuit 50.

The sampling and holding circuit 50 includes two capacitors 53 and 55 and four switches 52, 54, 56,
58, and these four switches 52,
Numerals 54, 56 and 58 control the two capacitors 53 and 55 to alternately perform the sampling and holding operations. The output buffer 60 includes an operational amplifier 70.
It consists of The operation of the combination of the sampling and holding circuit 50 and the output buffer 60 is as described below.

FIG. 3A is a circuit diagram showing a preferred example of the sampling and holding circuit. As shown in FIG.
The first switch has a first end and a second end.
And a second end. The first end of the first switch 52 is electrically connected to the first end of the second switch 56, and the first end of the first switch 52 is connected to the input end (Vin). Since the first end of the first switch 52 is electrically connected to the first end of the second switch 56, the first end of the second switch 56 is electrically connected to the input end (Vin). It is. The first capacitor 53 has a first end and a second end, the third switch 54 has a first end and a second end, and the first end of the first capacitor 53 is a first switch 52.
, A second end of the first switch 52 is electrically connected to a first end of the third switch 54, and a first end of the first capacitor 53 is connected to the first switch. Since it is electrically connected to the second end of the first switch 52, the first end of the third switch 54 and the first end of the first capacitor 53 are conductive, and the second end of the first capacitor 53 has a fixed level. Connected to a power source or directly grounded. The second capacitor 55 has a first end and a second end.
The fourth switch 58 has a first terminal and a second terminal. The first terminal of the second capacitor 55 is electrically connected to the second terminal of the second switch 56, and the second switch The second end of the second switch 56 is electrically connected to the first end of the fourth switch 58, and the first end of the second capacitor 55 is electrically connected to the second end of the second switch 56. , The first end of the fourth switch 58 and the second capacitor 55
Is electrically connected to the first end of the second capacitor 55
Are connected to a fixed level power supply or directly grounded. The operational amplifier 70 has a non-inverting input terminal (V +), an inverting input terminal (V-), and an output terminal (Vout).
And the non-inverting input terminal (V +) is connected to the third
The third switch 5 is electrically connected to the second end of the switch 54,
4 is electrically connected to the second terminal of the fourth switch 58, and the non-inverting input terminal (V +) is connected to the third switch 54.
Of the fourth switch 58 and the non-inverting input terminal (V +) are electrically connected, and the inverting input terminal (V
-) Is electrically connected to the output terminal (Vout).

FIG. 3B shows the sampling time at the first time point.
As shown in the equivalent circuit diagram of the holding circuit configuration diagram, at the first sampling and holding phase, the first switch 52 and the fourth switch 58 are closed, and the second switch 56 and the third switch 54 are open. The circuit configuration diagram is as described below. The first switch 52 has a first end and a second end, the first end is electrically connected to an input end (Vin), the first capacitor 53 has a first end and a second end, The second end of the switch 52 is electrically connected to the first end of the first capacitor 53, and the second end of the first capacitor 53 is grounded. Second capacitor 55
Has a first end and a second end, the second end of the second capacitor 55 is grounded, and the fourth switch 58 has a first end and a second end, and the first switch of the fourth switch 58 The end is electrically connected to the first end of the second capacitor 55. The operational amplifier 70 has a non-inverting input terminal (V +), an inverting input terminal (V-), and an output terminal (Vout). The non-inverting input terminal (V +) of the operational amplifier 70 is 4 switches 5
8 is electrically connected to the second end of the
Is electrically connected to the output terminal (Vout). As can be seen, during the sampling / holding phase at the first time, the first switch 52 and the fourth switch 58 are closed, and the second switch 56 and the third switch are open. And the second capacitor 55 outputs the potential data of the analog signal. It should be particularly noted that the first switch 52 is not always closed during the sampling / holding phase at the first time point, and the first switch 52 for every three channels is sequentially closed according to the order of the channels. And then open immediately, the first of every three channels
The capacitor 53 sequentially stores the potential data of the analog signal.

FIG. 3 (c) shows the sampling time at the second time point.
As shown in the equivalent circuit diagram of the holding circuit configuration diagram, the first switch 52 and the fourth switch 58 are open, and the second switch 56 and the third switch 54 are closed during the sampling and holding phase at the second time point. The circuit configuration diagram is as described below. The second switch 56 has a first end and a second end, the first end is electrically connected to an input end (Vin), the second capacitor 55 has a first end and a second end, The second end of the switch 56 is connected to a second capacitor 55
Is electrically connected to the first end of the second capacitor, and the second end of the second capacitor is grounded. The first capacitor 53 has a first end and a second end, a second end of the first capacitor 53 is grounded,
The third switch 54 has a first end and a second end,
A first end of the switch 54 is electrically connected to a first end of the first capacitor 53. The operational amplifier 70 includes a non-inverting input terminal (V +), an inverting input terminal (V-), and an output terminal (Vout).
+) Is electrically connected to the second terminal of the third switch 54, and the inverting input terminal (V−) of the operational amplifier 70 is electrically connected to the output terminal (Vout). As can be seen, during the sampling and holding phase at the second point in time, the first
The switch 52 and the fourth switch 58 are open, and the second switch 56 and the third switch 54 are closed.
The capacitor 53 outputs the potential data of the analog signal,
The second capacitor 55 stores the potential data of the analog signal. It should be particularly noted that the second switch 56 is not always closed during the sampling / holding phase at the second point in time.
The second switches 56 for each channel are opened immediately after they are sequentially closed, so that the potential data of the analog signals are sequentially stored in the second capacitors 55 for each of the three channels.

As can be understood from the above, the sampling and holding circuit includes two capacitors and four switches, and utilizes the four switches to perform the above-described operation.
This is to control the number of capacitors and alternately perform sampling and holding operations.

If a data driver of 300 channels and 6 bits is taken as an example, the present invention is constituted by the number of unit elements calculated as follows. The latch circuit requires 3 × 6 bit latch devices. The level shifter requires 3 × 6 bit level shift elements. The digital-to-analog converter requires a resistor group and three sets of multiplexers, and the multiplexer has 128 + 64 + 32 +
It requires 16 + 8 + 4 + 2 = 254 MOS transistors and 128 connections, and the digital-to-analog converter
It only requires output connections across all three chips. A shift register requires 100 linked register elements. 300 sampling and holding circuits are required. 300 output buffers are required. As can be seen, the present invention compares the prior art thin film transistor liquid crystal display data driver with:
For each channel, a shift register, sampling and
It only has a holding circuit and an output buffer, and the whole chip only has one to several sets of latch circuits, a level shifter, and a digital-to-analog converter, and a sampling and holding circuit is added. However, if the circuit area is compared with the reduced area described above, it is insignificant.

As described above, the present invention has been disclosed by the preferred embodiments. However, the embodiments are not intended to limit the present invention, and as will be easily understood by those skilled in the art, the technical features of the present invention will be described. Since appropriate changes and modifications can naturally be made within the scope of the idea, the scope of patent protection should be determined based on the claims and equivalents thereof.

[0019]

As described above, in the data driver circuit of the thin-film transistor liquid crystal display according to the present invention, each display channel has one set of shift register, one set of sampling and holding circuit, and one set of output. Buffer and only one buffer
Since only a couple of latch circuits, a level shifter, and a digital-to-analog converter are required, the number of circuit elements can be reduced, the chip area can be significantly reduced, and the cost can be reduced.

A data driver circuit of a thin film transistor liquid crystal display according to the present invention uses a small number of latch circuits, a level shifter, and a digital-to-analog converter, and has a data driving structure by adding a sampling and holding circuit. To be completed,
Since the number of circuit elements can be significantly reduced and the connection area can be reduced, product cost can be reduced and competitiveness can be improved. Therefore, the industrial use value is high.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data driver circuit of a conventional thin film transistor liquid crystal display.

FIG. 2 is a block diagram of a preferred embodiment based on a data driver circuit of a thin film transistor liquid crystal display according to the present invention.

FIG. 3A is a circuit configuration diagram of a preferred example of a sampling and holding circuit based on a data driver circuit of a thin film transistor liquid crystal display according to the present invention, and FIG.
FIG. 3 is an equivalent circuit diagram of the sampling and holding circuit at a first time point, and FIG. 3C is an equivalent circuit diagram of the sampling and holding circuit at a second time point.

[Explanation of symbols]

 36 shift register 30 latch circuit 32 level shifter 34 digital-to-analog converter 60 output buffer 40 digital display data 52 first switch 56 second switch 54 third switch 58 fourth switch 53 first capacitor 55 second capacitor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623G 623H 623L F-term (Reference) 2H093 NA16 NC16 NC22 NC23 NC26 NC34 NC35 ND54 5C006 AF82 BB16 BC06 BC12 BC13 BF03 BF04 BF11 BF25 BF46 EB05 FA43 FA51 5C080 AA10 BB05 DD23 DD27 DD30 JJ02 JJ03

Claims (4)

[Claims] 1. A latch circuit for individually latching serial data based on a timing pulse and then outputting the latched serial data; a latch circuit electrically connected to the latch circuit; A level shifter that outputs serial data, a digital-to-analog converter that is electrically connected to the level shifter and converts the high-voltage serial data into an analog signal, and is electrically connected to the digital-to-analog converter and samples the analog signal. And a sampling and holding circuit for holding, and electrically connected to the sampling and holding circuit to generate a pulse signal, the pulse signal controlling the sampling and holding circuit based on the timing pulse, and Sampler A shift register for grayed, the while being electrically connected to a sample and hold circuit, the data driver circuit thin film transistor liquid crystal display, characterized by comprising an output buffer for buffering the output of the sampling hold circuit. A first switch having a first end and a second end; a first switch having a first end and a second end, wherein the first end is the first end of the first switch. A second switch connected to the analog signal and a first end and a second end, wherein the first end is electrically connected to the second end of the first switch; The second
A first capacitor having an end electrically connected to a fixed potential, a first end and a second end, wherein the first end is electrically connected to the first end of the first capacitor, and the second end is A third switch electrically connected to the output buffer; a first end and a second end, wherein the first end is electrically connected to a second end of the second switch, and the second end has a fixed potential. A second capacitor electrically connected to the second capacitor, a first end and a second end, wherein the first end is electrically connected to a first end of the second capacitor, and the second end is electrically connected to the output buffer. A fourth switch to be connected, wherein the pulse signal alternately opens and closes two sets of the first switch and the fourth switch, and the second switch and the third switch. Characterized by A data driver circuit for a thin film transistor liquid crystal display according to claim 1. 3. The non-inverting input terminal of the output buffer,
An operational amplifier having an inverting input terminal and an output terminal, wherein the non-inverting input terminal is electrically connected to the second terminal of the fourth switch, and the inverting input terminal is electrically connected to the output terminal. 3. The data driver circuit for a thin film transistor liquid crystal display according to claim 2, wherein 4. At a first point in time, the first switch and the fourth switch are closed, the second switch and the third switch are open, and the first capacitor is connected to the potential of the analog signal. The data is stored, and at a second time, the first switch and the fourth switch are opened, the second switch and the third switch are closed, and the first capacitor is connected to the stored analog signal. 3. The data driver circuit according to claim 2, wherein the data driver outputs potential data to the output buffer.