1226506 修正日期93.U5 06716twfl.doc/006 玖、發明說明： 本發明是有關於一種液晶顯示器的資料驅動器架構， 且特別是有關於一種薄膜電晶體液晶顯示器的資料驅動器 電路。 ~般薄膜電晶體可運用於傳真機（FAX machine)、接 觸式影像感測器（CIS)，例如掃描器（Scanner)，以及其 它各種電子元件等之製造外，亦可運用於一般薄膜電晶體 平面顯示器之製造，其中平面顯示器則可以是液晶顯示器 (L c D )、有機光激發雙極晶體（〇led)等平面顯籲 不器。 薄膜電晶體平面顯示器主要係由薄膜電晶體元件和平 面餘頁不兀件構成，其中薄膜電晶體元件係由多個薄膜電晶 體組成，而以矩陣的方式排列，其中每一個薄膜電晶體都 對應一個畫素電極(Pixel Electrode)。上述之薄膜電晶體主 要係由在一絕緣基材上形成之閘極（Gate)、閘介電層（Gate Dielectric)、通道層（channel Layer)、與源極/汲極堆疊而 成’此薄膜電晶體係用來作爲平面顯示單元的開關元件。 請參照第1A圖，其繪示的是根據一般薄膜電晶體液_ 晶顯示器的資料驅動器架構之實施例方塊圖。此薄膜電晶 體液晶顯示器的資料驅動器架構包括：移位暫存器10、閂 鎖電路14、準位遷移器16、數位類比轉換器18以及輸出 緩衝器2〇。若以3〇0 channel 6 bit的資料驅動器爲例，傳 統的架構需要以下所計算出的個數之單元元件。其中移位 暫存器10需要1〇〇個暫存器串成；閂鎖電路I4需要300 ehannel* 6 Mt*2個閂鎖器，而乘以2的原因是因爲一 1226506 06716twf 1 .doc/006 修正日期 93 _ 1.15 組作取樣，一組做保持；準位遷移器16需要300 channel * 6 bit個準位遷移元件；數位類比轉換器18需要電阻 串，300組多工器，而每組多工器需要128 + 64+ 32 + 16 + 8 + 4+ 2 = 254個MOS電晶體及128條繞線，這128條 繞線需橫跨整個晶片；輸出緩衝器20則需要300個輸出 緩衝元件。 請參照第1B圖，繪示的是實現一般薄膜電晶體液晶 顯示器的資料驅動器架構之電路方塊圖。在第1B圖中， 第1A圖之移位暫存器10係由第1B圖之100個D型正反_ 器所實現。上述之閂鎖電路14在第1圖中係分爲2個300 channel* 6 bit的單元，其中，一個單元係爲接收資料-R 、資料-G與資料-B。而另外一個單元則依照載入（load) 信號將前一級閂鎖單元的資料載入。準位遷移器16係由 300個6位元的轉位遷移器所組成，數位類比轉換器18係 由300個128至1的多工器所組成，其中，每一個多工器 係接收P灰階1至P灰階64與η灰階1至η灰階64的輸 入信號，然後經過多工器運算後由輸出端輸出。輸出緩衝 器20則由300個輸出緩衝器組成。 · 第1C圖繪示的是實現一般薄膜電晶體液晶顯示器的 128-1多工器之電路圖。若以M0S電晶體來實現128-1多 工器，其在第1層需要有128個M0S電晶體，第二層則 需要64 M0S電晶體，第三層需要32個M0S電晶體，第 4層需要16個M0S電晶體，第5層需要8個M0S電晶 體，第6層需要4個M0S電晶體，第7層需要2個M0S 電晶體，因此，當以M0S電晶體來實現128-1多工器時， 1226506 06716twf 1 .d〇c/〇〇6 修正日期 93.1.15 總共需要254個MOS電晶體。 由上可知，此習知之薄膜電晶體液晶顯示器的資料驅 動器需要大量的電路元件，尤其其中之數位類比轉換器的 元件與繞線極多，佔晶片極大部分的面積，故成本也就相 當高。 有鑒於此，本發明提出一種新的薄膜電晶體液 晶顯示器的資料驅動器架構，能減少電路元件，尤其是減 少數位類比轉換元件，故可縮小所佔之晶片面積，進而降 低成本。 本發明提出之一種薄膜電晶體液晶顯示器的資料驅動鲁 器架構包括：閂鎖電路、準位遷移器、數位類比轉換器、 取樣與保持電路、移位暫存器、以及輸出緩衝器。此薄膜 電晶體液晶顯示器的資料驅動器架構利用閂鎖電路依據時 序時脈將串列資料個別鎖住，再輸出閂鎖串列資料，而準 位遷移器耦接至閂鎖電路，使之將閂鎖串列資料升至高 壓，輸出高壓串列資料。數位類比轉換器耦接至準位遷移 器，用以將高壓串列資料轉爲類比信號’而取樣與保持電 路耦接至數位類比轉換器，用以將類比信號作取樣與保 持。移位暫存器耦接至取樣與保持電路’此時移位暫存器籲 依據時序時脈產生之脈衝信號控制各通道（channel)之取樣 與保持電路依序對類比信號作取樣。輸出緩衝器耦接至取 樣與保持電路用以緩衝取樣與保持電路之輸出。 本發明之實施例其中的取樣與保持電路’包括：第一 開關，具有第一端及第二端；第二開關’具有第一端及第 二端，該第二開關之第一端耦接到第一開關之第一端，且 連接至類比信號；第一電容’具有第一端及弟一纟而’電谷 1226506 06716twf 1 .doc/006 修正日期 93.1 · 15 之第一端耦接至第一開關之第二端，而電容之第二端耦接 到地（或固定準位之電源）；第三開關，具有第一端及第二 端，第三開關之第一端耦接到第一電容之第一端，第三開 關之第二端耦接到輸出緩衝器；第二電容，具有第一端及 第二端，電容之第一端耦接至第二開關之第二端，電容之 第二端耦接到地（或固定準位之電源）；以及第四開關，具 有第一端及第二端，第四開關之第一端耦接到第二電容之 第一端，第四開關之第二端耦接到輸出緩衝器，該脈衝信 號使第一開關及第四開關與第二開關及第三開關兩組輪流_ 開路及閉路。 本發明之實施例中輸出緩衝器係爲運算放大器，具有 非反向輸入端、反向輸入端及輸出端，該非反向輸入端親 接到第四開關之第二端，反向輸入端耦到輸出端。本發明 之另一實施例中在第一時間點之取樣與保持相位時，各通 道之第四開關閉路，第二開關及第三開關開路，各通道之 第一開關依移位暫存器之輸出脈衝依序閉路後再開路，使 每一通道之第一電容依序儲存類比信號之電位資料；在第 二時間點之取樣與保持相位時，各通道之第一開關及第四# 開關開路，第三開關閉路，各通道之第二開關依移位暫存 器之輸出脈衝依序閉路後再開路，使各通道之第二電容依 序儲存類比信號之電位資料；同時第一電容將之前其儲存 之類比信號之電位資料輸出至輸出緩衝器。 綜合以上所述，可知薄膜電晶體液晶顯示器的資料驅 動器架構中，每一顯示之Channel僅包含一組移位暫存器、 一組取樣與保持電路及一組輸出緩衝器，而整個晶片僅需 1226506 06716twfl.doc/006 修正日期 93.1.15 要少數的一至數組閂鎖電路、準位遷移器及數位類比轉換 器’由此可知，本發明可減少電路及大幅減少晶片面積’ 故而降低成本。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖繪示的是根據一般薄膜電晶體液晶顯示器的 資料驅動器架構之實施例方塊圖； 第1B圖繪示的是實現一般薄膜電晶體液晶顯示器的 資料驅動器架構之電路方塊圖。 第1C圖繪示的是實現一般薄膜電晶體液晶顯示器的 128-1多工器之電路圖。 桌2圖繪不的是根據本發明薄膜電晶體液晶顯示器的 資料驅動器架構之一較佳實施例方塊圖； 弟3 A圖繪不的是根據本發明薄膜電晶體液晶顯示器 的資料驅動器架構之取樣及保持電路之一較佳實施例電路 圖； 第3B圖繪示的是根據本發明薄膜電晶體液晶顯示器 的貝料驅動器架構之取樣及保持電路第一'時間點之等效電 路圖；以及 第3C圖繪示的是根據本發明薄膜電晶體液晶顯示器 的資料驅動器架構之取樣及保持電路第二時間點之等效電 路圖。 圖式之標示說明： 1226506 06716twf 1 .doc/006 修正曰期 93.1 · 15 10、36 :移位暫存器 14、30 :閂鎖電路 16、32 :準位遷移器 18、34 :數位類比轉換器 20、60 :輸出緩衝器 22 :時脈 2 4、4 0 : —^串列資料 52、 54、56、58 :開關 53、 55 :電容 · 實施例 請參照第2圖，其繪示的是根據本發明薄膜電晶體液 晶顯示器的資料驅動器架構之一較佳實施例方塊圖。首先 數位顯示資料40輸入至閂鎖電路30中，而閂鎖電路30 依據時序時脈將資料個別鎖住，再輸出閂鎖串列資料。而 準位遷移器32耦接至閂鎖電路30，可將閂鎖串列資料經 準位遷移器32升至高壓。例如，準位遷移器32可由一電 晶體所組成，並利用電晶體特性將輸入之閂鎖串列資料的 電壓升壓。然後準位遷移器32耦接至數位類比轉換器34，籲 使數位類比轉換器34將高壓串列資料轉爲類比信號。由 於取樣與保持電路50耦接至數位類比轉換器34，故其可 將類比信號作取樣與保持，又由於移位暫存器36耦接至 取樣與保持電路50，使移位暫存器36依據時序時脈產生 脈衝信號，來控制取樣與保持電路5〇對類比信號作取樣° 最後經取樣與保持後的類比信號將經輸出緩衝器6〇 出，其用以緩衝取樣與保持電路50之輸出。 1226506 06716twfl.doc/006 修正日期 93.1.15 其中取樣與保持電路50是由兩個電容53、55與四個 開關52、54、56、58所組成的，此四個開關52、54、56、 58可控制這兩個電容53、55交替做取樣與保持的動作， 而輸出緩衝器70是由一運算放大器所組的。取樣與保持 電路50及輸出緩衝器70組成後運作時的情況如下所述。 請參考第3A圖，其繪示的是取樣及保持電路之較佳實施 例電路圖。第一開關52具有第一端及第二端，第二開關56 具有第一端及第二端，而第一開關52的第一端耦接到第 二開關56的第一端，且第一開關52的第一端耦接到輸入_ 端(Vin)，又因第一開關52的第一端耦接到第二開關56的 第一端，所以第二開關56與輸入端(Vin)是相通的，第一 電容53具有第一端及第二端，第三開關54具有第一端及 第二端，而第一電容53的第一端與第一開關52的第二端 耦接，且第一開關52的第二端與第三開關54的第一端耦 接，又因第一電容53的第一端與第一開關52的第二端耦 接，所以第三開關54的第一端與第一電容53第一端相通， 而第一電容53的第二端接到固定準位之電源或直接接地； 第二電容55具有第一端及第二端，第四開關58具有第一籲 端及第二端，而第二電容55的第一端與第二開關56的第 二端耦接，且第二開關56的第二端與第四開關58的第一 端耦接，又因第二電容55的第一端與第二開關56的第二 端耦接，所以第四開關58的第一端與第二電容的第一端 相通，而第二電容55的第二端接到固定準位之電源或直 接接地，運算放大器70具有非反向輸入端(V+)、反向輸 入端（V-)及輸出端（Vout)，該非反向輸入端（V+)與第三開 1226506 06716twfl.doc/006 修正日期 93.1.15 關54的第二端耦接’而第三開關54的第二端與第四開關 58的第二端耦接’且非反向輸入端(V+)與第三開關54的 第二端耦接，所以第四開關58的第二端與非反向輸入端(V + )相通，而該反向輸入端(V-)與輸出端(Vout)耦接。 請參考第3B圖’其繪示的是第一時間點的取樣及保 持電路圖之等效電路’當第一時間點之取樣與保持相位 時，第一開關52與第四開關58閉路，第二開關56與第 三開關54開路。其電路圖如下所述：第一開關52具有第 一端及第二端’而第一端耦接至輸入端(Vin)，第一電容53_ 具有第一端及第二端，而第一開關52的第二端耦接至第 一電容53的第一端，且第一電容53的第二端耦接地。第 二電容55具有第一端及第二端，而第二電容55第一端耦 接地，第四開關58具有第一端及第二端，而第四開關58 的第一端耦接至第二電容55的第二端，運算放大器70具 有非反向輸入端（v+)、反向輸入端（V-)及輸出端(Vout)， 而運算放大器70的非反向輸入端(V+)稱接至第四開關58 的第二端，且運算放大器70的反向輸入端(V-)耦接至輸 出端(Vout)。由此可看出第一時間點之取樣與保持相位時，籲 爲第一開關52與第四開關58閉路，而第二開關56與第 三開關54開路’則第一電容53在儲存類比信號之電位資 料，第二電容55將類比信號之電位資料輸出。要特別注 意的是在第一時間點之取樣與保持相位時，第一開關52 並非一直閉路；而是依照通道的順序，每三個通道的第一 開關52依序閉路後隨即開路，使每三個通道的第一電容53 依序儲存類比信號之電位資料。 1226506 06716twfl.doc/006 修正日期 93.1.15 請參考第3C圖，其繪示的是第二時間點的取樣及保 持電路圖之等效電路，當第二時間點之取樣與保持相位 時，第一開關52與第四開關58開路，而第二開關56與 弟二開關54閉路。其電路圖如下所述··第一^開關56具有 第一端及第二端，而第一端耦接至輸入端(Vin)，第二電容 55具有弟一端及第二端，而第二開關56的稱接至弟一電 容55的第一端，而第二電容55的第二端耦接地。第一電 容53具有第一端及第二端，而第一電容53第一端耦接地， 第三開關53具有第一端及第二端，而第三開關53的第一鲁 端耦接至第一電容53的第二端，運算放大器70具有非反 向輸入端(V+)、反向輸入端(v_)及輸出端（Vout)，而運算 放大器7〇的非反向輸入端(V+)耦接至第三開關的第二端， 且運算放大器70的反向輸入端（V-)耦接至輸出端 (Vout)。由此可看出第二時間點之取樣與保持相位時，爲 第一開關52與第四開關58開路，而第二開關56與第三 開關54閉路，則第一電容53將類比信號之電位資料輸出， 第二電容55在儲存類比信號之電位資料。要特別注意的 是在第二時間點之取樣與保持相位時，第二開關56並非籲 一直閉路；而是依照通道的順序，每三個通道的第二開關 56依序閉路後隨即開路，使每三個通道的第二電容55依 序儲存類比信號之電位資料。 綜合以上所述可知取樣與保持電路中包含兩個電容 及四個開關，並利用此四個開關來控制這兩個電容輪流做 取樣與保持的動作。 若同樣以300 channel 6 bit的資料驅動器爲例，本發 12 1226506 06716twfl.doc/006 修正日期 93.1.15 明需要以下所計算出的個數之單元元件組成。其中閂鎖電 路需要3* 6 bit個閂鎖器；準位遷移器需要3* 6 bit個 準位遷移元件；數位類比轉換器需要電阻串，3組多工器， 而多工器需要 128+ 64+ 32+ 16+ 8 + 4+ 2= 254 個 MOS 電晶體及128條繞線，數位類比轉換器僅3條輸出繞線會 橫跨整個晶片；移位暫存器需要1〇〇個暫存元件串成；取 樣與保持電路需要300個；輸出緩衝器則需要300個，由 - 此可看出本發明較傳統的薄膜電晶體液晶顯示器資料驅動 _ 器上每一通道僅包含移位暫存器、取樣與保持電路及輸出馨 · 緩衝器；而整個晶片僅包含一至數組閂鎖電路、準位遷移 器及數位類比轉換器，雖然多出了取樣與保持電路，但其 電路面積與上述節省的面積相較，可以說是微不足道。 雖然本發明已以一較佳實施例揭露如上，然其並非用 ’ 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 · 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 131226506 Revised date 93.U5 06716twfl.doc / 006 发明, Description of the invention: The present invention relates to a data driver architecture for a liquid crystal display, and more particularly to a data driver circuit for a thin film transistor liquid crystal display. ~ Thin film transistors can be used in facsimile machines (FAX machines), contact image sensors (CIS), such as scanners, and various other electronic components. It can also be used in general thin film transistors. The manufacture of flat displays, where flat displays can be liquid crystal displays (L c D), organic light-excited bipolar crystals (OLEDs) and other flat displays. The thin film transistor flat display is mainly composed of a thin film transistor element and a planar blank sheet. The thin film transistor element is composed of a plurality of thin film transistors and arranged in a matrix manner. Each of the thin film transistors corresponds to One pixel electrode. The above-mentioned thin-film transistor is mainly formed by stacking a gate, a gate dielectric, a channel layer, and a source / drain formed on an insulating substrate. The transistor system is used as a switching element of a flat display unit. Please refer to FIG. 1A, which illustrates a block diagram of an embodiment of a data driver architecture according to a general thin film transistor liquid crystal display. The data driver architecture of the TFT LCD includes: a shift register 10, a latch circuit 14, a level shifter 16, a digital analog converter 18, and an output buffer 20. If we take a data driver with a channel of 6 bits as an example, the traditional architecture requires the number of unit elements calculated below. Among them, the shift register 10 needs 100 registers in series; the latch circuit I4 needs 300 ehannel * 6 Mt * 2 latches, and the reason for multiplying by 2 is because of a 1226506 06716twf 1 .doc / 006 Correction date 93 _ 1.15 Group for sampling and one for holding; level shifter 16 requires 300 channel * 6 bit level shifting components; digital analog converter 18 requires resistor string, 300 sets of multiplexers, and each set The multiplexer requires 128 + 64+ 32 + 16 + 8 + 4+ 2 = 254 MOS transistors and 128 windings. These 128 windings need to span the entire chip. The output buffer 20 requires 300 output buffers. element. Please refer to FIG. 1B, which shows a circuit block diagram of a data driver architecture for implementing a general thin film transistor liquid crystal display. In FIG. 1B, the shift register 10 in FIG. 1A is implemented by 100 D-type flip-flops in FIG. 1B. The above-mentioned latch circuit 14 is divided into two 300 channel * 6 bit units in the first figure, and one unit is for receiving data-R, data-G, and data-B. The other unit loads the data of the previous latch unit according to the load signal. The level shifter 16 is composed of 300 6-bit transposition shifters, and the digital analog converter 18 is composed of 300 128 to 1 multiplexers, where each multiplexer receives P gray The input signals of level 1 to P gray level 64 and η gray level 1 to η gray level 64 are then output by the output terminal after being multiplexed. The output buffer 20 is composed of 300 output buffers. · Figure 1C shows a circuit diagram of a 128-1 multiplexer that implements a general thin-film transistor liquid crystal display. If a 128-1 multiplexer is implemented with M0S transistors, it requires 128 M0S transistors on the first layer, 64 M0S transistors on the second layer, 32 M0S transistors on the third layer, and 4th layer 16 M0S transistors are needed, 8 M0S transistors are required for the fifth layer, 4 M0S transistors are required for the 6th layer, and 2 M0S transistors are required for the 7th layer. Therefore, when M0S transistors are used to achieve more than 128-1 1226506 06716twf 1 .doc / 〇〇6 revision date 93.1.15 A total of 254 MOS transistors are required. It can be known from the above that the data driver of the conventional thin film transistor liquid crystal display requires a large number of circuit components, especially the digital analog converter has a large number of components and windings, which occupy a large area of the chip, so the cost is relatively high. In view of this, the present invention proposes a new thin-film transistor liquid crystal display data driver architecture, which can reduce circuit elements, especially a few bit analog conversion elements, so the area occupied by the chip can be reduced, thereby reducing costs. A data-driven router architecture of a thin film transistor liquid crystal display provided by the present invention includes a latch circuit, a level shifter, a digital analog converter, a sample and hold circuit, a shift register, and an output buffer. The data driver architecture of this thin-film transistor liquid crystal display uses a latch circuit to individually lock the serial data according to the timing clock, and then outputs the latch serial data, and the level shifter is coupled to the latch circuit to enable it to latch The lock serial data is raised to high voltage, and the high voltage serial data is output. The digital analog converter is coupled to the level shifter for converting the high-voltage serial data into an analog signal 'and the sample and hold circuit is coupled to the digital analog converter for sampling and holding the analog signal. The shift register is coupled to the sample and hold circuit. At this time, the shift register calls for controlling the sampling and holding circuits of each channel to sequentially sample the analog signal according to the pulse signal generated by the timing clock. The output buffer is coupled to the sample and hold circuit to buffer the output of the sample and hold circuit. In the embodiment of the present invention, the sample and hold circuit includes a first switch having a first terminal and a second terminal; a second switch having a first terminal and a second terminal, and the first terminal of the second switch is coupled To the first terminal of the first switch and connected to the analog signal; the first capacitor 'has the first terminal and the second terminal' Diangu 1226506 06716twf 1 .doc / 006 The first terminal of the amendment date 93.1 · 15 is coupled to The second terminal of the first switch and the second terminal of the capacitor are coupled to ground (or a fixed level power supply); the third switch has a first terminal and a second terminal, and the first terminal of the third switch is coupled to The first terminal of the first capacitor and the second terminal of the third switch are coupled to the output buffer; the second capacitor has a first terminal and a second terminal, and the first terminal of the capacitor is coupled to the second terminal of the second switch The second terminal of the capacitor is coupled to ground (or a fixed level power supply); and the fourth switch has a first terminal and a second terminal, and the first terminal of the fourth switch is coupled to the first terminal of the second capacitor The second terminal of the fourth switch is coupled to the output buffer, and the pulse signal enables the first switch and the fourth switch. In turn with the second switch and the third switch _ open and closed. In the embodiment of the present invention, the output buffer is an operational amplifier, which has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to the second terminal of the fourth switch, and the inverting input terminal is coupled. To the output. In another embodiment of the present invention, at the time of sampling and holding at the first time point, the fourth switch of each channel is opened and closed, the second switch and the third switch are opened, and the first switch of each channel is based on a shift register. The output pulses are sequentially closed and then open, so that the first capacitor of each channel sequentially stores the potential data of the analog signal; when sampling and holding the phase at the second time point, the first switch and the fourth # switch of each channel Open circuit, third open circuit and closed circuit. The second switch of each channel is closed in sequence according to the output pulse of the shift register and then opened, so that the second capacitor of each channel stores the potential data of the analog signal in sequence; meanwhile, the first capacitor The potential data of the previously stored analog signal is output to the output buffer. Based on the above, it can be seen that in the data driver architecture of the thin film transistor liquid crystal display, each displayed Channel includes only a set of shift registers, a set of sample and hold circuits, and a set of output buffers. The entire chip only needs to be 1226506 06716twfl.doc / 006 Revision date 93.1.15 A few one-to-array latch circuits, level shifters, and digital analog converters are required. 'It can be seen that the present invention can reduce the circuit and greatly reduce the chip area', thus reducing the cost. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1A FIG. 1B illustrates a block diagram of an embodiment of a data driver architecture of a general thin film transistor liquid crystal display; FIG. 1B illustrates a circuit block diagram of a data driver architecture of a general thin film transistor liquid crystal display. Figure 1C shows a circuit diagram of a 128-1 multiplexer that implements a general thin-film transistor liquid crystal display. Table 2 does not show a block diagram of a preferred embodiment of the data driver architecture of a thin film transistor liquid crystal display according to the present invention; Figure 3A does not show a sample of the data driver architecture of a thin film transistor liquid crystal display according to the present invention. A circuit diagram of a preferred embodiment of the holding and holding circuit; FIG. 3B shows an equivalent circuit diagram of the sampling and holding circuit at the first time point of the shell driver structure of the thin film transistor liquid crystal display according to the present invention; and FIG. 3C Shown is an equivalent circuit diagram of the sampling and holding circuit at the second time point of the data driver architecture of the thin film transistor liquid crystal display according to the present invention. Description of the drawing: 1226506 06716twf 1 .doc / 006 Amendment date 93.1 · 15 10, 36: Shift register 14, 30: Latch circuit 16, 32: Level shifter 18, 34: Digital analog conversion Device 20, 60: Output buffer 22: Clock 2 4, 4 0: ^ Serial data 52, 54, 56, 58: Switch 53, 55: Capacitance. Please refer to Figure 2 for examples. It is a block diagram of a preferred embodiment of a data driver architecture of a thin film transistor liquid crystal display according to the present invention. First, the digital display data 40 is input into the latch circuit 30, and the latch circuit 30 locks the data individually according to the timing clock, and then outputs the latch serial data. The level shifter 32 is coupled to the latch circuit 30 and can raise the latch serial data to a high voltage through the level shifter 32. For example, the level shifter 32 may be composed of a transistor and use the characteristics of the transistor to boost the voltage of the input latch serial data. The level shifter 32 is then coupled to the digital analog converter 34, and the digital analog converter 34 is called to convert the high-voltage serial data into an analog signal. Since the sample and hold circuit 50 is coupled to the digital analog converter 34, it can sample and hold the analog signal, and because the shift register 36 is coupled to the sample and hold circuit 50, the shift register 36 Generate a pulse signal according to the timing clock to control the sample and hold circuit 50 to sample the analog signal. Finally, the analog signal after the sample and hold will be output through the output buffer 60, which is used to buffer the sample and hold circuit 50. Output. 1226506 06716twfl.doc / 006 Modification date 93.1.15 The sample and hold circuit 50 is composed of two capacitors 53, 55 and four switches 52, 54, 56, 58. The four switches 52, 54, 56, and 58 can control these two capacitors 53, 55 to alternately perform the sampling and holding operation, and the output buffer 70 is composed of an operational amplifier. The operation of the sample-and-hold circuit 50 and the output buffer 70 is as follows. Please refer to FIG. 3A, which shows a circuit diagram of a preferred embodiment of the sample and hold circuit. The first switch 52 has a first terminal and a second terminal, the second switch 56 has a first terminal and a second terminal, and the first terminal of the first switch 52 is coupled to the first terminal of the second switch 56 and the first The first terminal of the switch 52 is coupled to the input terminal (Vin), and because the first terminal of the first switch 52 is coupled to the first terminal of the second switch 56, the second switch 56 and the input terminal (Vin) are Connected, the first capacitor 53 has a first terminal and a second terminal, the third switch 54 has a first terminal and a second terminal, and the first terminal of the first capacitor 53 is coupled to the second terminal of the first switch 52, The second terminal of the first switch 52 is coupled to the first terminal of the third switch 54, and because the first terminal of the first capacitor 53 is coupled to the second terminal of the first switch 52, One end is in communication with the first end of the first capacitor 53, and the second end of the first capacitor 53 is connected to a fixed level power source or directly grounded; the second capacitor 55 has a first end and a second end, and the fourth switch 58 has The first terminal and the second terminal, and the first terminal of the second capacitor 55 is coupled to the second terminal of the second switch 56, and the second terminal of the second switch 56 is coupled to the first terminal of the fourth switch 58. Because the first terminal of the second capacitor 55 is coupled to the second terminal of the second switch 56, the first terminal of the fourth switch 58 is in communication with the first terminal of the second capacitor, and the second terminal of the second capacitor 55 is Terminated to a fixed level power supply or directly grounded, the operational amplifier 70 has a non-inverting input terminal (V +), an inverting input terminal (V-), and an output terminal (Vout). The non-inverting input terminal (V +) and the first Sankai 1226506 06716twfl.doc / 006 Correction date 93.1.15 The second terminal of the switch 54 is coupled to 'the second terminal of the third switch 54 is coupled to the second terminal of the fourth switch 58' and the non-inverting input terminal ( V +) is coupled to the second terminal of the third switch 54, so the second terminal of the fourth switch 58 is in communication with the non-inverting input terminal (V +), and the inverting input terminal (V-) is connected to the output terminal (Vout ) Coupled. Please refer to FIG. 3B, which shows the equivalent circuit of the sample and hold circuit diagram at the first time point. When the sample and hold phase at the first time point, the first switch 52 and the fourth switch 58 are closed, and the second The switch 56 is open to the third switch 54. The circuit diagram is as follows: the first switch 52 has a first terminal and a second terminal, and the first terminal is coupled to the input terminal (Vin); the first capacitor 53_ has a first terminal and a second terminal; and the first switch 52 The second terminal of is coupled to the first terminal of the first capacitor 53, and the second terminal of the first capacitor 53 is coupled to ground. The second capacitor 55 has a first terminal and a second terminal, and the first terminal of the second capacitor 55 is coupled to ground. The fourth switch 58 has a first terminal and a second terminal. The first terminal of the fourth switch 58 is coupled to the first terminal. The second terminal of the two capacitors 55. The operational amplifier 70 has a non-inverting input terminal (v +), an inverting input terminal (V-), and an output terminal (Vout). The non-inverting input terminal (V +) of the operational amplifier 70 is called It is connected to the second terminal of the fourth switch 58, and the inverting input terminal (V-) of the operational amplifier 70 is coupled to the output terminal (Vout). It can be seen that when sampling and holding the phase at the first time point, the first switch 52 and the fourth switch 58 are closed, and the second switch 56 and the third switch 54 are open. The first capacitor 53 stores the analog signal. The second capacitor 55 outputs the potential data of the analog signal. It should be particularly noted that the first switch 52 is not always closed when sampling and holding the phase at the first time point; instead, the first switch 52 of each of the three channels is closed in sequence and then opened in accordance with the order of the channels. The first capacitors 53 of the three channels sequentially store the potential data of the analog signals. 1226506 06716twfl.doc / 006 Revision date 93.1.15 Please refer to Figure 3C, which shows the equivalent circuit of the sample and hold circuit diagram at the second time point. When the sample and hold phase at the second time point, the first The switch 52 is open to the fourth switch 58, and the second switch 56 is closed to the second switch 54. The circuit diagram is as follows: The first switch 56 has a first terminal and a second terminal, the first terminal is coupled to the input terminal (Vin), the second capacitor 55 has a first terminal and a second terminal, and the second switch The scale 56 is connected to the first terminal of the first capacitor 55, and the second terminal of the second capacitor 55 is coupled to ground. The first capacitor 53 has a first terminal and a second terminal, the first terminal of the first capacitor 53 is coupled to ground, the third switch 53 has a first terminal and a second terminal, and the first terminal of the third switch 53 is coupled to The second terminal of the first capacitor 53, the operational amplifier 70 has a non-inverting input terminal (V +), an inverting input terminal (v_), and an output terminal (Vout), and the non-inverting input terminal (V +) of the operational amplifier 70. The second terminal of the third switch is coupled, and the inverting input terminal (V-) of the operational amplifier 70 is coupled to the output terminal (Vout). It can be seen that when the sample and hold phase at the second time point is that the first switch 52 and the fourth switch 58 are open, and the second switch 56 and the third switch 54 are closed, the potential of the analog signal is first capacitor 53 Data output. The second capacitor 55 stores the potential data of the analog signal. It is important to note that the second switch 56 is not always closed when sampling and holding the phase at the second time point; instead, the second switch 56 for each three channels is closed in sequence and then opened in accordance with the order of the channels. The second capacitor 55 of each three channels sequentially stores the potential data of the analog signals. Based on the above, it can be seen that the sample and hold circuit includes two capacitors and four switches, and the four switches are used to control the two capacitors to take turns to perform the sample and hold operation. If a 300 channel 6 bit data driver is also used as an example, this issue 12 1226506 06716twfl.doc / 006 revision date 93.1.15 shows that the number of unit components calculated as follows is required. The latch circuit requires 3 * 6 bit latches; the level shifter needs 3 * 6 bit level shifting components; the digital analog converter requires a resistor string, 3 sets of multiplexers, and the multiplexer requires 128+ 64+ 32+ 16+ 8 + 4+ 2 = 254 MOS transistors and 128 windings, only 3 output windings of the digital analog converter will span the entire chip; the shift register requires 100 temporary Storage elements are stringed; 300 sample and hold circuits are required; 300 output buffers are required. From this, it can be seen that the more traditional thin film transistor liquid crystal display data driver of the present invention includes only a shift Memory, sample and hold circuit, and output buffer. The entire chip only includes one-to-array latch circuits, level shifters, and digital analog converters. Although there are additional sample and hold circuits, the circuit area is the same as above. Compared with the area saved, it can be said to be insignificant. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and decorations without departing from the spirit, spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. 13