JP2002175026A - Active matrix type display device and portable terminal using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type display device enabling size reduction of the set and cost reduction, and to provide a portable terminal, using the same as a display part. SOLUTION: In the active matrix type display device provided with a display area part 12 where pixels are arranged in a matrix form, H-drivers 13U, 13D, a V-driver 14, a reference voltage generating circuit 15, a counter electrode voltage generating circuit 16, a power supply voltage conversion circuit 17, and a timing generating circuit 8 are constructed on the same glass substrate 11 as the display area part 12 using the same process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix type display device and a portable terminal using the same as a display unit.

[0002]

2. Description of the Related Art In recent years, portable telephones and PDAs (Personal Digital
gital Assistants) and other mobile terminals are remarkable. One of the factors behind the rapid spread of these mobile devices is that
There is a liquid crystal display device mounted as the output display unit. The reason is that the liquid crystal display device has a characteristic that does not require power for driving in principle, and is a display device with low power consumption.

In an active matrix type display device in which pixels are arranged in a matrix, such as a liquid crystal display device, and each of these pixels is driven, a vertical drive circuit for selecting each pixel in a row unit and a vertical drive circuit And a horizontal drive circuit for writing information to each pixel in a row selected by the circuit. These drive circuits tend to be formed integrally with the display area on the same substrate.

In an active matrix type display device, in addition to a vertical drive circuit and a horizontal drive circuit, a timing generation circuit for generating various timing signals for controlling the timing of these drive circuits and a different circuit unit are provided. Since a DC voltage having a voltage value is often used as a power supply voltage, a power supply voltage conversion circuit or the like that converts a single DC power supply voltage into a plurality of types of DC voltages having different voltage values and provides the DC voltage to each circuit unit is also used. Conventionally, these circuits have been formed on a separate chip by a single crystal silicon IC or on a printed circuit board by discrete components separately from the substrate including the display area.

[0005]

As described above, in an active matrix display device, a timing generation circuit, a power supply voltage conversion circuit, and the like are provided on a separate chip or by a single-crystal silicon IC separately from a substrate including a display area. Forming on a printed circuit board with discrete components increases the number of components that make up the set and requires separate processes to create each set, which hinders the miniaturization and cost reduction of the set. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an active matrix type display device capable of reducing the size and cost of a set and using the same as a display unit. To provide a mobile terminal.

[0007]

In order to achieve the above object, according to the present invention, there is provided a display area in which pixels having electro-optical elements are arranged in a matrix, and each pixel in the display area is divided into rows. And a reference voltage generation circuit for generating a plurality of reference voltages, and a reference voltage selection type DA conversion circuit for selecting a reference voltage corresponding to digital image data from the plurality of reference voltages. A horizontal drive circuit for supplying the reference voltage selected by the DA conversion circuit as an image signal to each pixel in a row selected by the vertical drive circuit, and a timing for generating various timing signals and supplying the timing signals to each circuit unit An active matrix table including a generating circuit and a power supply voltage conversion circuit for converting a single DC voltage into a plurality of types of DC voltages having different voltage values and applying the converted voltage to each circuit unit In the device, the vertical drive circuit, a reference voltage generating circuit, a horizontal drive circuit, a timing generation circuit and the power supply voltage converting circuit, adopts a configuration that was created using the same process on the same substrate together with the display area unit. This active matrix display device is used as a display unit of a portable terminal.

In the active matrix type display device having the above configuration or a portable terminal using the same, all peripheral circuits necessary for display driving in the display area are formed together with the display area on the same substrate using the same process. Thus, the number of parts constituting the set can be reduced. Therefore, the cost of the set can be reduced, and the set can be made thinner and more compact.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention. Here, for example, a case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell as an electro-optical element of each pixel will be described.

In FIG. 1, on a transparent insulating substrate, for example, a glass substrate 11, a display area 12 in which a large number of pixels including liquid crystal cells are arranged in a matrix is formed. The glass substrate 11 has a first substrate on which a large number of pixel circuits including active elements (for example, transistors) are arranged in a matrix (in a matrix), and is opposed to the first substrate with a predetermined gap. And a second substrate to be formed. Then, a liquid crystal is sealed between the first and second substrates.

FIG. 2 shows an example of a specific configuration of the display area section 12. Here, for simplification of the drawing, a case of a pixel array of 3 rows (n-1 row to n + 1 row) and 4 columns (m-2 column to m + 1 column) is taken as an example. In FIG. 2, vertical scanning lines...
−1, 21n, 21n + 1,..., And data lines.
, 2m-2, 22m-1, 22m, 22m + 1,... Are wired in a matrix, and the intersection of the unit pixels 2
3 are arranged.

The unit pixel 23 has a configuration including a thin film transistor TFT as a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. Here, the liquid crystal cell LC
Means a capacitance generated between a pixel electrode formed by the thin film transistor TFT and a counter electrode formed to face the pixel electrode. In the thin film transistor TFT, the gate electrode has a vertical scanning line..., 21n−1, 21n, 21n + 1,
, And the source electrode is connected to the data line.
2, 22m-1, 22m, 22m + 1,...

The liquid crystal cell LC has a pixel electrode connected to the drain electrode of the thin film transistor TFT, and a counter electrode connected to the common line 24. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 24. The common line 24 is supplied with a common electrode voltage (common voltage) Vcom, and this common voltage Vcom is applied to the common electrode of the liquid crystal cell LC in common for each pixel.

On the glass substrate 11, a pair of upper and lower H drivers (horizontal drive circuits) 13U and 13D and a V driver (vertical drive circuit) are formed integrally with the display area section 12. Each end of the vertical scanning lines..., 21n-1, 21, n, 21n + 1,.
It is connected to each output terminal of the corresponding row of the V driver 14. The V driver 14 is formed of, for example, a shift register, and sequentially generates vertical selection pulses in synchronization with a vertical transfer clock VCK (not shown) and supplies the vertical selection pulses to vertical scanning lines..., 21n-1, 21, n, 21n + 1,. Performs vertical scanning.

On the other hand, in the display area section 12, for example, odd-numbered data lines..., 22m-1, 22m + 1,
Are connected to the respective output terminals of the corresponding columns of the H driver 13U, even-numbered data lines..., 22m-2, 22m,.
Are connected to the respective output terminals of the corresponding column of the H driver 13D. FIG. 3 shows an example of a specific configuration of the H drivers 13U and 13D.

As shown in FIG. 3, the H driver 13U includes:
The configuration includes a shift register 25U, a sampling latch circuit (data signal input circuit) 26U, a line sequential latch circuit 27U, and a DA conversion circuit 28U. The shift register 25U performs horizontal scanning by sequentially outputting a shift pulse from each transfer stage in synchronization with a horizontal transfer clock HCK (not shown). The sampling latch circuit 26U responds to a shift pulse given from the shift register 25U, and samples and latches input digital image data of predetermined bits in a dot-sequential manner.

The line-sequentializing latch circuit 27U re-latches the digital image data latched in the dot-sequential manner by the sampling latch circuit 26U line by line, thereby line-sequentially converting the digital image data for one line. Output to The DA conversion circuit 28U has, for example, a circuit configuration of a reference voltage selection type, and has a line-sequential latch circuit 27.
The digital image data for one line output from U is converted into an analog image signal to convert the digital image data into an analog image signal.
, 22m-2, 22m-1, 22m,
22m + 1, ....

FIG. 4 shows a reference voltage selection type DA conversion circuit 28.
4 shows a configuration example of a unit circuit of U. Here, the input digital image data is, for example, 3 bits (b2, b1, b).
0) is taken as an example, and eight (= 2 ³ ) reference voltages V0 to V7 are prepared for the 3-bit data. This unit circuit is the pixel area unit 1
2 data lines ..., 22m-2, 22m-1, 22
m, 22m + 1,... are arranged one by one.

The lower H driver 13D also has a shift register 25 just like the upper H driver 13U.
D, a sampling latch circuit 26D, a line sequential latch circuit 27D, and a reference voltage selection type DA conversion circuit 28D. In the active matrix type liquid crystal display device according to this embodiment, the H drivers 13U and 13D are arranged above and below the display area 12, but the present invention is not limited to this. It is also possible to adopt a configuration of distributing the information.

On the glass substrate 11, a reference voltage generation circuit 15, a common electrode voltage generation circuit 16, a power supply voltage conversion circuit 17, and a timing generation circuit 18 are also displayed in the same manner as the H drivers 13U, 13D and V driver 14. It is formed integrally with the area 12. Here, for example, in the case of a liquid crystal display device adopting a configuration in which H drivers 13U and 13D are arranged above and below the display area section 12, a frame area of a side where the H drivers 13U and 13D are not mounted (the display area section 12). Reference voltage generation circuit 1 in the peripheral area)
5, counter electrode voltage generation circuit 16, power supply voltage conversion circuit 17
And a timing generation circuit 18.

The reason is that the H drivers 13U, 13D
As described above, since the number of components is larger than that of the V driver 14 and the circuit area is often very large as described above, the H driver 13U, 13D is mounted in the frame area on the side where the H driver 13U, 13D is not mounted. The reference voltage generation circuit 15, the counter electrode voltage generation circuit 16, the power supply voltage conversion circuit 17, and the timing generation circuit 18 are connected to the display area section 12 without reducing the effective screen ratio (the area ratio of the effective area section 12 to the glass substrate 11). This is because it can be mounted on the same glass substrate 11 as.

In the active matrix type liquid crystal display device according to the present embodiment, the V driver 14 is mounted on one side of the frame area on the side where the H drivers 13U and 13D are not mounted. A configuration is adopted in which a reference voltage generation circuit 15, a common electrode voltage generation circuit 16, a power supply voltage conversion circuit 17, and a timing generation circuit 18 are mounted in a frame area on the side.

FIG. 5 is a circuit diagram showing an example of a specific configuration of the reference voltage generating circuit 15. The reference voltage generation circuit 15 according to the present example includes two switch circuits 31 and 32 that switch the positive power supply voltage VCC and the negative power supply voltage VSS in a fixed cycle in opposite phases to each other, and these switch circuits 31 and 3
7 divided resistors R1 connected in series between respective output terminals
To R7. Here, the positive power supply voltage VCC and the negative power supply voltage VSS are set to a fixed cycle,
Switching in the opposite phase in the H cycle is performed by driving the liquid crystal by alternating current (1H in this example) in order to prevent deterioration of the liquid crystal.
This is for performing inversion driving.

In the reference voltage generation circuit 15 having the above configuration, the output voltage VA of the switch circuit 31 is used as it is as the reference voltage V7 for a white signal in normally white, and the output voltage VB of the switch circuit 32 is used as it is in normally white. Used as a reference voltage V0 for a black signal. Also,
By dividing the difference voltage between the reference voltage V0 for the black signal and the reference voltage V7 for the white signal by the division resistors R0 to R6, the reference voltages V1 to V6 for the halftone are created. In the case of normally black, the output voltage VA is used as the reference voltage V7 for the black signal, and the output voltage VB is used as the reference voltage V0 for the white signal.

FIG. 6 is a block diagram showing an example of a specific configuration of the common electrode voltage generation circuit 16. As shown in FIG. The counter electrode voltage generation circuit 16 according to the present example includes a switch circuit 33 that switches and outputs a positive power supply voltage VCC and a negative power supply voltage VSS at a constant cycle, and a DC level of the output voltage VA of the switch circuit 33. Is converted to the common electrode voltage Vcom.
And a DC level conversion circuit 34 for outputting

The switch circuit 33 has a positive power supply voltage VCC.
, And a switch SW2 that receives the negative power supply voltage VSS. The switches SW1 and SW2 are switched by control pulses φ1 and φ2 having opposite phases to each other, so that the positive power supply voltage V
The configuration is such that CC and the negative power supply voltage VSS are alternately output at a constant cycle. Thereby, the switch circuit 33
Output a voltage VA having an amplitude of VSS to VCC.

The DC level conversion circuit 34 converts the level of the output voltage VA having an amplitude of VSS to VCC of the switch circuit 33 into a DC voltage having an amplitude of VSS-ΔV to VCC-ΔV, for example, and outputs it as a common electrode voltage Vcom. As the DC level conversion circuit 34, various circuit configurations can be considered. As shown in FIG. 7, a circuit configuration including a capacitor 341 and a DC voltage generation circuit 342 is generally used as a simple circuit configuration.

Next, the power supply voltage conversion circuit 17 will be described. As the power supply voltage conversion circuit 17, a charge pump type circuit has been increasingly used in recent years as power consumption and size of portable terminals have been reduced. FIG. 8 is a circuit diagram showing an example of the configuration of a charge pump type power supply voltage conversion circuit (DC-DC converter), where (A) shows a negative voltage generation type and (B) shows a boost type.

In FIG. 8, a single DC power supply voltage VCC
Between the power supply and ground (GND).
OS transistor Qp11 and NchMOS transistor Q
n11 are connected in series, and the gates are connected in common to form a CMOS inverter 41. This C
A switching pulse having a predetermined frequency is applied from a pulse generation source 42 to the gate common connection point of the MOS inverter 41.

One end of a capacitor C11 is connected to a common drain connection point (node B) of the CMOS inverter 41. The other end of the capacitor C11 is connected to a switch element, for example, a drain of an NchMOS transistor Qn12 and a source of a PMOS transistor Qp12. A load capacitor C12 is connected between the source of the NchMOS transistor Qn12 and the ground.

One end of a capacitor C13 is connected to a common connection point of the gates of the CMOS inverter 41. The other end of the capacitor C13 is connected to the anode of the diode D11. The cathode of the diode D11 is grounded to form a first clamp circuit 43. The other end of the capacitor C13 further includes an NchMOS transistor Qn12 and a PchMOS transistor Qp
Twelve gates are connected to each other. PchMOS
The drain of the transistor Qp12 is grounded.

A PchMOS transistor Qp13 is connected between the other end of the capacitor C13 and the ground. A clamp pulse generated by a pulse generation source 44 is level-shifted by a level shift circuit 45 and applied to the gate of the PchMOS transistor Qp13. The PchMOS transistor Qp13, the pulse generation source 44, and the level shift circuit 45 constitute a second clamp circuit 46 for clamping the switching pulse voltage of the switching transistor (NchMOS transistor Qn12 and PchMOS transistor Qp12).

In the second clamp circuit 46, the level shift circuit 45 converts the power supply voltage VCC input to the present power supply voltage conversion circuit into a positive circuit power supply and a load capacitor C1.
The output voltage Vout of this circuit derived from both ends of the second circuit 2 is used as a negative circuit power supply, and the clamp pulse of the first amplitude (VCC-0 [V]) generated by the pulse generator 44 is supplied to the second circuit.
Of the amplitude (VCC-Vout [V]), and gives it to the gate of the PchMOS transistor Qp13. Thereby, the switching operation of the PchMOS transistor Qp13 is performed more reliably.

Next, the circuit operation of the negative voltage generation type charge pump type power supply voltage conversion circuit having the above configuration will be described with reference to the timing chart of FIG. Note that the timing chart of FIG.
Signal waveforms A to G at nodes A to G in the circuit of FIG.
Is shown.

When the power is turned on (start-up), the output potential of the capacitor C13 based on the switching pulse generated by the pulse generation source 42, that is, the potential of the node D is first set to the negative circuit power supply potential by the diode D11. The signal is clamped at the “H” level to a potential level shifted from a certain ground (GND) level by the threshold voltage Vth of the diode D11.

When the switching pulse is at the "L" level (0 V), the PchMOS transistor Qp1
1 and Qp12 are turned on, so that the capacitor C11
Is charged. At this time, the NchMOS transistor Qn
Since 11 is in the off state, the potential of the node B becomes the VCC level. Next, when the switching pulse becomes “H” level (VCC), the NchMOS transistor Qn1
1 and Qn12 are turned on, and the potential of the node B becomes the ground level (0 V).
It becomes CC level. The potential of this node C remains unchanged for Nch
Output voltage Vout through MOS transistor Qn12
(= −VCC).

Next, when the output voltage Vout rises to some extent (at the end of the start-up process), the level shift circuit 45 for the clamp pulse starts operating. When the level shift circuit 45 starts operating, the clamp pulse having the amplitude VCC-0 [V] generated by the pulse generation source 44 is supplied to the level shift circuit 45 by the amplitude VCC-Vout.
The level is shifted to the clamp pulse of [V], and then applied to the gate of the PchMOS transistor Qp13.

At this time, since the "L" level of the clamping pulse is the output voltage Vout, ie, -VCC, the Pch
MOS transistor Qp13 is reliably turned on.
As a result, the potential of the node D is clamped to the ground level (negative circuit power supply potential) instead of the potential level shifted from the ground level by the threshold voltage Vth of the diode D11. Thereby, in the subsequent pumping operation, in particular, the PchMOS transistor Qp12
, A sufficient driving voltage can be obtained.

As described above, in the power supply voltage conversion circuit using the charge pump, the switching elements (Nch MOS transistors Qn12 and Pn12)
The voltage of the control pulse (switching pulse) for the chMOS transistor Qp12) is first clamped by the diode D11 of the first clamp circuit 43 when the circuit is activated, and the second clamp circuit 4 is activated after the activation process is completed.
6, the clamping is performed in two stages, such as the PchMOS transistor Qp1.
2, a sufficient driving voltage can be obtained.

As a result, the Pch MOS transistor Qp
12, a sufficient switching current can be obtained, so that a stable DC-DC conversion operation can be performed and the conversion efficiency can be improved. In particular, since a sufficient switching current can be obtained without increasing the transistor size of the PchMOS transistor Qp12, a power supply voltage conversion circuit having a large current capacity and a small circuit scale can be realized.

The booster DD converter shown in FIG. 8B has the same basic circuit configuration and circuit operation.

That is, in FIG. 8B, the switching transistor and the clamping transistor (MO)
The S transistors Qp14, Qn14, Qn13) are the MOS transistors Qn12, Qp1 of the circuit of FIG.
2, Qp13 and the diode D
11 is connected between the other end of the capacitor C11 and the power supply (VCC), and the level shift circuit 45 uses the output voltage Vout of this circuit as a positive circuit power supply and the ground level as a negative circuit power supply. Figure 8
The only difference from the circuit of FIG.

In terms of circuit operation, basically, FIG.
This is exactly the same as the circuit of FIG. The difference is that the switching pulse voltage (control pulse voltage) is first diode-clamped at startup, clamped to the VCC level (positive circuit power supply potential) at the end of the startup process, and output voltage Vout is twice the power supply voltage VCC. Voltage value 2 × V
Only the point from which the CC is derived. FIG. 9 (B) shows FIG.
Signal waveforms A to G at nodes A to G in the circuit of FIG.
3 shows a timing chart.

Here, the power supply voltage conversion circuit 17 has been described by taking a charge pump type as an example, but this is merely an example and the present invention is not limited to this.

Next, the timing generation circuit 18 will be described. As schematically shown in FIG. 10, the timing generation circuit 18 includes a horizontal synchronization signal HD,
The vertical synchronization signal VD and the master clock MCK are input, and the horizontal start pulse HST applied to the shift register 25U of the H driver 13U is first set based on these inputs.
And a horizontal transfer pulse HCK, and a vertical start pulse VS given to the shift register 141 of the V driver 14.
T and a vertical transfer pulse VCK are generated.

Here, the horizontal start pulse HST is a pulse signal generated after a lapse of a predetermined time after the generation of the flat synchronization signal HD, and the horizontal transfer pulse HCK is the master clock M
This is a pulse signal obtained by dividing CK, for example. The vertical start pulse VST is a pulse signal generated after a predetermined time has elapsed after the generation of the vertical synchronization signal VD, and the vertical transfer pulse VCK is a pulse signal obtained by, for example, dividing the frequency of the horizontal transfer pulse HCK.

Therefore, in the timing generation circuit 18, the horizontal start pulse HST, the horizontal transfer pulse HCK, and the vertical start pulse VCK are set on the basis of the horizontal synchronizing signal HD, the vertical synchronizing signal VD and the master clock MCK.
A circuit for generating the ST and the vertical transfer pulse VCK can be realized by a simple counter circuit having several stages.

The timing generation circuit 18 further outputs timing data obtained from an appropriate transfer stage of the shift register 25U of the H driver 13U and timing data (timing information) obtained from an appropriate transfer stage of the shift register 141 of the V driver 14. Also, a timing pulse used by the H driver 13U and a timing pulse used by the V driver 14 are generated based on these timing data.

The timing pulse used in the H driver 13U is, for example, a latch control pulse used in the line sequential latch circuit 27U (27D) shown in FIG. However, it is not limited to this.
On the other hand, the timing pulse used in the V driver 14 is, for example, a display period control pulse for specifying the display period in the partial display mode in which display is performed only during a certain period in the vertical direction of the display area unit 12. . However, it is not limited to this.

FIG. 11 is a block diagram showing an example of a specific configuration of the timing generation circuit 18. As shown in FIG. Here, the case where the timing generation circuit 18 generates a latch control pulse used in the line-sequentialization latch circuit 27U based on the timing data given from the shift register 25U of the H driver 13U will be described as an example.

In FIG. 11, first, an H driver 13U
Shift register 25U has M stages of D-type flip-flops (hereinafter, referred to as the number of horizontal pixels in the display area unit 12).
DFF) 51-1 to 51-M. When the horizontal start pulse HST is given, the shift register 25U having such a configuration transfers the horizontal transfer pulse HC.
The shift operation is performed in synchronization with K. As a result, the DFF 51
−1 to 51-M, the horizontal transfer pulse H
Pulses (timing information) are sequentially output in synchronization with CK.

Each of the Q output pulses of the DFFs 51-1 to 51-M is sequentially supplied to the sampling latch circuit 26U as a sampling pulse. Also, DFF51-
Among the Q output pulses 1 to 51-M, the Q output pulse of an appropriate transfer stage, here, as an example, the first stage DFF5
1-1, the Q output pulse A and the M-1 stage DFF 51-
The M-1 Q output pulse B is supplied to the timing generation circuit 18.

In the timing generation circuit 18, a latch control pulse generation circuit 52 for generating a latch control pulse has, for example, a configuration including a DFF 53 and a buffer 54. The DFF 53 is a shift register 25
The clock (CK) is input to the Q output pulse A of the first stage DFF 51-1 supplied from U, and the M-1 stage DFF 51-1
The -M-1 Q output pulse B is used as a clear (CLR) input, and its own inverted Q output is used as a data (D) input.

As a result, the pulse which becomes "H" level (high level) in the period from the rising timing of the Q output pulse A of the DFF 51-1 to the rising timing of the Q output pulse B of the DFF 51-M-1 is changed to the DFF
A latch control pulse C is obtained from the Q output terminal 53 via the buffer 54.

As described above, the timing generation circuit 18
, The H drivers 13U and 13D and the V driver 14
Driver 13 for generating timing pulses used in
U and 13D shift registers 25U and 25D and V driver 14 shift register 141 are also used, and timing pulses are generated based on the timing data obtained from these shift registers, so that a dedicated circuit such as a counter circuit is not required. And the circuit configuration can be simplified,
This makes it possible to reduce the size, cost, and power consumption of the set.

Here, the timing generation circuit 18
Are the horizontal start pulse HST and the horizontal transfer pulse HC
K, vertical start pulse VST and vertical transfer pulse V
The case where CK is generated has been described as an example, but this is merely an example and the present invention is not limited to these timing pulses.

Other timing pulses include, for example, the switching pulse and the clamping pulse used in the charge pump type power supply voltage conversion circuit 17 described above.
As described above, the switching pulse and the clamping pulse are also generated by the timing generation circuit 18, so that the charge pump type power supply voltage conversion circuit 17 shown in FIG. , 43 can be omitted, so that the circuit configuration of the power supply voltage conversion circuit 17 can be simplified by that much, so that the scale of the circuit integrally formed on the glass substrate 11 can be reduced.

The reference voltage generation circuit 15, the common electrode voltage generation circuit 16, and the power supply voltage conversion circuit 1 according to each of the above-described configuration examples.
When the circuit 7 and the timing generation circuit 18 are integrally formed on the same glass substrate 11 together with the display area section 12, all the circuit elements constituting those circuits, or at least the active elements (or active / passive elements) are replaced with a glass substrate. 11 is created. As a result, since no active element (or active / passive element) exists outside the glass substrate 11, the configuration of the peripheral portion of the substrate can be simplified, and the size and cost of the device can be reduced. .

The circuits integrally formed on the same glass substrate 11 together with the display area section 12 include, in addition to the reference voltage generation circuit 15, the common electrode voltage generation circuit 16, the power supply voltage conversion circuit 17, and the timing generation circuit 18, For example, as shown in FIG. 12, a CPU interface circuit 61, an image memory circuit 62, an optical sensor circuit 63, a light source driving circuit 64, and the like are included.

Here, the CPU interface circuit 61
Is a circuit for inputting and outputting data to and from an external CPU. The image memory circuit 62 is a memory for storing image data input from the outside through the CPU interface circuit 61, for example, still image data. The optical sensor circuit 63 is a sensor that detects the intensity of external light, such as the brightness of the environment in which the present liquid crystal display device is used, and provides the detection information to the light source drive circuit 64. The light source drive circuit 64 is a circuit that drives a backlight or a front light that illuminates the display area unit 12, and adjusts the brightness of the light sources based on intensity information of external light provided from the optical sensor circuit 63.

The circuits 61 to 64 are connected to the display area 1
In the case where the circuit elements are integrally formed on the same glass substrate 11 together with the circuit board 2, all the circuit elements constituting those circuits, or at least the active elements (or active / passive elements) are formed on the glass substrate 11. In addition, the size and cost of the device can be reduced.

In the above embodiment, the case where the present invention is applied to an active matrix type liquid crystal display device has been described as an example. However, the present invention is not limited to this, and an electroluminescent (EL) element may be used for each pixel. The present invention can be similarly applied to other active matrix display devices such as an EL display device used as an element.

The active matrix type display device represented by the active matrix type liquid crystal display device according to the above embodiment is used not only as a display for OA equipment such as a personal computer and a word processor, but also for a display such as a television receiver. It is suitable for use as a display unit of a portable terminal such as a cellular phone or a PDA whose main body has been reduced in size and size.

FIG. 13 shows a portable terminal to which the present invention is applied.
FIG. 1 is an external view schematically illustrating a configuration of a mobile phone, for example.

The mobile phone according to this embodiment has a configuration in which a speaker 72, a display 73, an operation unit 74, and a microphone 75 are arranged in this order from the upper side on the front side of an apparatus housing 71. In the mobile phone having such a configuration, the display unit 7
For example, a liquid crystal display device 3 is used as the liquid crystal display device 3, and the active matrix liquid crystal display device according to the above-described embodiment is used as the liquid crystal display device.

As described above, in a portable terminal such as a portable telephone, by using the active matrix type liquid crystal display device according to the above-described embodiment as the display section 73,
The liquid crystal display device can be realized at low cost,
Since the terminal is small, the cost and size of the terminal body can be reduced.

[0067]

As described above, according to the present invention,
In an active matrix type display device or a portable terminal using the same as a display unit, in addition to a drive circuit including a vertical drive circuit and a horizontal drive circuit, peripheral circuits are formed together with a display area unit on the same substrate using the same process. By doing so, the number of parts constituting the set can be reduced, so that the cost of the set can be reduced, and the set can be made thinner and more compact.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a display area of a liquid crystal display device.

FIG. 3 is a block diagram illustrating an example of a specific configuration of an H driver.

FIG. 4 is a circuit diagram showing an example of a specific configuration of a reference voltage selection type DA converter.

FIG. 5 is a circuit diagram showing an example of a specific configuration of a reference voltage generation circuit.

FIG. 6 is a block diagram illustrating an example of a specific configuration of a common electrode voltage generation circuit.

FIG. 7 is a block diagram illustrating an example of a configuration of a DC level conversion circuit.

FIG. 8 is a circuit diagram showing an example of a configuration of a charge pump type power supply voltage conversion circuit.
(B) shows the boost type.

FIGS. 9A and 9B are timing charts for explaining the circuit operation of the charge pump type power supply voltage conversion circuit, wherein FIG. 9A shows a negative voltage generation type and FIG. 9B shows a step-up type.

FIG. 10 is a schematic diagram for explaining a configuration of a timing generation circuit.

FIG. 11 is a block diagram illustrating an example of a specific configuration of a timing generation circuit.

FIG. 12 is a block diagram showing a modification of the active matrix liquid crystal display device according to the embodiment.

FIG. 13 is an external view schematically showing a configuration of a mobile phone which is a mobile terminal according to the present invention.

[Explanation of symbols]

11: glass substrate, 12: display area, 13U, 13
D: H driver (horizontal drive circuit), 14: V driver (vertical drive circuit), 15: reference voltage generation circuit, 16: counter electrode voltage generation circuit, 17: power supply voltage conversion circuit, 18:
Timing generation circuit, 23 ... unit pixel, 25U, 25D
... Shift register, 26U, 26D ... Sampling latch circuit, 28U, 28D ... Reference voltage selection type DA conversion circuit, 61 ... CPU interface circuit, 62 ... Image memory circuit, 63 ... Optical sensor circuit, 64 ... Light source drive circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 680 G09G 3/20 680S 5K027 3/30 3/30 J H 3/36 3/36 H04M 1 / 00 H04M 1/00 W (72) Inventor Shunichi Maekawa 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 2H093 NA16 NC03 NC09 NC11 NC29 NC41 NC55 ND49 ND54 5C006 AA16 AF83 BB16 BC12 BC20 BF03 BF04 BF43 EB00 FA41 FA51 5C080 AA06 AA10 BB05 DD22 DD27 EE29 FF11 GG12 JJ02 JJ03 JJ04 JJ06 KK07 KK47 5C094 AA15 AA43 AA44 BA03 BA27 BA43 CA19 DA09 DA13 FA01 EB01 FB01 EE37 LL07 5K027 AA11 BB14 FF22 MM17

Claims (14)

[Claims] 1. A display area in which pixels having an electro-optical element are arranged in a matrix, a vertical drive circuit for selecting each pixel in the display area on a row-by-row basis, and a reference for generating a plurality of reference voltages A voltage generation circuit, and a reference voltage selection type DA conversion circuit for selecting a reference voltage corresponding to digital image data from the plurality of reference voltages, wherein the reference voltage selected by the DA conversion circuit is used as an image signal. A horizontal drive circuit that supplies each pixel in the row selected by the vertical drive circuit, a timing generation circuit that generates various timing signals and supplies each circuit unit, and a plurality of single DC voltages having different voltage values. A power supply voltage conversion circuit that converts the voltage into a DC voltage of a specific type and supplies the DC voltage to each circuit unit, the vertical drive circuit, the reference voltage generation circuit, the horizontal drive circuit, and the timing generation circuit. An active matrix display device wherein the raw circuit and the power supply voltage conversion circuit are formed on the same substrate together with the display area using the same process. 2. The active device according to claim 1, further comprising an image memory circuit for storing image data, wherein the image memory is created together with the display area on the same substrate by using the same process. Matrix display device. 3. The active device according to claim 1, further comprising an interface circuit for inputting / outputting data, wherein the interface circuit is formed on the same substrate together with the display area using the same process. Matrix display device. 4. The optical sensor circuit according to claim 1, further comprising an optical sensor circuit for detecting the intensity of the external light, wherein the optical sensor circuit is formed on the same substrate together with the display area using the same process. The active matrix type display device according to the above. 5. The active matrix type display device according to claim 1, wherein said electro-optical element is a liquid crystal cell. 6. A counter electrode voltage generation circuit for generating a voltage applied to a counter electrode of the liquid crystal cell, wherein the counter electrode voltage generation circuit is formed on the same substrate together with the display area using the same process. The active matrix display device according to claim 5, wherein: 7. The active matrix display device according to claim 1, wherein said electro-optical element is an electroluminescence element. 8. A display area as a display section, in which pixels having electro-optical elements are arranged in a matrix, a vertical drive circuit for selecting each pixel of the display area on a row-by-row basis, and a plurality of reference voltages. And a reference voltage selection type D / A conversion circuit for selecting a reference voltage corresponding to digital image data from the plurality of reference voltages, and the reference voltage selected by the D / A conversion circuit A horizontal drive circuit that supplies an image signal to each pixel of a row selected by the vertical drive circuit, a timing generation circuit that generates various timing signals and supplies the timing signals to each circuit unit, A power supply voltage conversion circuit that converts the voltage into a plurality of types of DC voltages having different values and provides the voltage to each circuit unit, wherein the vertical drive circuit, the reference voltage generation circuit, the horizontal drive circuit, Mobile terminal whose serial timing generating circuit and said power supply voltage converting circuit, characterized in that it uses an active matrix display device comprising been created using the same process on the same substrate together with the display area unit. 9. The active matrix display device further includes an image memory circuit for storing image data, wherein the image memory is formed on the same substrate together with the display area using the same process. The mobile terminal according to claim 8, wherein 10. The active matrix display device further includes an interface circuit for inputting and outputting data, and the interface circuit is formed on the same substrate together with the display area using the same process. The mobile terminal according to claim 8, wherein 11. The active matrix display device further includes an optical sensor circuit for detecting the intensity of external light, and the optical sensor circuit is formed on the same substrate together with the display area using the same process. The mobile terminal according to claim 8, wherein: 12. The mobile terminal according to claim 8, wherein the active matrix display device is a liquid crystal display device using a liquid crystal cell as the electro-optical element. 13. The active matrix display device further includes a common electrode voltage generation circuit for generating a voltage applied to a common electrode of the liquid crystal cell, and the common electrode voltage generation circuit is provided on the same substrate together with the display area. 13. The portable terminal according to claim 12, wherein the portable terminal is created using the same process. 14. The portable terminal according to claim 8, wherein the active matrix type display device is an electroluminescent display device using an electroluminescent element as the electro-optical element.