CN1306467C - Data drive used on liquid crystal display panel - Google Patents
Data drive used on liquid crystal display panel Download PDFInfo
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- CN1306467C CN1306467C CNB031067158A CN03106715A CN1306467C CN 1306467 C CN1306467 C CN 1306467C CN B031067158 A CNB031067158 A CN B031067158A CN 03106715 A CN03106715 A CN 03106715A CN 1306467 C CN1306467 C CN 1306467C
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Abstract
The present invention relates to a data driver which drives a plurality of data lines of a liquid crystal display panel according to a plurality of pixel data. In the data driver, a digit buffer is used for respectively receiving and storing the pixel data and outputting a group of pixel data at a time in a selective mode; a digital analog converter is used for respectively receiving the pixel data outputted by the digit buffer, respectively converting the pixel data to a plurality of groups of analog pixel data, and outputting the analog pixel data; an analog buffer is used for respectively receiving the analog pixel data outputted by the digital analog converter and outputting the analog pixel data at a time; an output buffer is used for receiving the analog pixel data outputted by the analog buffer to drive the data lines.
Description
Technical field
The invention relates to a kind of data driver that is used in display panels, and particularly about a kind of data driver of saving required digital analog converter.
Background technology
Because LCD (Liquid Crystal Display, the advantage of thin, the in light weight and low electromagnetic of volume LCD), day by day widely-used in recent years.How reducing the cost of LCD, to increase the competitiveness of product in market, is one of problem of endeavouring of industry.
Please refer to Fig. 1, it has illustrated the system construction drawing of conventional liquid crystal.Be that 1024 * 768 display panels (LCD Panel) 100 is that example is done explanation now with resolution.Display panels 100 is to have 1024 * 3 data lines (Data Line) and 768 sweep traces (Scan Line), and data line and sweep trace are respectively by data driver (Data Driver) 102 and 104 drivings of scanner driver (Scan Driver).Suppose that each data driver 102 can drive 384 data lines, and each scanner driver 104 can drive 256 data lines, then display panels 100 needs 8 data drivers 102 and 3 scanner drivers 104 to drive altogether.Data driver 102-1～102-8 receives many pixel datas (Pixel Data) PD that is transmitted by controller 106 in regular turn under the control of the data controlling signal Cntl_D that a controller 106 is exported.Data driver 102-1～102-8 is that the pixel data PD that will receive handles, and in order to drive many data lines of display panels 100.Scanner driver 104 then is under the control of the scan control signal Cntl_S that controller 106 is exported, and output scanning signal in regular turn is to scan every sweep trace in regular turn.
Please refer to Fig. 2, it has illustrated the circuit block diagram of the data driver 102-1～102-8 among Fig. 1.Traditional data driver 102 is made up of an offset buffer 212, one first line buffer 214A, one second line buffer 214B, a D/A conversion circuit 216 and an output buffer 218.Offset buffer 212 is in order to export a control signal C.The first line buffer 214A is in order to according to control signal C, receives and store the pixel data PD that is exported by controller 106 in regular turn.After the first line buffer 214A finished the reception action, the first line buffer 214A was sent to the second line buffer 214B simultaneously with all pixel data PD that are stored in the first line buffer 214A.The second line buffer 214B exports all pixel data PD to D/A conversion circuit 216 together.Output buffer 218 then is to be used for block form ground (Parallely) to receive the pixel data PD that is exported by D/A conversion circuit 216, and output buffer 218 is gone back block form ground output pixel data PD to a plurality of data lines of display panels 100.
Be example now, be further described at the operational scenario of data driver 102-1～102-8 that Fig. 2 illustrated with data driver 102-1.Suppose controller 106 be at every turn the output two ends to the pixel data PD of (two port) to line buffer 214-1, wherein, each port pixel data includes (channel) red pixel data, a blue pixel data and green pixel data.Promptly be that controller 106 is that 6 pixel data PD of output are to line buffer 214-1 at every turn.Suppose that every pixel data is 8, because data driver 102-1 must drive 384 data lines, so the big palpulus of the first line buffer 214A and the second line buffer 214B respectively is 384 * 8, just 6 * 64 * 8.And controller 106 must each output 6 pixel datas of 6 * 8, export 64 times after, just can finish pixel data input action to a data driver 102-1.After one of them data driver 102 was finished pixel data reception action, next data driver 102 sides began to carry out pixel data and receive action.
After the first line buffer 214A-1 finished pixel data reception action, the first line buffer 214A-1 was that block form ground side by side is sent to the second line buffer 214B-1 with 6 * 64 * 8 the pixel data PD that is stored.Then, the second line buffer 214B-1 then be side by side output pixel data PD to D/A conversion circuit 216-1.D/A conversion circuit 216-1 includes 384 digital analog converters, and (Digital to Analog Converter DAC), also is DAC (1)～DAC (384).Each DAC can change for 1 pixel data PD.So D/A conversion circuit 216-1 can be to 384, just 6 * 64 * 8 pixel data PD side by side carries out digital-to-analogue conversion.
And after D/A conversion circuit 216-1 finished 6 * 64 * 8 the digital-to-analogue conversion of pixel data PD simultaneously, 384 analog pixel data PD block forms ground after D/A conversion circuit 216-1 will change inputed among the output buffer 218-1 simultaneously.Output buffer 218-1 is made up of a plurality of operational amplifiers (OP Amplifier), with the ability of the driving data lines that promotes 384 analog pixel data PD that data driver 102-1 exported.
In the general circuit layout, digital analog converter DAC has taken considerable area usually.In each traditional data driver 102, must carry out digital-to-analogue conversion to 384 data pixel PD simultaneously, so must use 384 digital analog converters.So, will make that the chip area of whole data driver 102 is too big, and cost is too high.So the area that how to reduce required digital analog converter is considerable to reduce cost.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of data driver, can reduce digital analog converter required area in chip effectively, to reach the purpose that reduces chip area and reduce cost.
According to purpose of the present invention, a kind of data driver is proposed, drive many data lines of a display panels according to a plurality of pixel datas, this data driver comprises: a digit buffer, comprise one first line buffer and one second line buffer, in order to receiving and to store these pixel datas respectively, and optionally once export a pixel data; One digital analog converter in order to receiving these pixel datas by the output of this digit buffer respectively, and converts these pixel datas to many analog pixel data respectively and exports, and exports one at every turn; One analogue buffer in order to receiving these analog pixel data by the output of this digital analog converter respectively, and is once exported these analog pixel data; One output buffer is in order to receive these analog pixel data by this analogue buffer output, to drive these data lines; And control circuit, in order to control described first and second line buffers or analogue buffer, finish its corresponding storage output action that receives.
According to another object of the present invention, a kind of data driver is proposed, drive many data lines of a display panels according to a plurality of pixel datas, this data driver comprises: a digit buffer, comprise one first line buffer and one second line buffer, receive respectively and store these pixel datas, and optionally once export N pixel data, N is greater than 1 positive integer and less than the quantity of these data lines; N digital analog converter receives these pixel datas by this digit buffer output, and converts N pixel data to N analog pixel data simultaneously and export; One analogue buffer receives these analog pixel data by this N digital analog converter output respectively, and once exports these analog pixel data; One output buffer receives these analog pixel data by this analogue buffer output, to drive these data lines; And control circuit, in order to control described first and second line buffers or analogue buffer, finish its corresponding storage output action that receives.
Therefore,, can reduce digital analog converter required area in chip effectively, to reduce chip area and to reduce cost according to data driver of the present invention.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 has illustrated the system construction drawing of conventional liquid crystal.
Fig. 2 has illustrated the circuit block diagram of the data driver 102-1～102-8 among Fig. 1.
Fig. 3 illustrates the circuit block diagram according to a plurality of data drivers of the present invention one first embodiment.
Fig. 4 has illustrated the detailed internal circuit diagram of the analogue buffer of Fig. 3.
Fig. 5 illustrates the circuit block diagram according to a plurality of data drivers of the present invention one second embodiment.
The drawing reference numeral explanation
100: display panels
102,302,502: data driver
104: scanner driver
106: controller
212,312,512: offset buffer
214,314A, 314B, 514A, 514B: line buffer
216,516: D/A conversion circuit
218,318,518: output buffer
314,514: digit buffer
316,516 (1)～(6): digital analog converter
317,517: analogue buffer
322,522: the line buffer control circuit
324,524: the analogue buffer control circuit
Embodiment
Essence of the present invention is, in each data driver, only use one or several digital analog converters, and make the mode of pixel data with one or number, input to digital analog converter, to carry out digital-to-analogue conversion in regular turn, reach the purpose of the chip area of saving data driver.
First embodiment
Please refer to Fig. 3, it has illustrated the circuit block diagram according to a plurality of data drivers of the present invention one first embodiment.Display panels needs a plurality of data drivers come driving data lines, in Fig. 3, is to be that example is done explanation with 8 data driver 312-1～312-8.Each data driver 302 comprises: an offset buffer 312, a digit buffer 314, a digital analog converter 316, an analogue buffer 317, an and output buffer 318.One first control signal C ' is to digit buffer 314 in offset buffer 312 outputs.Digit buffer 314 receives and storage pixel data PD in regular turn according to the first control signal C '.Digit buffer 314 is optionally exported these pixel datas PD respectively.Wherein, digit buffer 314 is once exported a pixel data PD to digital analog converter 316.The pixel data PD that digital analog converter 316 receives by digit buffer 314 outputs converts pixel data PD to analog pixel data APD afterwards.Analogue buffer 317 receives the analog pixel data APD of storage by digital analog converter 316 outputs, and the analog pixel data APD that is stored is once exported.Output buffer 318 receives the analog pixel data APD of analogue buffer 317 outputs, with driving data lines.
Digit buffer 314 can be made up of one first line buffer 314A and one second line buffer 314B.The first line buffer 314A receives and storage pixel data PD in regular turn according to control signal C '.After the first line buffer 314A finished the reception action, this first line buffer 314A was sent to the second line buffer 314B simultaneously with the pixel data PD block form ground that all are stored in the first line buffer 314A.
Data driver 302 of the present invention also comprises a line buffer control circuit 322.The second line buffer 314B is made up of a plurality of line buffers unit (not being illustrated among the figure).Line buffer control circuit 322 is in order to export one second control signal C2 to the second line buffer 314B.The second line buffer 314B then is under the control of online Buffer control circuit 322, once to export the mode of a pixel data, and output pixel data PD optionally.Just, the second control signal C2 once selects a line buffer unit, and the second line buffer 314B is the pixel data PD that the selecteed line buffer of output unit is stored.
For instance, the line buffer unit can be made up of latch (Latch) and switch.Latch is in order to storage pixel data PD, and switch is conducting or not conducting under the control of the second control signal C2 then.The above-mentioned optionally mode of output for example is can pass through the second control signal C2, with the switch conduction of selected line buffer unit, so that the pixel data PD that is stored in the latch of selected line buffer unit output.
Wherein, digital analog converter 316 once carries out the digital-to-analogue conversion action to a pixel data PD, and once exports an analog pixel data APD.
In addition, analogue buffer 317 can be made up of a plurality of simulated cushioned unit, comprises simulated cushioned unit (1)～simulated cushioned unit (384).Each simulated cushioned unit can be reached by a sample-and-hold circuit (Sampleand Hold Circuit).And analogue buffer 317 is controlled by an analogue buffer control circuit 324.Analogue buffer control circuit 324 is that output one the 3rd control signal C3 is with control analogue buffer 324.The 3rd control signal comprises signal C3-1～C3-384, in order to control simulated cushioned unit (1)～simulated cushioned unit (384) respectively.Under the control of the 3rd control signal C3, these simulated cushioned unit are in order to receive the analog pixel data APD by digital analog converter 316 outputs in regular turn.And be in a mode of one from the analog pixel data APD of digital analog converter 316 output, be stored among simulated cushioned unit (1)～simulated cushioned unit (384).After analogue buffer 317 was finished the reception action, analogue buffer 317 was that analog pixel data APD is exported simultaneously to output buffer 318 in block form ground.
Wherein, the control mode to analogue buffer 317 of the 3rd control signal C3 that exported of analogue buffer control circuit 324 can be following mode.The 3rd control signal C3 can select the simulated cushioned unit that will electrically connect with digital analog converter 316, to receive the analog pixel data APD of digital analog converter 316 outputs.The 3rd control signal C3 also can control the time point of the output analog pixel data APD of simulated cushioned unit, for example be to control simulated cushioned unit (1)～simulated cushioned unit (384) after 384 analog pixel data APD all finish receiving, output buffer 318 is side by side exported to 384 analog pixel data APD again in simulated cushioned unit (1)～(384).
Now the operational scenario at the data driver of the present invention 302 that Fig. 3 illustrated is further described.Under the roughly the same situation of the operational scenario of data driver 302-1～302-8, the driver 302-1 that now fetches data is that example illustrates it.
Suppose that the first line buffer 314A-1 is the pixel data PD that at every turn receives dual-port, promptly all receive 2 red pixel data, 2 blue pixel data and 2 green pixel data, totally 6 pixel datas at every turn simultaneously.If every pixel data PD is 8, then each first line buffer 314A-1 receives the pixel data PD of 6 * 8=48 position.By allowing one of among the offset buffer 312-1 64 for enabling, that is to say and allow one of control signal C '-1 (1)～C '-1 (64) for enabling, can choose the memory address of the first different line buffer 314A-1, received pixel data PD is stored in the memory address of the corresponding first line buffer 314A-1.After the first line buffer 314A-1 like this need receive 64 times, 384 pixel data PD can be received.Wherein, the capacity of the first line buffer 314A-1 can be 6 * 64 * 8.
After the first line buffer 314A-1 finished the reception action, all pixel data PD that are stored in the first line buffer 314A-1 were that block form ground is sent to the second line buffer 314B-1 simultaneously.Wherein, the capacity of the second line buffer 314A-1 similarly can be 6 * 64 * 8.
When the second line buffer 314B-1 receives after all are stored in pixel data PD among the first line buffer 314A-1, the second line buffer 314B-1 follows under the control of online Buffer control circuit 322-1, optionally once export a pixel data PD to digital analog converter 316-1, so that pixel data PD is carried out digital-to-analogue conversion.Wherein, the second line buffer 314B-1 has 384 line buffer unit, supposes that these 384 line buffer unit are selected in regular turn from left to right to export the digital pixel data PD that it is stored.Digital analog converter 316-1 has then carried out 384 times digital-to-analogue conversion, finishes with the digital pixel data PD conversion that 384 are stored among the second line buffer 314B-1.
That is to say, line buffer control circuit 322-1 controls the second line buffer 314B-1 and exports the pixel data PD that is stored stroke by stroke, digital analog converter 316-1 receives pixel data PD stroke by stroke, and once carries out the digital-to-analogue conversion action at a pixel data PD.So, the second line buffer 314B-1 must export 384 times pixel data PD, and D/A conversion circuit 316-1 must carry out after 384 times the digital-to-analogue conversion, and 384 pixel data PD conversions that just now all are stored among the second line buffer 314B-1 finish.Under the control of the control signal C3 that analogue buffer control circuit 324-1 is exported, analog pixel data APD after the conversion is in a mode of one, is stored in order in simulated cushioned unit (1)～simulated cushioned unit (384) of analogue buffer 317-1.
Then, after 384 analog pixel data APD all are stored in analogue buffer 317-1, analogue buffer 317-1 is under the control of the control signal C3 that analogue buffer control circuit 324-1 is exported, and these 384 analog pixel data APD are exported among the output buffer 318-1.Analog pixel data APD for example is 384 operational amplifiers via 384 among output buffer 318-1 output buffer cell (1)～(384).Output buffer cell (1)～(384) electrically connect data line respectively.
The upper limit of the switching time of carrying out digital-to-analogue conversion of the D/A conversion circuit 316 in the present embodiment can be up to 1/384th sweep time.Wherein, be meant that the time that the image of a pairing column of pixels of sweep trace shows, the demonstration time of a picture that approximates whole LCD is divided by the number of sweep trace so-called sweep time.When data pixels PD imported the first line buffer 314A, in a sweep time, 384 * 8=3092 pixel data PD must input to the first line buffer 314A-1～first line buffer 314A-8 in regular turn.Yet, because each second line buffer 314B is in a sweep time, only need export 384 pixel datas, be that each digital analog converter 316 only need be handled 384 pixel datas in a sweep time, the old friend, the processing speed of the speed of the output pixel data PD of the second line buffer 314B and digital analog converter 316, can be the first line buffer 314A reception pixel data PD speed 1/8.That is to say that the required operating frequency of digital analog converter used in the present invention can be the octuple of the incoming frequency of pixel data PD.Such hardware requirement is easy to and can reaches.
Please refer to Fig. 4, it has illustrated the detailed internal circuit diagram of the analogue buffer 317 of Fig. 3.Each simulated cushioned unit is to be reached by a sample-and-hold circuit, and each sample-and-hold circuit is by switch S 1, S2, S3 and S4, and capacitor C 1 is formed with C2.When receiving 384 analog pixel data APD of a certain row pixel, switch S 1 (1)～S1 (384) is conducting in regular turn, and analog pixel data APD is stored among capacitor C 1 (1)～C1 (384) in regular turn.And when receiving 384 analog pixel data APD of next column pixel, switch S 1 (1)～S1 (384) transfers not conducting to, switch S 3 (1)～S3 (384) then transfer conducting to, and 384 analog pixel data APD of next column pixel are stored among capacitor C 2 (1)～C2 (384).Simultaneously, switch S 2 (1)～S2 (384) transfer conducting to, make 384 analog pixel data APD that stored among capacitor C 1 (1)～C1 (384) export output buffer cell (1)～output buffer cell (384) respectively to.And when receiving again 384 analog pixel data APD of next column pixel, switch S 1 (1)～S1 (384) transfers conducting to, switch S 3 (1)～S3 (384) then transfer not conducting to, and 384 analog pixel data APD of next column pixel are stored among capacitor C 1 (1)～C1 (384).Simultaneously, switch S 4 (1)～S4 (384) transfer conducting to, make 384 analog pixel data APD that stored among capacitor C 2 (1)～C2 (384) export output buffer cell (1)～output buffer cell (384) respectively to.
The data driver 302 of present embodiment shown in Figure 3 is compared with the data driver 102 of Fig. 2, because the D/A conversion circuit 216 in the data driver 102 needs 384 digital analog converters, to carry out digital-to-analogue conversion at 384 pixel data PD simultaneously, the data driver 302 of present embodiment then only needs a digital analog converter 316, so present embodiment can reach the advantage of saving chip area.
Second embodiment
Please refer to Fig. 5, it has illustrated the circuit block diagram according to a plurality of data drivers of second embodiment of the invention.Each data driver 502 comprises: an offset buffer 512, a digit buffer 514, several digital analog converters, an analogue buffer 517, an and output buffer 518.Digit buffer 514 can be made up of one first line buffer 514A and one second line buffer 514B.
Different with first embodiment shown in Figure 3 is, the employed D/A conversion circuit of the data driver 502 of second embodiment 516 is made up of a plurality of digital analog converter, its number is less than 384, for example be 6, be respectively digital analog converter 516 (1)～digital analog converters 516 (6).Therefore, under the control of online Buffer control circuit 322, can there be 6 pixel data PD to export digital analog converter 516 (1)～516 (6) to by the second line buffer 514B simultaneously, and be carried out digital-to-analogue conversion simultaneously.Under the control of analogue buffer control circuit 324,6 analog pixel data APD after the conversion can be stored in 6 simulated cushioned unit to carry out follow-up processing simultaneously.
In two above embodiment, the offset buffer of data driver and the size of line buffer are to change along with different designs.And the resolution of LCD, pixel data imports the figure place of data driver at every turn, and the stroke count of the pixel data of the each conversion of digital analog converter, and the needs in the time of all can be according to design are adjusted.Digit buffer also can optionally the impact damper or the internal memory of output data replace by other.Optionally pixel data is carried out various variations or the retouching carried out under the purpose of digital-to-analogue conversion reaching, all within the scope of the present invention.When illustrating, though offset buffer, line buffer control circuit, be distinguished into different circuit with the analogue buffer control circuit, actual taking up an official post, also can be integrated into a special control circuit more than both.
The advantage of above-mentioned two the disclosed data drivers of embodiment of the present invention is: required digital analog converter reduces many than conventional practice, so the present invention can reduce digital analog converter required area in chip effectively, to reach the purpose that reduces chip area and reduce cost.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; those skilled in the art; do not breaking away from the spirit and scope of the invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the appending claims person of defining.
Claims (12)
1. data driver drives many data lines of a display panels according to a plurality of pixel datas, it is characterized in that comprising:
One digit buffer comprises one first line buffer and one second line buffer, in order to receiving and to store these pixel datas respectively, and optionally once exports a pixel data;
One digital analog converter in order to receiving these pixel datas by the output of this digit buffer respectively, and converts these pixel datas to many analog pixel data respectively and exports, and exports one at every turn;
One analogue buffer in order to receiving these analog pixel data by the output of this digital analog converter respectively, and is once exported these analog pixel data;
One output buffer is in order to receive these analog pixel data by this analogue buffer output, to drive these data lines; And
Control circuit in order to control described first and second line buffers or analogue buffer, is finished its corresponding storage output action that receives.
2. data driver as claimed in claim 1 also comprises an offset buffer, receives these pixel datas in order to indicate this digit buffer.
3. data driver as claimed in claim 1, wherein this first line buffer receives and stores these pixel datas respectively; When this first line buffer finish receive action after, this first line buffer with all be stored in this first line buffer these pixel data block forms be sent to this second line buffer; This second line buffer is once exported a pixel data to this digital analog converter.
4. data driver as claimed in claim 3, wherein this control circuit comprises a line buffer control circuit, and this second line buffer comprises a plurality of line buffers unit; Wherein, this line buffer control circuit is in order to once selecting one of these line buffer unit, and this pixel data that this selecteed this line buffer unit of second line buffer output is stored.
5. data driver as claimed in claim 1, wherein this analogue buffer comprises a plurality of simulated cushioned unit, these simulated cushioned unit receive these analog pixel data by this digital analog converter output respectively.
6. data driver as claimed in claim 5, wherein this control circuit also comprises an analogue buffer control circuit, in order to indicate this analogue buffer to receive these analog pixel data of this digital analog converter output respectively and to be stored among these simulated cushioned unit; And after this analogue buffer is finished the reception action, indicate these these analog pixel data of analogue buffer block form ground output to this output buffer.
7. data driver drives many data lines of a display panels according to a plurality of pixel datas, it is characterized in that comprising:
One digit buffer comprises one first line buffer and one second line buffer, receives respectively and stores these pixel datas, and optionally once export N pixel data, and N is greater than 1 positive integer and less than the quantity of these data lines;
N digital analog converter receives these pixel datas by this digit buffer output, and converts N pixel data to N analog pixel data simultaneously and export;
One analogue buffer receives these analog pixel data by this N digital analog converter output respectively, and once exports these analog pixel data;
One output buffer receives these analog pixel data by this analogue buffer output, to drive these data lines; And
Control circuit in order to control described first and second line buffers or analogue buffer, is finished its corresponding storage output action that receives.
8. data driver as claimed in claim 7 also comprises an offset buffer, receives these pixel datas in order to indicate this digit buffer.
9. data driver as claimed in claim 8, wherein this first line buffer receives and stores these pixel datas respectively; When this first line buffer finish receive action after, this first line buffer with all be stored in this first line buffer these pixel data block forms be sent to this second line buffer; N pixel data of this second line buffer selective one-time output is to these digital analog converters.
10. data driver as claimed in claim 9, wherein this control circuit comprises a line buffer control circuit, and this second line buffer comprises a plurality of line buffers unit; Wherein, this line buffer control circuit is once selected N of this a few line buffers unit, and these pixel datas that this selecteed this line buffer unit of second line buffer output is stored.
11. data driver as claimed in claim 7, wherein this analogue buffer comprises a plurality of simulated cushioned unit, and these simulated cushioned unit receive these analog pixel data by these digital analog converter outputs respectively.
12. data driver as claimed in claim 11, wherein this control circuit also comprises an analogue buffer control circuit, in order to indicate this analogue buffer to receive from these pixel datas of these digital analog converters output respectively and to be stored among these simulated cushioned unit; And after this analogue buffer is finished the reception action, indicate these these pixel datas of analogue buffer block form ground output to this output buffer.
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| CNB031067158A CN1306467C (en) | 2003-02-27 | 2003-02-27 | Data drive used on liquid crystal display panel |
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| CNB031067158A CN1306467C (en) | 2003-02-27 | 2003-02-27 | Data drive used on liquid crystal display panel |
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| CN1306467C true CN1306467C (en) | 2007-03-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405420A (en) * | 2014-09-09 | 2016-03-16 | 拉碧斯半导体株式会社 | Display Device, Display Panel Driver, And Image Data Signal Transmission Method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7327297B2 (en) * | 2006-06-30 | 2008-02-05 | Himax Technologies Limited | Source driver of liquid crystal display and the driving method |
| JP5233972B2 (en) * | 2009-11-30 | 2013-07-10 | ソニー株式会社 | SIGNAL LINE DRIVE CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE |
| US8698958B2 (en) * | 2010-06-16 | 2014-04-15 | Silicon Image, Inc. | Mechanism for memory reduction in picture-in-picture video generation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000137207A (en) * | 1998-11-04 | 2000-05-16 | Oki Electric Ind Co Ltd | Liquid crystal display driving circuit |
| JP2002202764A (en) * | 2000-12-21 | 2002-07-19 | Renei Kagi Kofun Yugenkoshi | Data driver circuit of thin-film transistor liquid crystal display |
| CN1378194A (en) * | 2001-04-03 | 2002-11-06 | 华邦电子股份有限公司 | Driving circuit of liquid crystal display device and its image display method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000137207A (en) * | 1998-11-04 | 2000-05-16 | Oki Electric Ind Co Ltd | Liquid crystal display driving circuit |
| JP2002202764A (en) * | 2000-12-21 | 2002-07-19 | Renei Kagi Kofun Yugenkoshi | Data driver circuit of thin-film transistor liquid crystal display |
| CN1378194A (en) * | 2001-04-03 | 2002-11-06 | 华邦电子股份有限公司 | Driving circuit of liquid crystal display device and its image display method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105405420A (en) * | 2014-09-09 | 2016-03-16 | 拉碧斯半导体株式会社 | Display Device, Display Panel Driver, And Image Data Signal Transmission Method |
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