CN1848236A - Circuit structure for dual resolution design, display panel using same and electronic device - Google Patents
Circuit structure for dual resolution design, display panel using same and electronic device Download PDFInfo
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- CN1848236A CN1848236A CN 200610072599 CN200610072599A CN1848236A CN 1848236 A CN1848236 A CN 1848236A CN 200610072599 CN200610072599 CN 200610072599 CN 200610072599 A CN200610072599 A CN 200610072599A CN 1848236 A CN1848236 A CN 1848236A
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Abstract
A dual resolution circuit for supporting normal resolution display mode and half resolution display mode is disclosed. In the dual resolution circuit, cascaded shift registers are controlled by a group of clock signals to generate intermediate scan signals in response to a start pulse. A normal/reverse scan switch, controlling a normal scan mode and a reverse scan mode, feeds back the intermediate scan signal from one shift register to another shift register. A dual resolution switch switches signal paths of the intermediate scan signals to logic gates. The logic gates perform logic operation on an enablement signal and the intermediate scan signals to generate final scan signals used in dual resolution display modes.
Description
Technical field
The invention relates to a kind of circuit structure for dual resolution design of supporting normal (normal) resolution display mode and half-resolution display mode, and use its display panel and electronic installation.
Background technology
LCD (LCD) has become general panel display apparatus.In LCD, have two kinds of resolution models at least, normal resolution display mode and half-resolution display mode.Generally speaking, LCD is shown under the normal resolution display mode.In some cases, such as, using down for saving energy or being in low resolution, LCD also can be shown under the low resolution display mode.
Fig. 1 a and Fig. 1 b show respectively under normal resolution display mode and the half-resolution display mode, for the definition of unit picture element (unit pixel).Please refer to Fig. 1 a, under the normal resolution display mode, a unit picture element comprises a complete pixel.A complete pixel has R, three sub-pixels of G and B.Please refer to Fig. 1 a, under the half-resolution display mode, a unit picture element comprises four complete pixel.In Fig. 1 a and 1b, symbol R, G and B represent R respectively, G and B sub-pixel, and " R1 ", " R2 " and " R3 " then represent first pixel column respectively, second pixel column and the 3rd pixel column.As the different unit picture elements of Fig. 1 a, can obtain the dual resolution design function by definition with 1b.
Two kinds of vertical scanning signals are used to be defined in the different unit picture elements under the different resolution pattern.Fig. 2 a and 2b show two kinds of vertical scanning signals respectively.In Fig. 2 a, for defining the unit picture element that is applicable to the normal resolution pattern, in a pulse, pixel column of a vertical scanning signal scanning.In Fig. 2 b, for defining the unit picture element that is applicable to the half-resolution pattern, in a pulse, two pixel columns of a vertical scanning signal scanning.
With resolution is that the LCD panel of 640 (row) *, 480 (passages) is an example, in this panel, need use 640 vertical scanning signals to scan 640 pixel columns.Under the normal resolution pattern, can demonstrate the resolution of 640*480.Under the half-resolution pattern, can demonstrate the resolution of 320*240.
So, the circuit structure for dual resolution design of a kind of low cost and high display performance better can be arranged, and use its display panel and electronic installation.
Summary of the invention
One of purpose of the present invention is to provide a kind of circuit structure for dual resolution design, and uses its display panel and electronic installation, and the cost of this circuit structure for dual resolution design is low, the high display performance of the little tool again of circuit area.
For reaching above-mentioned and other purpose, the invention provides a kind of dual resolution design circuit, can be supported in the dual resolution design display mode in the display device.This dual resolution design circuit comprises shift register stage, dual resolution design switch and logic circuit stage.This shift register stage receives initial pulse and at least four clock signals, produces a plurality of middle attitude sweep signals.This dual resolution design switch is controlled by the resolution model control signal, to switch the signal path of attitude sweep signal in those.This logic circuit stage receives attitude sweep signal in those that are switched by this shift register stage produced in those attitude sweep signal and by this dual resolution design switch, to produce a plurality of sweep signals, carries out the dual resolution design display mode.
The present invention also provides a kind of display panel, has the dual resolution design circuit that can support the dual resolution design display mode.This dual resolution design circuit comprises: clock generator produces the first, second, third and the 4th clock signal; Shift register stage receives initial pulse and this first, second, third and the 4th clock signal, produces a plurality of middle attitude sweep signals; Just sweep/the anti-switch of sweeping, receive and just sweeping signal, anti-signal and this initial pulse swept, to control just sweeping or counter sweeping of this display panel; The dual resolution design switch is controlled by the resolution model control signal, to switch the signal path of attitude sweep signal in those; And logic circuit stage, receive attitude sweep signal in those that are switched by this shift register stage produced in those attitude sweep signal and by this dual resolution design switch, to produce a plurality of sweep signals, carry out the dual resolution design display mode.
The present invention provides a kind of electronic installation with display panel again.This display panel comprises the dual resolution design circuit, to be supported in the dual resolution design display mode in this display panel.This dual resolution design circuit comprises: clock generator produces the first, second, third and the 4th clock signal; Shift register stage receives initial pulse and this first, second, third and the 4th clock signal, produces a plurality of middle attitude sweep signals; Just sweep/the anti-switch of sweeping, receive and just sweeping signal, anti-signal and this initial pulse swept, to control just sweeping or counter sweeping of this display panel; The dual resolution design switch is controlled by the resolution model control signal, to switch the signal path of attitude sweep signal in those; And logic circuit stage, receive attitude sweep signal in those that are switched by this shift register stage produced in those attitude sweep signal and by this dual resolution design switch, to produce a plurality of sweep signals, carry out the dual resolution design display mode.
For above-mentioned and other purpose, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 a and 1b are presented at the unit picture element under normal resolution pattern and the half-resolution pattern.
Fig. 2 a and 2b display application two kinds of vertical scanning signals under normal resolution pattern and half-resolution pattern.
Fig. 3 shows the calcspar of dual resolution design circuit according to an embodiment of the invention.
Fig. 4 a shows the clock generator of the dual resolution design circuit that is used for Fig. 3, and Fig. 4 b shows the clock signal oscillogram that clock generator produced by Fig. 4 a.
Fig. 5 shows the shift register of the dual resolution design circuit be used for Fig. 3, with and signal output waveform figure.
Fig. 6 is presented at the sweep signal oscillogram under the normal resolution pattern.
Fig. 7 is presented at the sweep signal oscillogram under the half-resolution pattern.
Fig. 8 a～8d just is presented at and sweeps/the anti-signal path of sweeping under pattern and the normal/half-resolution pattern.
Fig. 9 shows electronic installation according to another embodiment of the present invention.
[main element label declaration]
300: the dual resolution design circuit
310: clock generator
330: shift register stage
350: just sweep/the anti-switch of sweeping
370: the dual resolution design switch
390: logic circuit stage
SR311, SR313, SR315, SR317: shift register
TM351～TM358, TM371, TM373, TM375, TM377, TM401, TM403, TM405, TM407: transmission gate
NAND1～NAND4:NAND door
311a, 311c, 313a, 313c, 315a, 315c, 317a, 317c: clocked inverter
311b, 313b, 315b, 317b: phase inverter
900: electronic installation
920: display panel
940: the dual resolution design circuit
Embodiment
Fig. 3 shows the calcspar of dual resolution design circuit according to an embodiment of the invention.Output signal GATE1～GATE4 that this dual resolution design circuit is produced can be as the sweep signal under the different resolution display mode, the sweep signal shown in Fig. 2 a or 2b.With reference to figure 3, this dual resolution design circuit 300 comprises: clock generator 310, shift register stage 330 is just swept/the anti-switch 350 of sweeping, dual resolution design switch 370 and logic circuit stage 390.
The operation of shift register stage 330 and oscillogram thereof are to be shown in Fig. 5.
Just sweep/counter sweep switch 350 according to just sweep/anti-control signal CSV and the XCSV of sweeping control and will just sweep or counter sweeping.Just sweep/the anti-switch 350 of sweeping comprises eight transmission gate TM351～TM358 at least.Just sweeping under the pattern, to the direction of scanning of pixel column such as being, by the top to the bottom.Sweeping under the pattern counter, then is opposite to the direction of scanning of pixel column, such as being, by the bottom to the top.Signal XCSV is the inversion signal of signal CSV.When needs were just swept, signal CSV was a logic high, that is signal XCSV is a logic low.On the other hand, when needs are anti-when sweeping, signal CSV is a logic low, that is signal XCSV is a logic high.Just sweep/anti-detail operations of sweeping switch 350 can understand with reference to figure 8a～8d.
Dual resolution design switch 370 is controlled according to resolution model control signal NORMAL and HALF will carry out normal resolution pattern or half-resolution pattern.Dual resolution design switch 370 comprises four transmission gate TM371, TM373, TM375, TM377 at least.Under normal resolution pattern and half-resolution pattern, dual resolution design switch 370 can conduct to logic circuit stage 390 with suitable middle attitude sweep signal SR_OUT_1～SR_OUT_4, to produce final sweep signal GATE1～GATE4.The detail operations of dual resolution design switch 370 can be with reference to figure 6, Fig. 7 and Fig. 8 a～8d and understand.When needs normal resolution pattern, signal NORMAL is a logic high, that is signal HALF is a logic low.When needs half-resolution pattern, signal NORMAL is a logic low, that is signal HALF is a logic high.
Fig. 4 a shows the clock generator 310 of the dual resolution design circuit that is used for Fig. 3, and Fig. 4 b shows the clock signal oscillogram that clock generator produced by Fig. 4 a.Shown in Fig. 4 a, clock generator 310 comprises four transmission gate TM401, TM403, TM405 and TM407.Conducting/not the conducting of transmission gate is controlled by signal NORMAL and HALF.When signal NORMAL is logic high and signal HALF when being logic low, that is be in normal resolution pattern following time, transmission gate TM403 and TM407 are conductings, and transmission gate TM401 and not conducting of TM405.So, be in normal resolution pattern following time, CKV3=CKV1 and CKV4=CKV2.Similarly, when signal NORMAL is logic low and signal HALF when being logic high, that is be in half-resolution pattern following time, transmission gate TM403 and TM407 are not conductings, then conducting of transmission gate TM401 and TM405.So, be in half-resolution pattern following time, CKV4=CKV1 and CKV3=CKV2.The waveform of signal CKV1～CKV4 under the different resolution pattern is shown among Fig. 4 b.Signal CKV1～CKV4 is used to be controlled at the mode of operation of the shift register of shift register stage 330.
Fig. 5 shows the shift register 330 of the dual resolution design circuit be used for Fig. 3, with and signal output waveform figure.Shift register stage 330 comprises shift register SR311～SR317 that the level Four string changes at least.Be simplicity of illustration, in Fig. 3 and Fig. 5, only demonstrate 4 grades shift register, but the present invention be not limited to this.Each shift register comprises two clocked inverters and a phase inverter.Shift register SR 311 comprise clocked inverter 311a/311c, with phase inverter 311b.Shift register SR313 comprise clocked inverter 313a/313c, with phase inverter 313b.Shift register SR 315 comprise clocked inverter 315a/315c, with phase inverter 315b.Shift register SR317 comprise clocked inverter 317a/317c, with phase inverter 317b.As known, clocked inverter has two operation attitudes: latch attitude and transmitting state.Be in when latching attitude, the output of clocked inverter can be latched, that is the output of shift register also can be latched.When being in transmitting state, then the output of shift register is its input.The framework of shift register and clocked inverter does not limit especially at this.
As Fig. 3 and shown in Figure 5, clock signal CKV 1～CKV4 is used to control the state of shift register.Such as, clock signal CKV 1 is used to control shift register SR311 with CKV2.If just sweeping under the pattern, the initial pulse that is received by shift register stage 330 is signal STVUI; If sweep under the pattern counter, the initial pulse that is received by shift register stage 330 is signal STVBI.In addition, depend on and just sweep or the anti-pattern of sweeping that initial pulse can input to first or last shift register in the shift register stage 330.Fig. 5 only demonstrates and is just sweeping under the pattern, and initial pulse STV (STVUI) can input to first order shift register SR311, as its input signal; The output signal of previous stage shift register is then treated as the input signal of next stage register.Such as, just sweeping under the pattern, the output signal SR_OUT_1 of first order shift register SR311 is as the input signal of next stage shift register SR313.On the other hand, sweep under the pattern counter, initial pulse STV (STVBI) can input to afterbody shift register SR317, as its input signal; The output signal of next stage shift register is then treated as the input signal of previous stage register, but for simplicity, Fig. 5 does not demonstrate anti-situation of sweeping.Such as, sweeping under the pattern counter, the output signal SR_OUT_4 of afterbody shift register SR317 is as the input signal of its previous stage shift register SR315.Just sweep/the anti-switch 350 of sweeping can conduct to suitable shift register with suitable initial pulse and middle attitude sweep signal.Just sweep/anti-detailed conduction operation of sweeping switch 350 will describe with reference to figure 8a～8d.
Fig. 6 is presented at the oscillogram of the sweep signal GATE1～GATE4 under the normal resolution pattern.Under the normal resolution pattern, in order to produce the sweep signal GATE1～GATE4 shown in Fig. 2 a, GATE1～GATE4 can be expressed as follows:
GATE1＝NAND(SR_OUT_1，SR_OUT_2，ENBV)
GATE2＝NAND(SR_OUT_2，SR_OUT_3，ENBV)
GATE3＝NAND(SR_OUT_3，SR_OUT_4，ENBV)
GATE4＝NAND(SR_OUT_4，SR_OUT_5，ENBV)
Though be not shown in the accompanying drawing, signal SR_OUT_5 representative be output signal by the level V shift register (not shown) in the shift register stage 330.Though only demonstrate level Four shift register and four sweep signal GATE1～GATE4 of shift register stage 330 in Fig. 3, the present invention is not limited to this.Such as, have under 640 pixel columns at the LCD panel, need 640 sweep signal GATE1～GATE640, and shift register stage 330 also needs 640 shift registers.
Fig. 7 is presented at the sweep signal oscillogram under the half-resolution pattern.Under the half-resolution pattern, in order to produce the sweep signal GATE1～GATE4 shown in Fig. 2 b, GATE1～GATE4 can be expressed as follows:
GATE1＝NAND(SR_OUT_1，SR_OUT_3，ENBV)
GATE2＝NAND(SR_OUT_2，SR_OUT_3，ENBV)
GATE3＝NAND(SR_OUT_3，SR_OUT_5，ENBV)
GATE4＝NAND(SR_OUT_4，SR_OUT_5，ENBV)
As shown in Figure 3, the output signal SR_OUT_1 of shift register stage 330～SR_OUT_4 can bypass just sweeps/instead sweep switch 350 and arrive dual resolution design switch 370, so just sweep/the anti-switch 350 of sweeping is not shown among Fig. 6 and Fig. 7.
Fig. 8 a～8d just is presented at and sweeps/the anti-signal path of sweeping under pattern and the normal/half-resolution pattern.
Fig. 8 a be presented at just sweep with the normal resolution pattern under signal path.In the case, just sweep/anti-transmission gate TM352, the TM353 that sweeps switch 350, TM356 and TM357 can conductings, and the transmission gate TM371 of dual resolution design switch 370 and TM375 also can conductings, but other then not conducting of transmission gate.Pulse STVUI can be fed into shift register SR311, and pulse STVBO is then produced by shift register SR317.Pulse STVBI can be fed into NAND door NAND4, as one of input signal.
Fig. 8 b be presented at just sweep with the half-resolution pattern under signal path.In the case, just sweep/anti-transmission gate TM352, the TM353 that sweeps switch 350, TM356 and TM357 can conductings, and the transmission gate TM373 of dual resolution design switch 370 and TM377 also can conductings, but other then not conducting of transmission gate.Pulse STVUI can be fed into shift register SR311, and pulse STVBO is then produced by shift register SR317.Pulse STVBI can be fed into NAND door NAND4, as one of input signal.
Fig. 8 c be presented at counter sweep with the normal resolution pattern under signal path.In the case, just sweep/anti-transmission gate TM351, the TM354 that sweeps switch 350, TM355 and TM358 can conductings, and the transmission gate TM371 of dual resolution design switch 370 and TM375 also can conductings, but other then not conducting of transmission gate.Pulse STVBI can be fed into shift register SR317, and pulse STVUO is then produced by shift register SR311.
Fig. 8 d be presented at counter sweep with the half-resolution pattern under signal path.In the case, just sweep/anti-transmission gate TM351, the TM354 that sweeps switch 350, TM355 and TM358 can conductings, and the transmission gate TM373 of dual resolution design switch 370 and TM377 also can conductings, but other then not conducting of transmission gate.Pulse STVBI can be fed into shift register SR317, and pulse STVUO is then produced by shift register SR311.
Utilize this embodiment, can reach the circuit structure for dual resolution design that to support normal resolution display mode and half-resolution display mode.This circuit structure for dual resolution design is still low-cost and high-performance arranged again.
Fig. 9 shows electronic installation according to another embodiment of the present invention.In Fig. 9, electronic installation 900 comprises display panel 920 at least, and this display panel 920 comprises the dual resolution design circuit 940 that can support normal resolution display mode and half-resolution display mode at least.Dual resolution design circuit 940 may be similar or be same as the dual resolution design circuit 300 of Fig. 3.This electronic installation may for, but be not subject to PDA(Personal Digital Assistant), mobile phone etc.Signal STVUO (Start Pulse Up Out) and signal STVBO (Start Pulse Bottom Out) can be used for the circuit function test.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (14)
1. a dual resolution design circuit is supported in the dual resolution design display mode in the display device, and this dual resolution design circuit comprises:
Shift register stage receives initial pulse and at least four clock signals, produces a plurality of middle attitude sweep signals;
The dual resolution design switch is controlled by the resolution model control signal, to switch the signal path of attitude sweep signal in those; And
Logic circuit stage receives attitude sweep signal in those that are switched by this shift register stage produced in those attitude sweep signal and by this dual resolution design switch, to produce a plurality of sweep signals, carries out the dual resolution design display mode.
2. dual resolution design circuit according to claim 1 also comprises:
Clock generator, receive first and second clock signal, be controlled by this resolution model control signal, and producing the first, second, third and the 4th clock signal according to first and second clock signal, this clock generator is exported this first, second, third and the 4th clock signal to this shift register stage.
3. dual resolution design circuit according to claim 2, wherein this dual resolution design display mode comprises normal resolution display mode and half-resolution display mode, when being in this normal resolution display mode, the 3rd clock signal is relevant to this first clock signal and the 4th clock signal is relevant to this second clock signal.
4. dual resolution design circuit according to claim 3, when wherein being in this half-resolution display mode, the 3rd clock signal is relevant to this second clock signal and the 4th clock signal is relevant to this first clock signal.
5. dual resolution design circuit according to claim 1, wherein this shift register stage comprises string a plurality of shift registers repeatedly, the mode of operation of those shift registers is controlled by those clock signals; And
Just sweeping under the pattern, the first order shift register of those shift registers receives this initial pulse, and the output signal of those shift registers is as attitude sweep signal in those, to input to this logic circuit stage; And
Sweep under the pattern counter, the afterbody shift register of those shift registers receives this initial pulse, and the output signal of those shift registers is as attitude sweep signal in those, to input to this logic circuit stage.
6. dual resolution design circuit according to claim 5 also comprises:
Just to sweep/the anti-switch of sweeping, receive and just to sweep control signal, anti-control signal and this initial pulse swept, this just sweeps/and the anti-switch of sweeping will conduct to another shift register from those strings signal that one of shift register exported that changes.
7. dual resolution design circuit according to claim 6, wherein this is just sweeping control signal for this counter inversion signal of sweeping control signal; And
Just sweeping under the pattern, this output signal of previous stage shift register is fed into the next stage shift register to treat as its input; Or
Sweep under the pattern contrary, this output signal of next stage shift register is fed into the previous stage shift register to treat as its input.
8. dual resolution design circuit according to claim 6, wherein this just sweep/the anti-switch of sweeping comprises repeatedly transmission gate group and second string transmission gate group that changes of first string; And
Just sweeping under the pattern, this first string repeatedly transmission gate group is this repeatedly then not conducting of transmission gate group of second string of conducting; Or
Sweep under the pattern contrary, this first string repeatedly transmission gate group is this repeatedly then conducting of transmission gate group of second string of not conducting.
9. dual resolution design circuit according to claim 1, wherein this dual resolution design switch comprises the 3rd transmission gate group and the 4th transmission gate group; And
Under the normal resolution display mode, the 3rd transmission gate group is conducting the 4th then not conducting of transmission gate group; Or
Under the half-resolution display mode, the 3rd transmission gate group is not conducting the 4th then conducting of transmission gate group.
10. dual resolution design circuit according to claim 1, wherein this logic circuit stage comprises a plurality of NAND doors, the attitude sweep signal is carried out logical operation in those that enable signal and this shift register are exported, to produce those sweep signals.
11. dual resolution design circuit according to claim 1, wherein this resolution model control signal comprises normal resolution mode signal and half-resolution mode signal.
12. dual resolution design circuit according to claim 1, wherein this display device is a display panels.
13. a display panel comprises:
The dual resolution design circuit is supported in the dual resolution design display mode in this display panel, and this dual resolution design circuit comprises:
Clock generator produces at least four clock signals;
Shift register stage receives initial pulse and this four clock signals, produces a plurality of middle attitude sweep signals;
Just sweep/the anti-switch of sweeping, receive and just sweeping control signal, anti-control signal and this initial pulse swept, to control just sweeping or counter sweeping of this display panel;
The dual resolution design switch is controlled by the resolution model control signal, to switch the signal path of attitude sweep signal in those; And
Logic circuit stage receives attitude sweep signal in those that are switched by this shift register stage produced in those attitude sweep signal and by this dual resolution design switch, to produce a plurality of sweep signals, carries out the dual resolution design display mode.
14. the electronic installation with display panel, this display panel comprises:
The dual resolution design circuit is supported in the dual resolution design display mode in this display panel, and this dual resolution design circuit comprises:
Clock generator produces at least four clock signals;
Shift register stage receives initial pulse and this four clock signals, produces a plurality of middle attitude sweep signals;
Just sweep/the anti-switch of sweeping, receive and just sweeping control signal, anti-control signal and this initial pulse swept, to control just sweeping or counter sweeping of this display panel;
The dual resolution design switch is controlled by the resolution model control signal, to switch the signal path of attitude sweep signal in those; And
Logic circuit stage receives attitude sweep signal in those that are switched by this shift register stage produced in those attitude sweep signal and by this dual resolution design switch, to produce a plurality of sweep signals, carries out the dual resolution design display mode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US67196505P | 2005-04-15 | 2005-04-15 | |
| US60/671,965 | 2005-04-15 | ||
| US11/386,339 | 2006-03-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1848236A true CN1848236A (en) | 2006-10-18 |
| CN100538813C CN100538813C (en) | 2009-09-09 |
Family
ID=37077777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100725995A Expired - Fee Related CN100538813C (en) | 2005-04-15 | 2006-04-13 | Circuit structure for dual resolution design reaches display panel and the electronic installation of using it |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100538813C (en) |
| TW (1) | TWI331740B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610185A (en) * | 2011-01-25 | 2012-07-25 | 群康科技(深圳)有限公司 | Display device compatible for double resolution display and driving method of the display device |
| CN104952425A (en) * | 2015-07-21 | 2015-09-30 | 京东方科技集团股份有限公司 | Display substrate, display device and display substrate resolution adjustment method |
| CN106157873A (en) * | 2016-08-31 | 2016-11-23 | 昆山工研院新型平板显示技术中心有限公司 | A kind of gate drive apparatus, driving method and display floater |
| WO2017020549A1 (en) * | 2015-08-06 | 2017-02-09 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display panel driving method, and display device |
| CN107591129A (en) * | 2017-09-04 | 2018-01-16 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit and display panel for diode displaying |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI694727B (en) | 2018-03-20 | 2020-05-21 | 台達電子工業股份有限公司 | Projection display apparatus and control method |
-
2006
- 2006-04-13 CN CNB2006100725995A patent/CN100538813C/en not_active Expired - Fee Related
- 2006-04-13 TW TW95113139A patent/TWI331740B/en not_active IP Right Cessation
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610185A (en) * | 2011-01-25 | 2012-07-25 | 群康科技(深圳)有限公司 | Display device compatible for double resolution display and driving method of the display device |
| CN102610185B (en) * | 2011-01-25 | 2015-12-02 | 群康科技(深圳)有限公司 | Support display device and its driving method of two resolution display |
| CN104952425A (en) * | 2015-07-21 | 2015-09-30 | 京东方科技集团股份有限公司 | Display substrate, display device and display substrate resolution adjustment method |
| WO2017012300A1 (en) * | 2015-07-21 | 2017-01-26 | 京东方科技集团股份有限公司 | Display substrate, display apparatus, and method for adjusting resolution of display substrate |
| US10079005B2 (en) | 2015-07-21 | 2018-09-18 | Boe Technology Group Co., Ltd. | Display substrate, display device and resolution adjustment method for display substrate |
| WO2017020549A1 (en) * | 2015-08-06 | 2017-02-09 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display panel driving method, and display device |
| US9747854B2 (en) | 2015-08-06 | 2017-08-29 | Boe Technology Group Co., Ltd. | Shift register, gate driving circuit, method for driving display panel and display device |
| CN106157873A (en) * | 2016-08-31 | 2016-11-23 | 昆山工研院新型平板显示技术中心有限公司 | A kind of gate drive apparatus, driving method and display floater |
| CN106157873B (en) * | 2016-08-31 | 2019-02-26 | 昆山工研院新型平板显示技术中心有限公司 | A kind of gate drive apparatus, driving method and display panel |
| CN107591129A (en) * | 2017-09-04 | 2018-01-16 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit and display panel for diode displaying |
| CN107591129B (en) * | 2017-09-04 | 2019-08-30 | 深圳市华星光电半导体显示技术有限公司 | Scan drive circuit and display panel for diode displaying |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100538813C (en) | 2009-09-09 |
| TWI331740B (en) | 2010-10-11 |
| TW200636652A (en) | 2006-10-16 |
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