JPH0557597B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal display device, and particularly to an active matrix type liquid crystal display device.

[Conventional technology]

In recent years, many attempts have been made to manufacture liquid crystal display devices using active matrix substrates in which a MOS transistor array is formed on a single crystal silicon substrate, or active matrix substrates in which a thin film MOS transistor array is formed on a transparent substrate. .

An active matrix liquid crystal display device has a gate line connected to a plurality of gate drive circuits, a data line connected to a plurality of data drive circuits orthogonal to the gate line, and a data line formed at each intersection of the gate line and the data line. The liquid crystal is interposed between an active matrix substrate made of MOS transistors and a transparent common electrode facing the active matrix substrate.

Conventionally, when the data line wiring is formed of a material with low resistivity such as aluminum or aluminum alloy, the time constant for charging and discharging the data line can be made small, so there is no need to provide a buffer amplifier in the data drive circuit. Ta.

An example is shown in FIG. In the same figure, 102
104 to 104 are gate lines, 105 to 107 are data lines, and 111 to 113 are pixels. 101 is an active matrix liquid crystal display device composed of gate lines, data lines, and a pixel array.

Further, 114 is a gate drive circuit, 121 to 12
5 is an analog switch; 126 is an input terminal for a video signal applied to the data line; 131 is a shift register that controls opening and closing of the analog switches 121 to 125;
125 and the shift register 131 constitute a data drive circuit.

Here, analog switches 121 to 125 and data lines 105 to 107 are connected to MOS transistors 3
The capacitance of the gate insulating film of 02 serves to sample and hold the video signal, and the time that one analog switch is conductive is at most
Limited to about 1μSec.

Figure 3 shows one pixel, 301 is a liquid crystal, 30
2 is a MOS transistor, 303 is a gate line, 3
04 is a data line. In an active matrix liquid crystal display device provided on a single-crystal silicon substrate, when the data line is formed with a P-type or N-type diffusion layer, the specific resistance of the data line becomes high, which causes problems when charging and discharging charges to the data line. The time constant becomes larger.

For this reason, if you try to drive a data line with a high specific resistance with a drive circuit like the one shown in Figure 1, the data line will not be completely charged or discharged within the conduction period of the analog switch (for example, 1 μ sec or less), and the image display will be interrupted. becomes extremely difficult.

Conventionally, in order to compensate for this drawback, a data drive circuit has been configured as shown in FIG. That is, a buffer amplifier (for example, a voltage follower) 24 is installed immediately after each analog switch 121 to 125.
Connect 1 to 245 and analog switch 121 to
125 and the parasitic capacitance of buffer amplifiers 241 to 245, sample and hold operations are performed, and data lines are driven via this buffer amplifier.

[Problem to be solved by the invention]

When the data drive circuit is configured as shown in Figure 2,
The same number of buffer amplifiers as the number of data lines are required, and the data drive circuit has a plurality of configurations, increasing the number of elements. Furthermore, since current always flows through the buffer amplifier, the power consumption of the data drive circuit increases. Since the main use of liquid crystal display devices is in low power consumption electronic equipment, the increase in the number of elements and power consumption of the drive circuit described above is a fatal drawback.

[Means to solve the problem]

An object of the present invention is to divide the video signal input to the data side drive circuit and efficiently utilize the buffer amplifier, thereby creating a data line with high specific resistance and a drive circuit with a small number of elements and low power consumption. The object of the present invention is to realize a drive circuit for an active matrix type liquid crystal display device that enables driving of an active matrix type liquid crystal display device and has excellent performance.

〔Example〕

Therefore, in the present invention, the video signal is divided and a material with high resistivity (P-type or N-type diffusion layer, ITO
By switching the input/output terminals of the buffer amplifier to drive data lines formed with transparent conductive film layers, silicon thin film layers, etc., with appropriate clock signals, the buffer amplifier is time-divisionally driven. The buffer amplifier drives multiple data lines.

Hereinafter, the present invention will be explained in detail based on Examples.

Fig. 4 shows an embodiment of the present invention, and Fig. 5 shows a fourth embodiment of the present invention.
An example of waveforms applied to each part of the drive circuit shown in the figure is shown. In FIG. 4, 401 to 406 are gate lines, 40
7 to 418 are materials with higher resistivity than aluminum (e.g., diffusion layer, transparent conductive film, silicon thin film, etc.)
419 to 423 are pixels having the structure shown in FIG. 3, 400 is the gate line,
An active matrix type liquid crystal display device consisting of the data line and the pixel array, 431 is a gate drive circuit. Further, 441 to 452 are analog switches, and 432 are analog switches 441 to 452.
Shift register for controlling opening/closing of 452, 434
~437 are buffer amplifiers, 481~484 are analog switches, and 433 is analog switch 4.
This is a shift register that controls opening and closing of 81 to 484, and these constitute a data drive circuit. FIG. 4 shows an example in which all data lines are driven by four buffer amplifiers in a data drive circuit.

Reference numerals 501 to 504 in FIG. 5 indicate output signals from output terminals 491 to 494 of the shift register 433, respectively. Further, 505 to 512 are respective output terminals 461 to 4 of the shift register 432.
68, the analog switch is conductive when the output signal is high, and the analog switch is nonconductive when the output signal is low.

The video signal input from the input terminal 438 is
During the period t ₁ to _{t 2} in FIG. 5, the analog switch 481
sampled by buffer amplifier 4
The input section 34 has the same potential as the input terminal 438. When the analog switch 481 opens at timing _t2 , the potential at the input of the buffer amplifier remains constant for a while due to the charge accumulated in the wiring capacitance between the analog switch 481 and the buffer amplifier 434. (SiO ₂ film, which is generally used for wiring insulation, has a sufficiently high resistance,
If the sampling period is as short as 100 nSec for several data lines, almost no leakage current will occur. ). The fact that parasitic capacitance occurs between the substrate and the wiring is shown, for example, in "Integrated Circuit <Design Principles and Manufacturing>, published by Kindai Kagakusha (May 10, 1962)," page 150. Therefore, the buffer amplifier 434 can continue to drive the data line 407 even during the period t ₁ to _{t 3} .

At t ₃ , the output signal 505 of the output terminal 461
becomes low, the analog switch 441 becomes non-conductive, the driving of the data line 407 by the buffer amplifier 434 is completed, and the video signal is transferred to the data line 407.
It is held by the parasitic capacitance of 07.

During the period t ₃ to _{t 4} , the analog switch 481 is turned on again.
conducts and samples the video signal.

The video signal sampled during the period t ₃ to t ₄ is sent to the analog switch 48 from the timing t ₄ .
1 and the wiring capacitance between the buffer amplifier 434, the potential at the input section of the buffer amplifier is kept constant for a while, and the analog switch 445 becomes conductive from _t3 to _t5 . data line 411 through buffer amplifier 434 during the period of
to drive.

By repeating the operations described above, the buffer amplifier 434 connects the data lines 407 to 411...
, the buffer amplifier 435 connects the data lines 408 to
412..., the buffer amplifier 436 connects the data lines 409 to 413..., the buffer amplifier 43
7 drives data lines 410 to 414, respectively.

4 and 5, the video signal is divided into a plurality of parts, one divided video signal is inputted to every fourth data line, and the second sample is determined based on the sampling time of the first sample hold means. Since the sampling time of the hold means is lengthened, it is possible to lengthen the sampling time of each video line by the maximum division. That is, while the conventional sampling time was from _t1 to _t2 , the present invention has a sampling time from _t1 to _t3 , which is four times longer than the conventional sampling time.

Generally, as the number of buffer amplifiers used increases, the time required to drive one data line increases, but the power consumption of the buffer amplifiers also increases.
Therefore, the most efficient use of buffer amplifiers can be achieved by appropriately determining the number of buffer amplifiers depending on the amount of time required to charge and discharge charges to one data line. , a high-performance drive circuit with low power consumption can be obtained.

Another embodiment of the invention is shown in FIGS. 6 and 7. The active matrix type liquid crystal display device and its driving circuit shown in FIG.
In place of the shift register 433, analog switches 601 to 604 of the same number as the number of data lines are used, and in place of the shift register 433, a shift register 600 having output terminals of the same number as the number of data lines is used.
It uses

In FIG. 6, the same symbols as in FIG. 4 represent the same things as in FIG. 4. At this time, each output terminal 621 to 626 of the shift register 600...
The output signals are respectively 701 to 706 in FIG.
..., and the output signals of each output terminal 461 to 466 of the shift register 432 are 707
〜712……set.

FIGS. 8 and 9a and 9b show configuration examples of buffer amplifiers. FIG. 8 shows a voltage follower constructed using an operational amplifier. In the figure, 801 is an operational amplifier, 802 is a voltage follower input terminal, and 803 is a voltage follower output terminal and a negative phase input terminal. The voltage follower shown in FIG. 8 can be used as a buffer amplifier with a gain of 1.

FIG. 9a shows an N-channel MOS transistor 90.
1 and a load resistor 902, and is a buffer amplifier with a gain of approximately 1. In the same figure, 903 is an input terminal, 906
is an output terminal, 904 is a positive power supply, and 905 is a negative power supply.

FIG. 9b shows a P-channel MOS transistor 91
1 and a load resistor 912, 913 is an input terminal, 916 is an output terminal, 914 is a positive power supply, and 915 is a negative power supply.

〔Effect of the invention〕

As described above, the present invention includes a first sampling means that sequentially samples a video signal inputted from a video signal input terminal, and a plurality of video signals divided by the first sampling means are inputted. N≦2) buffer amplifiers, signal lines connected to the output portions of each of the N buffer amplifiers, and video signals output from the buffer amplifiers to the signal lines; a second sampling means for sequentially supplying the sampled video signal to the data line, the data line is connected to the signal line every Nth line through a switch means, and the second sampling means Since the sampling period of is made longer than the sampling period of the first sampling means, it is possible to lengthen the writing and discharging time for each data line, and these are sufficiently performed to improve the horizontal resolution of the display device. be able to.

In addition, by appropriately determining the number of buffer amplifiers to be used depending on the amount of time required to charge and discharge charge to one data line, the most efficient use of buffer amplifiers can be achieved. I can,
A high-performance drive circuit with low power consumption can be obtained.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining a conventional active matrix liquid crystal display device and its driving circuit. FIG. 3 is a diagram showing the configuration of one pixel of an active matrix liquid crystal display device. FIG. 4 and FIG. 5 are diagrams for explaining an embodiment of the present invention. FIG. 6 and FIG. 7 are diagrams for explaining another embodiment of the present invention. FIG. 8 and FIG. 9 are diagrams for explaining a configuration example of a buffer amplifier.

Claims (1)

[Claims] 1. A pixel electrode arranged in a matrix on a substrate, a transistor connected to the pixel electrode,
In a liquid crystal display device having a data line connected to the transistor and sampling means for sequentially sampling a video signal and supplying the sampled video signal to the data line, the video signal input from the video signal input terminal is sequentially input. a first sampling means for sampling; N (N≧2) buffer amplifiers into which a plurality of video signals divided by the first sampling means are input; and each of the N buffer amplifiers. a signal line connected to the output section; and a second circuit that samples the video signal output from the buffer amplifier to the signal line and sequentially supplies the sampled video signal to the data line.
sampling means, the data line is connected to the signal line every N lines via a switch means, and the sampling period of the second sampling means is longer than the sampling period of the first sampling means. A liquid crystal display device characterized by its long length.