JPS61284117A - Sequential comparison type analog-digital converter - Google Patents

Abstract

PURPOSE:To quicken the A/D converting operation and output operation of an A/D conversion data by synchronizing the A/D converting operation and the output operation of an A/D conversion data with a serial clock or the like. CONSTITUTION:While conversion mode changeover signals AD/DA' are at H level, a reference voltage signal outputted from a D/A converter 1 is compared with an analog input signal ADI by a comparator circuit 2. An output signal of the circuit 2 is latched by an A/D conversion output latch circuit 3 is the timing of the trailing edge of an A/D conversion clock SCK' and fed to a D/A conversion input latch circuit 4, where a signal D0 among digital input signals D0-D7 to the converter 1. A series of operations are repeated, the signals D6-D0 are decided sequentially and the serial A/D conversion data ADO is outputted sequentially. On the other hand, when signals AD/DA' are at L level, a digital input signal DAI is latched sequentially by the circuit 4. Then the converting operation of the converter 1 is applied and a D/A conversion data DAO is outputted.

Description

TECHNICAL FIELD The present invention relates to a successive approximation type A/D converter, and more specifically to an A/D converter that operates in synchronization with an external device such as a microcomputer. be.

(b) Prior Art A successive approximation type A/D converter is known as one type of A/D converter. This type of A/D converter uses one comparison circuit to compare the analog input signal to be converted and the reference voltage signal, and then changes the reference voltage signal according to the comparison result and compares again. This operation is repeated, and in the process, the output signals of the comparator circuit are latched in sequence and outputted as parallel or serial A/D conversion data. The output signal of the latch circuit for obtaining the A/D conversion output is further connected to the D/A for generating the reference voltage signal.
The signals are sequentially latched from the upper bit side in synchronization with the A/D conversion clock in a latch circuit connected to the plurality of digital signal input terminals of the converter, and are supplied in parallel to the plurality of digital signal input terminals.

By the way, when such an A/D converter is used in synchronization with a microcomputer.

In order to make it possible to send and receive signals with a small number of signal lines, a method of coupling with a microcomputer via a serial interface is often used.

In this case, the structure of the successive approximation type A/D converter is, for example, to introduce an A/D conversion clock from the outside, perform A/D conversion, latch the A/D conversion data, and then serialize it. A device that outputs data in synchronization with a serial clock from an interface is known. With this configuration,
The serial interface can accept A/D converted data and transmit it to the microcomputer.

However, in such a configuration, the A/D conversion itself is not synchronized with the serial clock, so the conversion timing cannot be known from the outside, so the A/D converter must latch the A/D converted data. In addition to requiring many additional circuit elements such as latch circuits with the same number of bits as the A/D conversion data and means for outputting an A/D conversion end signal to the outside, the configuration becomes complicated. , There were also difficulties in speeding up the transfer of A/D conversion data. Furthermore, it is not practical to have to input two types of clock signals, an A/D conversion clock and a serial clock, to the A/D converter. Since a clock input terminal is required, the total number of terminals increases, which is disadvantageous in terms of cost, especially when realizing an A/D converter with a one-chip IC.

(c) Purpose The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an A/D device synchronized with a serial clock used in a serial interface.
It is possible to carry out conversion operations and output operations of A/D converted data, and to achieve higher speeds in these operations, and the circuit configuration is simple and requires fewer terminals, thereby reducing costs. Furthermore, it is an object of the present invention to provide a successive approximation type A/D converter that can operate with only one type of serial clock introduced from the outside. A converter, a comparison circuit that compares the output signal of this D/A converter and an analog input signal to be A/D converted, and a comparison circuit that compares the output signal of this comparison circuit with one of the external A/D conversion clocks. an A/D conversion output latch circuit that outputs serial A/D conversion data by sequentially latching it in synchronization with the edges of the D/A converter; /A conversion input latch circuit and the serial A/D conversion data outputted from the A/D conversion output latch circuit in synchronization with the other edge of the A/D conversion clock for the D/A conversion input. The present invention is characterized by comprising means for causing the latch circuit to latch sequentially.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a successive approximation type A/D converter according to an embodiment of the present invention.

As shown in the figure, this successive approximation type A/D converter includes a D/A converter 1 for generating a reference voltage signal, and a reference voltage signal from the second D/A converter 1 and an analog signal to be converted. A comparison circuit 2 that compares the magnitude with the input signal ADI, and an A/D converter that converts the output signal of this comparison circuit 2 into an A/D conversion start signal after inputting the A/D conversion start signal.
A 1-bit A/D conversion output latch circuit 3 that outputs serial A/D conversion data ADO by sequentially latching it in synchronization with one edge of the conversion clock;
Device D is connected to each of the eight digital signal input terminals of the converter 1 and is composed of an A/D conversion output latch circuit 3, which sequentially latches the converted data in synchronization with the other edge of the A/D conversion clock. , consisting of eight set/reset input terminal type flip-flops F9 to F16 that supply the corresponding digital input terminals of the D/A converter 1.
/A conversion input latch circuit 4 as a main component. In addition, in order to control the latch circuit 4 for D/A conversion input, the A/D'& conversion clock 8 is shifted.
A shift register 5 consisting of D-type flip-flops F1 to F8, gates 01 to G12 and an inverter II
, I2 are provided.

Here, assuming that the successive approximation type A/D converter of this embodiment transmits and receives signals to and from a microcomputer via a serial interface, the serial clock S from the serial interface is used as the A/D conversion clock.
CK shall be given. Also, A/
The D converter is assumed to have a D/A conversion function in addition to the A/D conversion function.

First, the A/D conversion operation will be explained with reference to the time chart shown in FIG. In addition, in Fig. 2, A D /
D A is a conversion mode switching signal for switching between A/D conversion mode and D/A conversion mode, ADS is a conversion start signal, and Q1 to Q16 are flip-flops F1 to FL.
6 outputs, 89 to S16 are flip-flops F9 to F.
16 each set input, CK16 is flip-flop F1
6 clock inputs are shown respectively.

When conversion mode switching signal AD/DA is at H level, this A/D converter is in A/D conversion mode. When the conversion start signal ADS becomes H level in this state, all of the flip-flops F1 to F16 in the shift register 5 and the D/A conversion input latch circuit 4 are reset. Next, when the conversion start signal ADS goes to the L level, only the flip-flop F9 in the D/A conversion input latch circuit 4 is set to the set state through the gate G1, and its output Q goes to the H level, and the A/D conversion This state is maintained until the clock (serial clock) SCK becomes L level. Here, the D/A conversion input latch circuit 4
The outputs Q of the flip-flops F9 to F16 are the digital input signals D7 to Do of the D/A converter l, respectively.
corresponds to Therefore, the digital input signals D7 to DO of the A/D converter in this case are rloooooooJ
becomes. However, digital input signals D7 to DO are
is the MSB and DO is the LSB.

In this state, the reference voltage signal output from the D/A converter 1 and the analog input signal ADI are compared in magnitude by the comparison circuit 2, and a signal that takes either H level or L level depending on the magnitude relationship is output. It is output from the comparator circuit 2. The output signal of the comparison circuit 2 is latched by the A/D conversion output latch circuit 3 at the timing of the first falling edge of the A/D conversion clock SC, and is output as the MSB of the A/D conversion data. , GIO, and GL2 to the D/A conversion input latch circuit 4. At this time, in the D/A conversion input latch circuit 4, the gate G
Only the flip-flop F9 is in the set state by the output of 1, and the latch pulse is input from the gate G2 to the clock input terminal (GK) of this flip-flop F9 at the timing of the first rising edge of the A/D conversion clock SC. is supplied, so the MSB of the A/D conversion data is eventually latched into the flip-flop F9 at the timing of the rising edge of the clock SCK. As a result, D/
Among the digital input signals DO to D7 of the A converter 1, D
7 (MSB) is finally determined.

Next, the reference voltage signal output from the D/A converter 1 and the analog input signal ADI are compared in magnitude by the comparison circuit 2,
The output signal is latched by the A/D conversion output latch circuit 3 at the timing of the falling edge of the A/D conversion clock SC, and is output as the second M5B of A/D conversion data. At the same time, the second M5 of this A/D conversion data
B is also supplied to the latch circuit 4 for D/A conversion input, and this time it is supplied to the flip-flop FIO which is in the set state via gate G2 at the timing of the next rising edge of the A/D conversion clock SCK. It is latched by a latch pulse from gate G3. As a result, among the digital input signals DO to D7 of the D/A converter 1, D6 is determined.

Hereinafter, in the same way, ■ comparing the analog input signal and the reference voltage signal in comparison circuit 2, and ■ performing the A/D conversion in synchronization with the falling edge of the A/D conversion clock.
The D conversion output latch circuit 3 latches serial A/D conversion data.

■ D/D in synchronization with the rising edge of the A/D conversion clock.
A series of operations in which the A conversion input latch circuit 4 latches the digital input signal to the D/A converter 1 are repeated, and finally 8-bit serial A/D conversion data AD
O is output sequentially from MSB.

On the other hand, when the conversion mode switching signal AD/DA becomes L level, this A/D converter enters the D/A conversion mode. This D/A conversion operation will be explained with reference to the time chart of FIG.

Now, in this D/A conversion mode, the conversion start signal A
When DS becomes L level, the digital input signal DAf to be D/A converted, which is serially input from MSB, is sequentially passed through the flip-flop F9 of the D/A conversion input latch circuit 4 in synchronization with the falling edge of the serial clock SCK. ~F16
latched to. Then, when the LSB of the digital input signal DAI is latched by the flip-flop F16, the conversion operation of the D/A converter 1 is performed, and the D/A converted data DAO is output.

As described above, in the successive approximation type A/D converter according to the present invention, A/D conversion operation and its A/D conversion operation are performed in synchronization with one type of external A/D conversion clock (for example, a serial clock from a serial interface). It is possible to perform both the output operation of /D conversion data, and thereby it is possible to exchange signals with an external device such as a microcomputer via a serial interface, for example.

In this case, since the external device side knows the A/D conversion timing from the conversion start signal and clock timing supplied to the A/D converter, the A/D converter side
Therefore, there is no need to temporarily hold all the converted data in a latch and output it in synchronization with the serial clock, and there is no need to output an A/D conversion end signal.

The circuit configuration of the A/D converter is simplified.

Furthermore, the fact that only one type of clock is required to be introduced into the A/D converter means that when the A/D converter is actually used in combination with a microcomputer, etc., it is only necessary to add an existing serial interface. It has the advantage of being easy to use. For example, some existing serial interfaces input and output data in synchronization with the rising edge of a serial clock, and output data in synchronization with the falling edge of a serial clock. According to the above embodiment, in the A/D conversion mode, the output signal of the comparison circuit is latched at the falling edge of the serial clock, and stable A/D conversion is performed at the rising edge of the serial clock, which is the input timing of the serial interface. Data can be output, and in the D/A conversion mode, the digital signal input is read at the falling edge of the serial clock, which is the output timing of the serial interface, making it easy to adapt to existing serial interfaces. can be adapted.

Furthermore, only one type of clock is required, and A/
Since it is not necessary to output a D conversion end signal, the number of terminals for transmitting and receiving signals between the A/D converter and an external device is reduced accordingly, which is advantageous when integrating the A/D converter into an IC. .

Note that the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention.

For example, in the above embodiment, the output signal of the comparison circuit 2, that is, the serial A/D conversion data, is synchronized with the falling edge of the A/D conversion clock (serial clock 5CK) introduced into the A/D converter. The A/D conversion data is latched by the A/D conversion output latch circuit 3, and the A/D conversion data from the A/D conversion output latch circuit 3 is latched in synchronization with the rising edge.
The latch circuit 4 for conversion input is used to latch the output signal, but conversely, the output signal of the comparator circuit 2 is latched in synchronization with the rising edge of the A/D conversion clock, and the output signal of the comparison circuit 2 is latched in synchronization with the falling edge of the A/D conversion clock. The A/D conversion data from the output latch circuit 3 may be latched; in short, these two
It is sufficient that the two latch timings are at different edges of the clock SCK.

Further, although the serial clock from the serial interface is used as the A/D conversion clock, the present invention is not limited to such a lock.

Furthermore, in the above embodiment, a D/A conversion function, that is, a function of converting an external digital signal input into an analog signal and outputting it, is added by using the D/A converter 1 for generating a reference voltage signal. However, it is of course possible to omit this function.

(e) Effects As described above, according to the present invention, both the A/D conversion and the output of A/D converted data can be performed in synchronization with the serial clock used in the serial interface. Therefore, not only can these two operations be made faster, but also the circuit configuration is simple because there is no need for a circuit to latch all bits of A/D conversion data at once or a circuit to output an A/D conversion end signal. By reducing the number of clocks, it is possible to reduce costs, and it is also possible to provide a successive approximation type A/D converter that can operate with only one type of clock introduced from the outside.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a successive approximation type A/D converter according to an embodiment of the present invention, and FIG. 2 is a block diagram of an A/D converter according to the same embodiment.
FIG. 3 is a time chart showing the operation in the D conversion mode, and FIG. 3 is a time chart showing the operation in the same <D/A conversion mode. ■...D/A converter, 2...Comparison circuit. 3... Latch circuit for A/D conversion output, 4...
...Latch circuit for D/A conversion input. 5...Shift register, F1~F8...D type flip-flop, F9~
F16...Set/reset terminal type flip-flop, 61~G12...Gate. It, I2...Inverter. Patent applicant: Rico Co., Ltd.

Claims (2)

[Claims] (1) A D/A converter, a comparison circuit that compares the output signal of this D/A converter with an analog input signal to be A/D converted, and an external A/D converter that converts the output signal of this comparison circuit into a /
A that outputs serial A/D converted data by sequentially latching it in synchronization with one edge of the D conversion clock.
/D conversion output latch circuit, and D/A each connected to a plurality of digital signal input terminals of the D/A converter.
The serial A/D conversion data output from the conversion input latch circuit and the A/D conversion output latch circuit is
/D conversion clock in synchronization with the other edge of the D/A conversion clock.
1. A successive approximation type A/D converter, comprising means for sequentially latching a conversion input latch circuit. (2) The successive approximation type A/D converter according to claim 1, wherein the A/D conversion clock is a serial clock from a serial interface.