JPS59223020A - Signal converting circuit - Google Patents

Abstract

PURPOSE:To obtain a necessary high-speed converter at a low cost by using in parallel plural low-speed general converters having a constant and limited processing time length in A/D and D/A signal converting circuits, and driving them by different time phases. CONSTITUTION:A timing generating circuit 10 operates the respective sample holding circuits 1, 4 and 7, and AD converting circuits 2, 5 and 8 by the second clock signal (b) whose phase is delayed by (1/3)T from the first clock signal (a) and also the third clock signal whose phase is delayed by (1/3)T, by which digital data D10, D11-, D20, D21-, and D30, D31- are outputted from the first AD converting circuit 2, the second AD converting circuit 5 and the third AD converting circuit 8, respectively. Subsequently, when the respective gate circuits 3, 6 and 9 are opened and closed by gate opening and closing signals (g), (h) and (i) which synchronize with said clock signals (a), (b) and (c) and open the gate circuits 3, 6 and 9 for (1/3)T time, and close them for (2/3)T time, and overall output (j) is obtained in an output line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal conversion circuit, and more particularly to increasing the speed of an AD conversion circuit that converts an analog signal into a digital signal and a DA conversion circuit that performs the inverse conversion.

Generally, AD conversion circuits and DA conversion circuits use the bandwidth of the signal to be converted (in the case of AD conversion) or the data transfer time (D
A conversion) determines the minimum time required for signal processing in the converter. Therefore, the wider the bandwidth or the faster the data transfer time, the more high-speed signal processing is required of the converter, but the higher the speed, the more complex and expensive the device becomes.

This invention was made in view of the problems of the conventional ones as described above, and it uses a plurality of low-speed general-purpose converters having a certain finite processing time length in parallel and drives them at different time phases. The object of the present invention is to provide a signal conversion circuit capable of performing required high-speed conversion.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an AD conversion circuit according to an embodiment of the first invention of the present application. In the figure, 1 is a first sample hold circuit as a signal holding circuit that holds the level of an input analog signal for a certain period of time, and 2 is this first sample hold circuit.
3 is a gate circuit for outputting the digital signal d from the first AD converting circuit 2 to the data line. and 4.
5.6, 7, and 8.9 are the same as 1. above, respectively. 2. a second sample-and-hold circuit having a processing capacity similar to that of No. 3;
A/D conversion circuit, a second gate circuit, a third sample hold circuit, a third (7) ADi conversion circuit, and a third gate circuit. Further, 20, 30, and 40 are the sample and hold circuits 1 and 4°7, and the AD conversion circuit 2, respectively. 5.
8. First to third unit circuits configured by mutually connecting gate circuits 3 and 6°9 in series, each unit circuit 20
, 30, and 40 people, and their outputs are connected in common. 1
0 is the sample hold circuit 1, 4.7 and AD conversion circuit 2. 5. Clock signal a driving 8.

b, c and gate opening/closing signals g, h synchronized with these.

This is a timing generation circuit that generates clock signals a, b, and c. The clock signals a, b, and c have the same clock period, and their time phases are shifted by 1/3 of the clock period.

Next, the operation will be explained.

In the configuration in which three sets of AD conversion unit circuits 20, 30, and 40 having the same processing time length are arranged in parallel as described above, the minimum time for conversion processing of one set of unit circuits is T, but the conversion timing and gate The opening/closing timing is determined by three sets of clock signals a and b whose time phases differ by (1/3)T from the basic clock.

By operating with C and gate opening/closing signals g, h, and i, the conversion processing time (1/3) T"?:'AD-converted data j is output.

This situation will be explained using FIG. 2. FIG. 2 is a timing diagram of each part.

The timing generation circuit 10 generates a first clock signal a shown in FIG. The third clock signal C(1/3)T phase delayed
(see figure (C)), each sample hold circuit 1
, 4, 7, by operating the AD conversion circuit 2°5.8, digital data (Dlo in the same figure (see dl)) is transmitted from the first AD conversion circuit 2.

Dll...2, digital data from the second AD conversion circuit 5 (see figure (e)) D20. D21. -..., digital data from the third AD conversion circuit 8 ((f) in the same figure)
Reference>D30. D31. ... is output. Next, in synchronization with the above clock signals a, b, and c, the gate circuit 3,
Gate opening/closing signals g and h that cause 6.9 to open for (1/3)T time and close for (2/3)T time.

If gate circuits 3, 6, and 9 are opened and closed according to i (see 01 in the same figure), a total output j (see 01 in the same figure) is obtained on the output line.

Although the above embodiment describes the operation of three sets of unit circuits, this is not limited to three sets; similarly, if N unit circuits are arranged side by side, N times faster operation can be expected. .

FIG. 3 is a block diagram of a DA conversion circuit according to an embodiment of the second invention of the present application. In the figure, the same reference numerals as in FIG. 1 indicate the same or equivalent parts. However, the first to third sample and hold circuits 1. 4. 7 is a digital sample and hold circuit such as a register that holds an input digital signal; 2", 5', and 8" are first to third circuits;
DA conversion circuit, 3. 6. Reference numeral 9 denotes first to third analog gate circuits, which here have high output impedance. 4 As can be seen from Fig. 4, the operation of this device is almost exactly the same as that of the device shown in Fig. 1, except that AD conversion is now DA conversion. It is possible to achieve three times higher speed operation than in the case of only one.

As described above, according to the signal conversion circuit according to the present invention, a plurality of low-speed general-purpose converters having a certain finite processing time length are used in parallel, and these are driven at different time phases, so that the required This has the effect of making it possible to obtain a high-speed converter at low cost.

[Brief explanation of drawings]

FIG. 1 is a block wiring diagram of a signal conversion circuit showing an embodiment of the first invention of the present application, FIG. 2 is a timing diagram showing waveforms of each part of the circuit of FIG. 1, and FIG. FIG. 4 is a block wiring diagram of a signal conversion circuit showing an embodiment of the invention of No. 2, and FIG. 4 is a timing diagram showing waveforms of various parts of the circuit of FIG. In the figure, 20 to 40 are unit circuits, ■, 4°7 is the first
or a third sample hold circuit (signal holding circuit),
2.5.8 is the first to third AD conversion circuit, 2', 5
', 8' are first to third ODA conversion circuits; 3. ．． 6
．． Reference numeral 9 represents first to third gate circuits, and reference numeral 10 represents a timing generation circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (1)

[Claims] (A signal holding circuit that holds the input signal amount of 11 sample points, an AD conversion circuit that AD converts the output signal of the signal holding circuit, and a gate circuit that opens and closes the output of the AD conversion circuit) It comprises N unit circuits connected in series and a timing generation circuit that generates a timing signal for driving each of the N unit circuits at a different time phase, and the input and output of each of the unit circuits is A signal conversion circuit characterized in that they are commonly connected. (2) A patent claim characterized in that the timing signals are N clock signals whose time phases are shifted by 1/N period of the clock period. The signal conversion circuit according to item 1. (3) A signal holding circuit that holds input data, a DA conversion circuit that converts output data of the signal holding circuit from DA to digital;
N unit circuits connected in series with gate circuits that open and close the output of the A conversion circuit, and a timing generation circuit that generates timing signals for driving each of the N unit circuits at different time phases. 1. A signal conversion circuit comprising: an input and an output of each of the unit circuits, wherein the inputs and outputs of each of the unit circuits are commonly connected. (4) The signal conversion circuit according to claim 3, wherein the timing signals are N clock signals whose time phases are shifted by 1/N period of the clock period.