JPS60189330A - Parallel-series converter - Google Patents

Abstract

PURPOSE:To execute a high-speed parallel-series conversion exceeding an operating speed by a parallel-series converting circuit whose operating speed is low, by distributing and inputting parallel information to plural converting circuits, and selecting and unifying a series information output from each converting circuit. CONSTITUTION:An oscillating clock 14 of an oscillating circuit 1 is frequency- divided 2, applied to a parallel-series converting circuit A3, and also a frequency- divided clock having a different phase is applied to a parallel-series converting circuit B4 through an invertor 7. As a result, a signal 17 and a signal 18 are sent to AND circuits 5, 6, respectively, from a circuit A3 which has converted parallel information A, C to series, and from a circuit B4 which has converted parallel information B, D to series, respectively. OR of its signals 19, 20 is taken by an OR circuit 8, and from the circuit 8, a series signal 21 of the parallel information A, C, B and D is outputted. In this way, by the parallel-series converting circuits 3, 4 whose operating speed is slow, the series information can be brought to a parallel-series conversion at a higher speed than the operating speed of these circuits 3, 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a parallel-serial conversion device that converts parallel information into serial information.

[Prior art] Conventionally, this type of converter that converts parallel information into serial information performs parallel-to-serial conversion using a clock signal that corresponds to the basic data time length of the serial information. When the clock signal is very short, that is, when the clock signal is short and high speed, the parallel-to-serial converter must also have a fast operation time, which has the disadvantage of being very expensive and consuming a large amount of power.

[Objective] The present invention has been made in view of the above-mentioned drawbacks of the prior art, and provides a parallel-to-serial conversion device capable of high-speed parallel-to-serial conversion of information using a low-speed parallel-to-serial converter. The purpose is to

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram of a parallel-to-serial converter circuit according to an embodiment of the present invention, and shows the case of 4-bit parallel information (m=4) and 2 parallel-to-serial converters (n=2). In Figure 1, 1 is an oscillation circuit that outputs the original oscillation clock signal 14, 2 is a frequency divider circuit that divides the original oscillation clock signal 14 outputted from the oscillation circuit by two, and 3 is a two-person parallel-to-serial conversion circuit A. , 4 is a parallel-to-serial conversion circuit B, which is also powered by two people, 5 and 6 are AND gates, 7 is a logic inversion gate, and 8 is an OR gate. Further, 10 to 3 are parallel information A-D, 15 is a frequency-divided clock A, and 16 is a frequency-divided clock signal B obtained by inverting the frequency-divided clock A15. 17 is a serial signal A from the parallel-to-serial conversion circuit A, 18 is a serial signal B from the parallel-to-serial conversion circuit B, and 19 is a serial signal A.
17 and the frequency-divided clock A15.
, 20 is a converted signal B obtained by taking the logical product of the serial signal B18 and the frequency-divided clock B16, and 21 is a serial information output obtained by taking the logical sum of the converted signal A and the converted signal B.

Next, the operation of the circuit diagram shown in FIG. 1 will be explained with reference to the timing chart I in FIG. 2.

In FIG. 1, IO-21 correspond to TIO-T21 (7) in FIG. 2, respectively.

Odd-numbered parallel information A, C (10, 12) is sent to parallel-to-serial conversion circuit A3, and even-numbered parallel information B is sent.

D (11, 13) is input to the parallel-to-serial converter circuit B4, and the parallel information A-D (10-13) is as shown in FIG. 2 (7) T10-T13c7), respectively.

An explanation will be given by taking the states of "'l", "1", and "O'" as an example.

The original clock signal 14 from the oscillation circuit l (T14 in Figure 2)
) is divided by two by the frequency divider circuit, and the divided clock A15 (T1
5), and the logical inversion gate 7 forms a divided clock B16 (T16) having a different phase. This frequency-divided clock A15 (T15) becomes a driving clock for the parallel-to-serial conversion circuit A3, and the parallel information A, C (10, 12) (T
IO, T12) is converted into a serial signal 17 (T17) in synchronization with the rise of the frequency-divided clock A15.

Similarly, the frequency-divided clock B16 (T16) becomes the drive clock for the parallel-to-serial converter circuit B4 and provides the parallel information B.

Depending on the state of D (11, 13), the serial signal B18 (T1
8).

As can be seen here, T17 replaces TIO, T12 with T1
8 connects Tll and T13 in parallel with 2-divided signals with different phases.
This is a serially converted signal. Since the serial signal A17 and the serial signal B18 have the same state twice the length of the actual serial information output 21, the serial signals A, B18 (1
7, 18), frequency-divided clock A15, and frequency-divided clock B16
are ANDed by the AND gates 5 and 6, and the output signals, the converted signal A19 (T19) and the converted signal B20 (T20), are logically summed by the OR gate 8, and the serial information output 21 (T21) can be obtained. This T21 signal is serial conversion information of parallel information A-D (TIO-T13).

As explained above, according to this embodiment, by providing two parallel to direct converter circuits, the operating speed of the parallel to direct converter circuit can be doubled.
Parallel-to-serial conversion is possible at twice the speed.

Also, although this parallel-to-direct conversion circuit was explained using two people,
Of course, the same applies even if it is done by two or more people.

Furthermore, in order to perform parallel-to-serial conversion at even higher speeds, the number (n) of parallel-to-serial conversion circuits may be increased and the frequency division by the frequency dividing circuit may be divided by n.

FIG. 3 shows an example in which there are three parallel-to-direct converter circuits (n=3).

Here, 22 is an oscillation circuit that oscillates the original clock 36 similar to the oscillation circuit l in FIG.
2 to 34 are the frequency-divided clocks a-C. 24-26
are parallel-to-direct conversion circuits a-c, 27 to 29 are AND gates,
30 is an OR gate.

Further, 31 is an m-bit parallel information input, and 35 is a serial information output.

The timing of the original clock 36 from the oscillation circuit 22 is T.
36, the frequency divided clock a32 from the frequency divider circuit 23
As the timing Ta2, the frequency-divided clock b3 is also used.
3 as T33 and the divided clock c34 as Ta2, their respective timing charts are shown in FIG.

This frequency-divided clock a-c (32-34) is given to the parallel-to-serial converter circuit a-c (24-26), and the parallel information 31 is obtained in the same way as in the case of n=2 shown in FIGS. 1 and 2. and serial information 3
Convert to 5 and output.

Here, the m-bit parallel information 31 is m = n, k
= 3k (k: natural number), and parallel information of m = nk bits is processed using n parallel-to-serial converter circuits and n frequency divider circuits. High-speed parallel-to-serial conversion becomes possible.

[Effects] As explained above, according to the present invention, it is possible to provide a parallel-to-serial conversion device capable of performing parallel-to-serial conversion at a very high speed exceeding the operating speed using an inexpensive parallel-to-serial converting means with a slow operating speed. .

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of one embodiment of the present invention, Fig. 2 is a timing chart of this embodiment, Fig. 3 is a circuit diagram of another embodiment of the invention, and Fig. 4 is a circuit diagram of another embodiment. 5 is a timing chart showing the output timing of the circuit. In the figure, 1, 22... Oscillation circuit, 2.23... Frequency dividing circuit, 3, 4.24-26... Parallel-DC conversion circuit, 10-
13.31... Parallel information input, 21.35... Serial information output. Patent applicant Canon Co., Ltd.

Claims (2)

[Claims] (1) comprising at least two converting means for converting parallel information into serial information, operating means for operating the converting means at different timings, and selection means for selecting one of the outputs of the converting means, A parallel-to-serial conversion device, characterized in that the parallel information is distributed and input to each of the conversion means, and the serial information output from each conversion means is integrated by the selection means. (2) The parallel-to-serial converter according to claim 1, wherein the operating means operates the converting means at a timing obtained by dividing the serial information output timing by the number of converting means.