JPH04185021A - System for multiplying signal by logic element - Google Patents

Abstract

PURPOSE:To generate a video signal about 100MHz for a display device of sufficiently high density by a circuit using a TTL element by easily generating the video signal whose band is twice as wide as that of a video signal generating circuit using a shift register until now. CONSTITUTION:It is noticed that serial data synchronized with a shift clock is obtained at the time of conversion from four-bit parallel data to serial data and serial data can be multiplied twice as wide as the clock at the time of expanding two-bit data in each cycle of the clock. Concretely, read-out data are so transposed that multiplied serial data D0 to D3 are correctly arranged, and parallel data in the order of D0, D2, D1, and D3 is obtained. This data is divided to high order two bits D0 and D2 and low order two bits D1 and D3, and each of them is converted to a serial signal. Thereafter, divides bits are logically converted in the order of on/off periods.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Stored in Memory Regarding information processing equipment that converts parallel signals obtained by reading character data etc. into serial signals and generates video signals for external display and printing, a shift for conventional shift registers that converts parallel signals into serial data. Using the clock, obtain a serial data video signal with a frequency twice that of the shift clock,
With the aim of increasing the cost performance of the entire information processing device, parallel bit data consisting of multiple bits is divided into multiple pieces, and the divided bit data is
The above parallel data is converted into serial data so that when the converted serial data of each divided unit is sequentially extracted from the beginning and rearranged into one serial data, it becomes a bit string obtained by converting the original parallel data into serial data. Swap some bit positions of the data and divide it into multiple pieces,
A parallel-to-serial conversion circuit converts each divided parallel data unit into serial data using a first clock (CLK1), and converts the converted serial data in divided units to serial data using the first clock (CLK1). , a synchronization circuit that synchronizes with a second clock (CLK2) having the same frequency and a slightly faster phase, and synchronizes the synchronized serial data in divided units with the first clock (CLK2) in the divided units. CLK1) and a third clock (CLK3) with the same frequency but a slightly slower phase, a signal ■ is generated, and a signal ■ which is logically ORed with the third clock (CLK3) and inverted is generated. Then, a logic circuit is provided to take the logical sum of the generated signal (2) and the signal (2), and the original parallel bit data is converted into the above-mentioned parallel bit data by the parallel-to-serial conversion circuit, the synchronization circuit, and the logic circuit. It is configured to convert into serial data multiplied to a frequency twice that of the clock (CLK1) of CLK1.

[Industrial Application Field] The present invention relates to an information processing device that converts a parallel signal obtained by reading character data etc. stored in a memory unit into a serial signal, generates a video signal, and displays or prints it externally. Regarding.

Usually, the display section and printer section of an information processing device are
Character data is stored in image memory (print memory), and the data is first read out as parallel data, converted to serial data, and then converted to serial video signal.
Display character data as bright spots on a display or dots on paper.

At this time, when converting parallel data to serial data, the band of the resulting video signal is determined by the clock used in the parallel-serial circuit.

If you try to use a high-density display device,
A high frequency clock is also required for the parallel-to-serial converter.

Therefore, using the conventional shift register clock,
A parallel-to-serial conversion method is required that can be displayed on the high-density display device.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram illustrating a conventional video signal generation system, and (a)
shows an example of the configuration, and (b) shows an operation time chart.

In the generation of a video signal using a conventional parallel-to-serial conversion circuit, a parallel-to-serial conversion circuit as shown in the figure converts a bit-by-bit parallel signal from parallel to serial to directly generate a video signal.

In the conventional parallel-to-serial conversion circuit, an n-bit shift register is usually used, and the shift clock determines the final video signal band.

In this conventional method, when the image data is output in units of 4 bits, a 4-bit shift register is used to convert 4 bits=+1 focus, and this signal is used as a video signal.

According to this method, the generation of video signals is simple, but
In order to use a high-density display device, it is necessary to increase the bandwidth of the video signal, and the shift clock used in the shift register also needs to have a high frequency.

FIG. 3(a) shows a conventional video signal generation circuit.

4-bit parallel data (Do~03) is read from a memory section (not shown), and the 4-bit shift register (SHIFT REG) 1 changes the data from 4 bits to 1.
A bit conversion is performed.

The obtained serial data is driven by a driver (DV) 4 and sent to a display device as a video signal.

At this time, the clock for the shift is 5HIFT CL.
K signal is given.

Figure (b) shows the video signal generated by the circuit in figure (a) above and the original 4-bit parallel data (D
0 to 03) is shown.

It is assumed that parallel data input to shift register 1 is shifted in the direction of D3 (DO) by shift register l.

Assume that data A is visible in DO, data B is visible in DI, data C is visible in D2, and data D is visible in D3. However, each data is 1-bit data of "1" or 0.

By the first shift clock, D3 bit data D
first appears outside the shift register and star, and D.

Bit data is shifted in the Dl direction, D1 bit data is shifted in the D2 direction, and D2 bit data is shifted in the D3 direction.

With the next shift clock, data C currently located at the D3 bit position appears. Below, in the same way, data 1
) = g + (< 13 → A becomes serial data.

In other words, one period of the shift clock corresponds to the width of one bit of data.

Therefore, when a high-density display device is used, the bandwidth of the video signal becomes higher and the frequency of the shift clock becomes higher accordingly.

According to such a conventional system, the frequency of the shift clock is directly equal to the band of the video signal.

For example, if you want to use a high-density display with a frame frequency of about 707, 1152 dots horizontally and 1700 lines vertically, the required video signal band is about 100 MHz, and the maximum operating frequency of the video signal in this band is about 8
A circuit using ECL or the like is required instead of TTL which is 0 MHz.

Generally, ECL circuits have different power supply voltages from TTL circuits.
Also, ECL devices are more expensive than TTL devices.

Therefore, the coexistence of TTL circuits and ECL circuits increases the cost of the device.

In view of the above conventional drawbacks, the present invention provides an information processing apparatus that converts a parallel signal obtained by reading character data etc. stored in a memory section into a serial signal, generates a video signal, and displays or prints it externally. The object of the present invention is to provide a circuit that can generate a video signal in a higher band within a range that can be driven by a conventional TTL circuit.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention.

The above problem can be solved by a signal multiplication method using logic elements configured as follows.

Divide parallel bit data consisting of multiple bits into multiple pieces, convert each of the divided bit data into serial data, and extract the converted serial data of each division unit sequentially from the beginning to create one serial data. The bit positions of some of the parallel data are swapped and divided into multiple pieces so that when rearranged into data, the original parallel data is converted into a serial bit string. A parallel-to-serial conversion circuit l converts the converted serial data in divided units into serial data using the first clock (CLK1), and a parallel-to-serial conversion circuit l that converts the converted serial data into serial data using the first clock (CLK1), which has the same frequency and a slightly faster phase. Synchronous circuit 2 that synchronizes with the second clock (CLK2)
Then, the synchronized serial data in divided units is transmitted to a third clock (CLK3) having the same frequency as the first clock (CLK1) and a slightly slower phase in the divided units.
The signal ■ which is ANDed with the third clock (CLK
Logic circuit 3 which generates an inverted signal ■ by performing a logical OR with 3), and calculates a logical OR between the generated signal ■ and the signal ■.
The original parallel bit data is converted into serial data in the division unit by the parallel-to-serial conversion circuit 1, and the synchronization circuit 2 converts the original parallel bit data into serial data by the second clock (CLK2).
), and the logic circuit 3 synchronizes with the first clock (
It is configured to convert into serial data multiplied to a frequency twice that of CLK1).

[Operation] When a conventional parallel-serial conversion circuit, a so-called shift register, converts, for example, 4-bit parallel data into serial data, serial data synchronized with the shift clock is obtained, but each cycle of the shift clock Focusing on the fact that by expanding 2-bit data, the serial data can be multiplied by twice the shift clock, in the present invention, the order of the serial data (Do-03) when multiplied is To line up correctly, first,
The second and third bits of the parallel data (DO-03) read from a memory (not shown) are exchanged. That is, Do, D2. It is assumed that the parallel data is in the order of Di and D3.

Then, the top 2 pits) (Do, 02) and the bottom 2
bits (Di, D3) and each is converted into a serial signal using the shift clock.

Then, since the first data Do and Dl and the next data D2 and D3 of each divided serial data are parallel, = 亥parallel data Do,
Di or D2. D3 is logically converted so that it enters the "on" period or "on" period of the shift clock.

With this configuration, serial data multiplied by twice the shift clock can be obtained.

Therefore, for example, in a circuit using a TTL element, for example,
A sufficiently high-density video signal for a display device in the vicinity of 100 MHz can be generated, and the cost performance of the entire device can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing the principle configuration of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, in which (a) shows an example of the configuration of a synchronous circuit, and (b) shows a logic diagram. An example of the circuit configuration is shown (
c) shows an operation time chart.

In the present invention, when parallel bit data consisting of a plurality of bits is divided into a plurality of pieces and each of the divided bit data is converted into serial data, the converted serial data is the same as each divided serial data. When extracted sequentially from the beginning and rearranged into one serial data, the bit positions of some of the above parallel data are swapped and divided into multiple groups so that the bit string is obtained by converting the original parallel data to serial data. , a parallel-to-serial conversion circuit 1 that converts each divided parallel data unit into serial data using a first clock (CIJ1);
A synchronization circuit 2 synchronizes the clock (CLK1) with a second clock (CLK2) having the same frequency and a slightly faster phase, and the synchronized serial data in divided units is synchronized in the divided units, The third clock (CLK1) has the same frequency as the first clock (CLK1) but has a slightly slower phase.
K3) and the signal ■ which is ANDed with the third clock (
A logic circuit (GATE) that performs a logical OR with CLK3) to generate an inverted signal ■, and performs a logical OR of the generated signal ■ and a signal ■.Means necessary for 3 to implement the present invention. It is.

Note that the same reference numerals indicate the same objects throughout the figures.

The signal multiplication method of the present invention will be explained below with reference to FIGS. 1 and 2.

First, in FIG. 1, 1 is a 4-bit shift register (SHIFT REG).

The parallel data is read out from the memory section (not shown) in 4 bits, but the shift register (St(
The output of IFT (REG) 1 is 2 bits of d out of the 4 bits of shift output.

In the present invention, this shift register (SHIFTR
EG) Part of the original parallel data DO to D3 is replaced as the parallel data input to EG1. Specifically, the second bit D1 and the third bit D2 of the 4-bit parallel data are exchanged.

That is, Do, 01, 02. The order of D3 is DO, D2, 0
It is assumed that the parallel data is in the order of 1.03.

Then, the upper 2 bits (Do, D2) and the lower 2 bits
Bits (01, 03) are each converted into a serial signal using the shift clock.

Then, since the first data DO and Dl and the next data D2 and D3 of each divided serial data are parallel, the parallel data 00.01
．． Or D2. By extracting D3, serializing each, and combining them into one, correct 1-serial conversion can be performed.

In the present invention, this serial conversion is performed using a logic circuit (GATE
) 3 to obtain serial data multiplied by the shift clock.

Therefore, the above shift register (SHIFT REG)
1, the divided parallel 2-bit node data is converted from 2 bits to 1 bits.

Reference numeral 2 in FIG. 1 is a synchronization circuit for synchronizing the 2-bit serial data obtained in this way with a clock. Further, 3 is a logic circuit (GATE) for converting the 2-bit data synchronized by the synchronization circuit 2 into final 1-bit data. And 4
is a driver for converting serialized 1-bit data into a video signal.

2(a) shows details of the synchronous circuit 2 of FIG. 1, and FIG. 2(b) shows details of the logic circuit (GATE) 3 of FIG. 1.

CLK2 in FIG. 2(a) is a shift register (S
HIFT REG) Clock for 1 rsHIFT C
For LKIJ (hereinafter simply referred to as CLKI),
These are signals with the same frequency but slightly faster phase, as shown in Figure 2 (b).
CLK3 is a signal with the same frequency and slightly slower phase than CLKI.

In the present invention, parallel data is transferred from the image memory to the shift register (SHIFT REG) at conventional timing.
When input to the shift register (SHIFT R
Serial data is output from EG) 1 at the timing shown at Ql and Q2 in the diagram (c).

However, for shift register (SHIFT REG) 1, load (Load) and shift (Sh
Load signal (LOA) such that i f t) is repeated
D) is input.

In this way, the outputs Q1 and Q2 of shift register 1
video data is output at twice the frequency of conventional circuits. That is, data C4A in the diagram (c).

It is like D→B.

When this signal is sampled by the synchronous circuit 2, the clock CLK2 of the synchronous circuit 2 is slightly faster than the clock CLKI of the shift register I, as described above, so the output of the synchronous circuit 2 is Qli in the diagram (c), It will be like Q2i.

The Q1i+12i signal obtained in this way is applied to the logic circuit (G
By inputting ATE) 3, video data as shown in the VIDEO signal in figure (c) can be obtained.

To explain specifically, the logic circuit (GA
TE) 3 AND circuit (A) 30, the above clock CLK3 and the above serial signal Q2i (D, B)
The shift clock CL is logically ANDed with the shift clock CL.
During the ON period of K3, the serial signal Q2i is output from the AND circuit (A) 30, and it can be seen from the video signal B in the time chart shown in FIG.

Further, in the logical sum circuit (OR) 31, the shift clock CLK3 and the serial signal Qli(^.

B), the signal becomes 0 during the "on" period of the shift clock CLK3, and the serial signal Qli(C, A ) is outputted from the logical sum circuit (OR) 31, and it can be seen that the video signals C and A of the time chart shown in FIG. 3(c) are obtained.

The output signal ■ of the AND circuit (A) 30 and the output signal ■ of the OR circuit (OR) 31 are input to the OR circuit (01?
) By ORing with 32, (c) VIDE in figure
Original shift clock CL, shown as O signal DCBA
A signal multiplied by twice the period of K1 can be obtained.

In this way, the conventional shift clock CLKI and the shift clock CLK2 . Using CLK3,
It is possible to generate a video signal with twice the bandwidth compared to a conventional video signal.

〔Effect of the invention〕

According to the present invention, it is possible to easily generate a video signal having twice the bandwidth as compared to a conventional video signal generation circuit using a shift register. Therefore, a circuit using a TTL element can generate a sufficiently high-density video signal for a display device in the vicinity of 100 MHz, which has the effect of increasing the cost performance of the entire device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the basic structure of the present invention. FIG. 2 is a diagram showing an embodiment of the present invention. FIG. 3 is a diagram explaining a conventional video signal generation method. It is. In the drawing, 1 is a shift register, and 2 is a synchronous circuit. 3 is a logic circuit (GATE). 30 is an AND circuit (A), 31.32 is an OR circuit (OR). 5HFT CLKI (or CLK1), CLK2.
CLK3 is a shift clock. ■ is the output signal of AND circuit (A) 30. ■ is the output signal of logical sum circuit (OR) 31. ■ is the output signal of logical sum circuit (OR) 32. are shown respectively. Figure 1 (a) (b) Diagrams showing one embodiment of the present invention Figure 2 (Part 1) Figure 2 (Part 2) Figure 3

Claims (1)

[Claims] Parallel bit data consisting of a plurality of bits is divided into a plurality of pieces, each of the divided bit data is converted into serial data, and the serial data of the converted divided units is extracted in order from the beginning. Then, when the parallel data is rearranged into one serial data, it becomes a bit string obtained by converting the original parallel data into serial data. A parallel-serial conversion circuit (which converts each unit into serial data using the first clock (CLK1)
1), and a synchronization circuit that synchronizes the converted divided serial data with a second clock (CLK2) having the same frequency as the first clock (CLK1) and a slightly faster phase (
2) The synchronized serial data in divided units is transmitted in divided units to a third clock (CLK3) that has the same frequency as the first clock (CLK1) but has a slightly slower phase.
and the signal ((1)) which is ANDed with the third clock (CLK3) and the inverted signal ((2)) which is ANDed with the third clock (CLK3).
The generated signal ((1)) and the signal ((
2)), the original parallel bit data is converted into serial data in the division unit by the parallel-to-serial conversion circuit (1), and the synchronization circuit (2), each is clocked by the second clock (
CLK2), and the logic circuit (3)
A signal multiplication method using a logic element, characterized in that the signal is converted into serial data multiplied to a frequency twice that of a clock (CLK1).