JPS6310914A - N-bit frequency division counter - Google Patents

Abstract

PURPOSE:To fetch an output of a counter and to decode a data without any problem and with less power consumption by constituting the titled counter by an m-bit asynchronous counter and an (n-m)-bit synchronous counter using the most significant digit output of the asynchronous counter as a clock input. CONSTITUTION:The titled counter consists of the m-bit asynchronous counter 4 and the (n-m)-bit synchronous counter 5 using the most significant digit output of the asynchronous counter 4 as the clock input. In an IC comprising a CMOS, the power consumption is increased proportional to the frequency of an input signal. Then the pre-stage counter operated by a signal having a high frequency is constituted by the asynchronous counter 4 with less power consumption and a signal subject to frequency division in the counter 4 to decrease the frequency is processed by the synchronous counter 5 of the post- stage having much power consumption. Thus, the entire power consumption is reduced, and since the frequency is divided by the synchronous counter 5 at the post-stage, the delay in the frequency division output is almost constant at the post-stage and the no sequential delay toward the number of stages is caused. Thus, even with many number of stages of the counters, there is no problem in decoding and fetching the count.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an n-bit divider counter useful for use in CMOS logic circuits.

2. Description of the Related Art Conventionally, it is often the case that a high-frequency clock is divided by a counter and the output of the counter is decoded to obtain an arbitrary clock signal, or the value of the counter at a certain point in time is taken into the launch.

As this frequency division counter, an asynchronous counter or a synchronous counter is used.

First, an example of a 4-bit asynchronous counter is shown and explained in FIG. As shown in Figure 4, the asynchronous counter has four D
It consists of FFs connected serially. one D
The FF operates by inputting the output of the DFF connected before it to the CK input terminal, so as shown in Figure 6, the output of the subsequent stage is sensitive to changes in the input clock signal. causing delays. The arrows in the garden indicate that the change represented by the start point of the arrow will lead to the change represented by the end point of the arrow.

Second, an example of a 4-pit synchronous counter is shown in FIG. 6 and will be described. As shown in Figure 6, the synchronous counter consists of 4 DFFs.
It consists of multiple gate circuits. The outputs of the four DFFs are decoded and supplied to the D input terminal of each DFF, and the clock signal of the four DFFs is supplied to the CK input terminal.When a clock pulse is obtained from the clock signal, the output of each DFF is Depending on the state of the D input terminal, 4 DFFs
Since both change at the same time, the outputs of the counters change at almost the same timing as shown in FIG.

Problems to be Solved by the Invention When the input clock has a high frequency and the number of stages of a frequency division counter is large, and an asynchronous counter is used as the frequency division counter, the following problems occur.

As shown in FIG. 8, if the output of an 8-pit asynchronous counter is obtained, as described above, the later the bits are, the later the change is with respect to the human clock. If an attempt is made to capture the counter value into the latch at point A, "1oQ0000o" will not be obtained and an incorrect value will be latched, as is clear from FIG.

◇6. ◇6. ◇7. Do the logical operation of Q8 and get 10,000.
Even if an attempt is made to obtain a signal that becomes "H" at "0oO", the signal shown in Figure 8 will be obtained and cannot be obtained.

This problem can be solved by configuring a frequency division counter with a synchronous counter, but a synchronous counter requires a high-frequency clock signal to be supplied to the CK terminal of all DFFs, consumes more power than an asynchronous counter, and is very inefficient. It's the economy.

SUMMARY OF THE INVENTION In view of these points, it is an object of the present invention to provide an n-bit frequency division counter that consumes less power and can read and decode a counter value without any problem.

Means for Solving the Problems The present invention is an n-bit counter comprising an m-bit asynchronous counter and a (n-m)-bit synchronous counter whose clock input is the most significant output of the asynchronous counter. It is a frequency division counter.

Further, the present invention is an n-bit frequency dividing counter that is composed of a plurality of synchronous counters, and uses the most significant output of the synchronous counter in the previous stage as a clock input of the synchronous counter in the subsequent stage.

It is known that in an IC configured with 0 MO3, power consumption increases in proportion to the frequency of an input signal. Therefore, by configuring the front-stage counter that operates on high-frequency signals as an asynchronous counter with low power consumption, and using the lower-frequency signal divided by this asynchronous counter to operate the subsequent stage synchronous counter that consumes more power. , the overall power consumption can be reduced, and since frequency division is performed by a synchronous counter in the subsequent stage, the delay in the divided output is almost constant in the subsequent stage, and there is no sequential delay according to the number of stages, and the delay is not delayed according to the number of stages of the counter. Even if there are many numbers, decoding and counter value import can be done without problems.

Example The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a motor speed control circuit to which the n-bit frequency division counter of the present invention is applied. 1 is a waveform shaping circuit that shapes the waveform of the input FG multiplied signal to obtain an FG pulse generated every FG cycle; 2 is a timing signal generation circuit that delays the FG pulse to generate a counter load signal and a latch latch signal. , 3 is an 8-pit frequency division counter of the present invention, 4 is 8
A 2-bit asynchronous counter that forms the front stage of the pit frequency division counter 3, 6 a 6-bit synchronous counter that forms the rear stage of the 8 pit frequency division counter, 6 a latch that latches the counter value, 7 a D/A converter, 8 is an amplifier, 9 is a compensation filter that stabilizes the control loop, 10 is a driver that drives the motor according to the supplied voltage, 11 is a motor, 1
Reference numeral 2 denotes an FG (frequency generator) that generates an FG multiplied signal having a frequency proportional to the number of rotations of the motor.

The operation of the motor speed control device configured as above will be explained below. In proportion to the rotation speed of the motor 11, FGl 2
, a <FG times signal as shown in FIG. 2A is generated and supplied to the waveform shaping circuit 1, and from the waveform shaping circuit 1 as shown in FIG.
A G pulse train is generated. The FG pulse train is supplied to the timing signal generator 2, and the timing signal generator 2,
Immediately after the FG pulse, the latch takes in the counter value,
Next, in order to load the counter, a latch pulse and a load pulse are generated as shown in FIG. 2C and D.

Then, the frequency division counter 3 counts using the clock signal as shown in FIG. The FG obtained by the latch 6 is obtained as a voltage by the same period D/A converter 7 and the amplifier 8, and is supplied to the driver 1o via the filter 9. If the load is constant, the motor 11 is driven at a constant speed.

When the load on the motor 11 increases and the rotation speed of the motor 11 decreases, the FG multiplication signal frequency decreases, and the F obtained at the latch 6 decreases.
G same period value increases. The FG same period value is converted to voltage,
Since the motor 11 is being driven, if the same period of FG increases,
The voltage driving motor 11 is increased and the speed of motor 11 is increased.

When the rotational speed of the motor 11 increases, a reverse operation is performed to reduce the speed of the motor 11 and control the speed to be constant.

Next, the operation of the frequency division counter 3 of the present invention will be explained with reference to the time chart of FIG. The frequency division counter 3 loads with the load pulse and counts the clock signal,
Outputs Q1-Q8 are obtained as shown in FIG. Output Q4.
Since Q2 and Q03 are the 11th-order delayed power ζQ3, the delay is almost constant because the frequency is divided by the synchronization counter 6, so the delay in the output of the branch station color/re3 is reduced. Then, the timing at which the output of the branch counter 3 is latched is determined by the clock signal, as shown in FIG. 3, td=t4. By latching at a delayed timing, the output of the frequency division counter 3 can be latched without error.

Therefore, the period of the FG pulse can be obtained without error, and the speed of the motor can be controlled stably.

In this example, n=8. Although the frequency dividing counter was configured with m=2, m may be any positive integer, and (n −
It is also possible to divide the m)-bit synchronous counter into two or more blocks, use the output of the previous block as a clock for the subsequent block, and connect a plurality of synchronous counters asynchronously. Furthermore, if a slight increase in power consumption is acceptable, the m bits in the first stage may also be configured as synchronous counters, and the overall configuration may be such that a plurality of synchronous counters are connected asynchronously.

As described in detail, according to the present invention, the power consumption is low, and the output of the counter can be taken in and decoded without any problem.
Its practical effects are great.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a motor speed control circuit according to an embodiment of the present invention, Fig. 2 is an operation time chart of the embodiment, and Fig. 3 is a time chart explaining the present invention of the embodiment. Figure 4 is a circuit diagram of an asynchronous counter, Figure 5 is an operation time chart of an asynchronous counter, Figure 6 is a circuit diagram of a synchronous counter, Figure 7 is an operation time chart of a synchronous counter, and Figure 8 is a problem with an asynchronous counter. It is a time chart explaining. 3... Frequency division counter, 4... Asynchronous counter, 5... Synchronous counter. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 Figure 5 Figure 6

Claims (3)

[Claims] (1) An n-bit frequency division counter comprising an m-bit asynchronous counter and an (n-m)-bit synchronous counter whose clock input is the most significant output of the asynchronous counter. (2) The (n-m) bit synchronous counter is composed of multiple synchronous counters, and the highest output of the previous stage synchronous counter is
2. The n-bit frequency dividing counter according to claim 1, which is used as a clock input of a subsequent stage synchronous counter. (3) An n-bit frequency division counter comprising a plurality of synchronous counters, and characterized in that the most significant output of the synchronous counter in the previous stage is used as the clock input of the synchronous counter in the subsequent stage.