JP2703967B2 - System clock divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a system clock frequency dividing circuit suitable for application to a digital processing circuit that performs high-speed processing.

(Prior Art) In recent years, microcomputers have been actively introduced in various fields. In order to improve the performance of the system, increase the functionality, reduce the size, and increase the noise resistance margin,
Multiple microcomputers and custom LSIs (hereinafter ASI
C), the entire system must be composed of digital circuits.

High-speed timing clocks are required to replace high-speed processing previously performed by analog circuits with digital circuits, and to facilitate data transmission between microcomputers and ASICs that operate asynchronously. . Generally, a digital circuit must operate in synchronization with a clock having an appropriate timing. Therefore, a low-frequency timing clock is required for a portion having a low processing speed such as a portion for performing a complicated process. For this reason, a high-frequency system clock, for example, a system clock of several tens of MHz is frequency-divided by a frequency dividing circuit,
It is necessary to create an appropriate timing clock having a lower frequency and to configure the circuit so that digital processing is performed in synchronization with the timing clock. Since the timing of the divided clock, which is the output of the dividing circuit, must be accurate, a synchronous counter is used for dividing the system clock as shown in FIG.

The synchronous counter in FIG. 4 is a synchronous 1/2 frequency dividing counter 2 composed of n stages of synchronous binary counters 2A, 2B, 2C... 2X.
And a carry signal detection circuit 4. The synchronous 1/2 frequency dividing counter 2 has two binary counters 2A and 2
B, 2C by entering the system clock 1 ...... 2X, the binary counter from the 1 / 2,1 / 4,1 / 8 ...... based on the frequency of the system clock 1, min 1/2 ⁿ Circumference clock
.., 2x, and digital processing of a system (not shown) is performed in synchronization with these clocks. Output divider clock 2 of 1/2 divider counter 2
Carry signals (carry signals) 4a, 4b, 4c,... are detected by carry signal detection circuit 4 based on a, 2b, 2c,.
Are input as carry input signals to the binary counters 2B, 2C, 2D,.

FIGS. 5 and 6 show different internal circuit configuration examples of the individual binary counters constituting the 1/2 frequency dividing counter 2 in the system clock frequency dividing circuit of FIG. FIG. 7 shows a configuration example.

The binary counter shown in FIG. 5 includes a DQ flip-flop 5, an exclusive OR NOT circuit (hereinafter, referred to as MATCH) 1
7, and an inverter 18. The system clock 1 is input to the clock input terminal CK of the flip-flop 5, the output signal of the MATCH 17 is input to the data input terminal D, the Q output is input to one input terminal of the MATCH 17 via the inverter 18, and the other The carry signal CRY from the carry signal detection circuit 4 is input to the input terminal.
The output of the inverter 18 outputs 1/2 frequency-divided clocks 2a, 2b, 2c...

The 1/2 frequency dividing counter in FIG. 6 comprises a DQ flip-flop 5 and a MATCH17. The system clock 1 is input to the clock input terminal CK of the flip-flop 5, the output signal of the MATCH 17 is input to the data input terminal D, and the QN output (negation of the Q output) and the carry signal CRY from the carry signal detection circuit 4 match the MATCH 17. Is input to The QN output of the flip-flop 5 is the output 1/2 of the frequency division counter 2
The divided clocks 2a, 2b, 2c...

The carry signal detection circuit 4 shown in FIG. 7 comprises a plurality of AND circuits 4B, 4C, 4D,... Having different numbers of inputs. The number of these AND circuits may be two less than the number of stages of the frequency division counter 2. The first carry signal 4a is formed by the first-stage frequency-divided clock 2a, and the second carry signal 4a
4b is formed by a first AND circuit 4B which receives as input the first and second divided clocks 2a, 2b, and the third carry signal 4c is formed by the first to third divided clocks 2a, 2b, 2c. The fourth and fifth carry signals 4c, 4d,... Are similarly formed by AND circuits 4D, 4E,. It is formed.

As described above, the synchronous counter constituting the conventional system clock dividing circuit is composed of n
The system clock 1 is input to each of the binary counters 2A, 2B, 2C... 2X of the stage, and the carry signal of the binary counter of a certain stage is divided as the count enable signal of the binary counter of the next stage to divide the system clock. When n binary counters are used, a clock with a frequency divided by 1/2 ⁿ from a high frequency to a low frequency can be obtained. Moreover, the timing error is caused by the DQ flip-flop 5
, And it is possible to obtain a very accurate timing. For example, the timing error of the frequency-divided clock when the above counter is used inside the ASIC is about 3 to 4 ns (nanosecond).

(Problems to be Solved by the Invention) The upper limit of the system clock frequency that can be input to the system clock frequency dividing circuit is 2
MATCH 17 via the divided clocks 2a to 2x output from the binary counter, the output carry signals 4a to 4w of the carry signal detection circuit 4, and the CRY (carry) input of the upper binary counter.
Is determined by the delay time before reaching the output side. Generally, the delay time of an AND circuit increases in proportion to the number of inputs. For this reason, the delay time of the path of the system clock → the output of the lowest binary counter → the carry signal to the highest → the output of the MATCH17 has resulted in the determination of the upper limit of the system clock frequency.

To configure the entire system with digital circuits,
Various timing clocks from high frequency to low frequency are required, so that, for example, 1/32 or 64
A clock such as one-half frequency division is required. In such a case, there is an inconvenience that the system clock frequency is limited by the delay time from the lowest binary counter to the carry input of the highest binary counter, and high-speed processing of the system cannot be realized.

The present invention has been made in order to eliminate such inconvenience, and an object of the present invention is to provide a high-speed operation type system lock frequency dividing circuit which is not affected by carry delay.

[Configuration of the invention]

(Means for Solving the Problems) In order to achieve the above object, a system clock frequency dividing circuit according to the present invention comprises: a 1/2 frequency divider comprising a plurality of stages of synchronous binary counters to which a system clock is input as a clock signal. A counter, a preceding carry signal detecting circuit for supplying a preceding carry signal which is enabled in a state before one count of the 1/2 frequency dividing counter, a preceding carry signal from the preceding carry signal detecting circuit, and a next clock And a register for giving a carry signal to the next higher binary counter so that the synchronous binary counters of a plurality of stages output a frequency-divided clock that is successively halved from lower to higher. It was done.

(Operation) In the system clock frequency dividing circuit having the above configuration, a carry signal one counter before a normal carry signal, that is, a preceding carry signal which is a carry signal having a timing earlier by one count is generated, and the preceding carry signal is generated by a register for one count. By delaying, a carry signal having the same timing as the original one is obtained. However, considering the delay from the system clock to the carry signal, the delay is only for the register. In this way, a synchronous counter that is not affected by the carry delay can be configured, and a high-speed digital processing circuit capable of high-speed processing can be configured as a suitable system clock frequency dividing circuit.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 shows an embodiment of a system clock frequency dividing circuit constructed according to the present invention. In the system clock frequency dividing circuit shown in FIG.
A preceding carry signal detecting circuit 3 is provided on the output side of the 1/2 frequency dividing counter 2 composed of A, 2B, 2C..., 2X, and the leading carry signal among the output divided clocks 3a, 3b, 3c. 3b, 3c,
3d is replaced with multi-stage DQ flip-flops 5B, 5C, 5D
.., 5w are delayed by one count to obtain signals 5b, 5c, 5d,.
Is provided to the binary counter as a carry signal. With this configuration, the carry signals 4b, 4c, 4d in FIG.
.., And carry signals 3b, 3c, 3d, which are carry signals at a timing one count earlier than
By delaying this by one count by the register 5, carry signals 5b, 5c, 5d,... Having the same timing as the carry signals 4b, 4c, 4d,. However, considering the delay from the system clock to the carry signal, the processing circuit of FIG. 1 is only a delay of the DQ flip-flops 5B to 5W constituting the register 5.

FIG. 2 shows the internal circuit configuration of the preceding carry signal detection circuit 3. 2 is composed of AND circuits 3B, 3C, 3D, 3E, 3F having 2, 3, 4, 5, and 6 inputs and one inverter 19. A first input terminal of each of the AND circuits 3B to 3F is commonly input with a first binary clock 2a inverted by an inverter 19, and the AND circuit 3B additionally receives a second frequency-divided clock 2b. The third and fourth frequency-divided clocks 2c, 2d,.
Is entered. The first divided clock 2a is the first
, And the second, third,... Preceding carry signals 3b, 3c, 3d,... Are output from the AND circuits 3B, 3C, 3D,.

FIG. 3 shows an application example of the system clock frequency dividing circuit of the present invention.

FIG. 3 shows an internal block of the ASIC for controlling an induction motor. An output pulse of a pulse generator (not shown) is counted as a clock 13 by a mechanical angle output counter 8 to obtain a mechanical angle 8a corresponding to the rotation angle of the electric motor. The multiplication circuit 9 is also supplied with pole pair number data 12a representing the motor pole pair number P, which is provided from the host microcomputer via the data access means 12, where the mechanical angle 8a is multiplied by P and the electrical angle 9a is output as the output. Is output. The upper microcomputer and the data access means 12 are connected by a data bus 15. 14 is a data bus control signal. The data access means 12 distributes data from the host microcomputer to each block. The slip frequency / slip angle data 12b from the data access means 12 is converted to a slip angle 11a by the slip frequency integration means 11,
The electrical angle 9a and the slip angle 11a are added by the adding circuit 10, and the electrical angle / slip angle addition data 10a is formed. The electrical angle / slip angle addition data 10a and the data access means 12
Is added to the electrical angle / slip angle / torque angle data 16 by the addition circuit 22. From the final output timing generating means 19 based on the addition data 16, the electric angle / slip angle / torque angle addition data
20 is output, and timing means 21 necessary for transfer to another ASIC or microcomputer is output.

The function of this ASIC is to detect an electric angle from an output pulse of a pulse generator, add a slip angle obtained by integrating a slip frequency given from a host microcomputer, and detect a motor magnetic flux position. By using a digital circuit instead of a conventional analog circuit or control device that has been processed by a microcomputer,
It is possible to realize with ASIC, space saving is achieved, noise resistance is improved, thereby reducing the burden on the upper microcomputer, and high performance and multi-functionalization of the whole system can be achieved. it can.

In the ASIC described above, on the one hand, the timing means of the counter 8 and the data access means 12 is set to 8 MHz or more,
Further, a part of the final output timing generation means 19 needs to be set to 16 MHz or more, and on the other hand, the slip frequency integration means 11
Timing means such as the multiplication circuit 9 and the addition circuits 10 and 22
The frequency must be as low as 00 KHz. In this case, in the present invention, the system clock of the ASIC is set to 32 MHz.
If this is divided by a 6-stage synchronous counter,
By one of the frequency division of 2 ⁶ minutes can be obtained clock of 500 KHz.

In this state, the conventional synchronous counter causes the system clock frequency dividing circuit to pass a 5-input AND circuit from the highest 16 MHz timing clock to the highest carry signal, and the delay time is 5 ns. It was about. Therefore, when the delay time of the DQ flip-flop and the MATCH is added, the clock cycle exceeds 32 MHz, and the system clock frequency has to be reduced. However, by using the synchronous counter based on the preceding carry shown in FIG. 1, the delay time of the AND circuit constituting the carry detection circuit can be ignored. For this reason, the ASIC of the present invention can be driven by a system clock of, for example, 32 MHz, and performance that sufficiently satisfies the design specifications can be exhibited.

〔The invention's effect〕

According to the system clock frequency dividing circuit using the synchronous counter using the preceding carry according to the present invention, a multi-stage system clock frequency dividing circuit is configured without considering the carry delay time which has conventionally limited the speeding up of the system clock. Thus, all of the high-speed processing part to the low-speed processing part can be constituted by digital circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a connection diagram showing an internal configuration of a preceding carry signal detecting circuit in FIG. 1, and FIG. 3 is an application of a system clock frequency dividing circuit according to the present invention. FIG. 4 is a block diagram showing a conventional system clock frequency dividing circuit, and FIGS. 5 and 6 each show a frequency dividing counter of the frequency dividing circuit shown in FIG.
FIG. 7 is a block diagram showing the internal configuration of a binary counter, and FIG.
FIG. 4 is a connection diagram illustrating an internal configuration of the carry signal detection circuit in FIG. 2: Synchronous 1/2 frequency dividing counter, 2A to 2X: Binary counter, 3: Advance carry signal detection circuit, 3B to 3F: Logical product (AND) circuit, 5: Register, 5B to 5W ... DQ flip-flops, 19 ... inverters.

Claims (1)

(57) [Claims] 1. A 1/2 frequency dividing counter comprising a plurality of stages of synchronous binary counters to which a system clock is input as a clock signal, and a preceding frequency which is enabled one count before the 1/2 frequency dividing counter. A preceding carry signal detecting circuit for supplying a carry signal; and a register for holding the preceding carry signal from the preceding carry signal detecting circuit and supplying the carry signal to the next higher binary counter at the next clock. A system clock divider circuit wherein the synchronous binary counter outputs a divided clock that is successively halved from lower to higher.