JP3121397B2 - Synchronous timing generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention is synchronous timing generating circuits
In respect, in particular, it outputs a synchronization clock signal of a plurality of frequencies to be synchronized with the reference clock signal in response to correct the phase shift of the reference clock signal outputted from the CPU to various peripherals to the processing speed of the various peripheral devices about the synchronization timing generation circuits.

[0002]

2. Description of the Related Art Recently, with the development of semiconductor technology, ICs have been developed.
(Integrated Circuit) has rapidly advanced in integration, speed, and functionality, and has been developing a wide variety of LSI (Large Scale).
Integrated circuits (ICs) have been developed according to the user's application, and ASICs (Application S-pecific Integrated C
ircuit).

In such an ASIC, various peripheral circuits (peripheral devices) such as a ROM, a RAM memory, a timer, etc., which are connected around the CPU as a core in the ASIC, include a CP in the ASIC.
The operating speed is often different from the operating speed of U.
Assuming that a clock signal for controlling the operation timing in U is a reference clock, the clock signal for controlling the operation timing of various peripheral circuits is supplied in a state where the reference clock signal is changed in speed according to the operation speed of various peripheral circuits. , C
The operation of the PU and the operation of various peripheral circuits are synchronized.

[0004]

However, in such an ASIC in which a conventional CPU and various peripheral circuits are integrated, there is a difference in path length and voltage fluctuation between the CPU and various peripheral circuits. Therefore, a phase shift occurs in the clock signal supplied to various peripheral circuits based on the reference clock signal in the CPU, so that the operation of the CPU and the operation of the various peripheral circuits cannot be synchronized, and the ASIC is designed as designed. There was a problem that performance could not be obtained. The problem of the occurrence of the synchronization deviation of the clock signal is particularly caused by the ASIC that performs high-speed processing.
Is remarkable.

Also, when the reference clock signal from the CPU is supplied to the peripheral circuit with a delay, the RAM is delayed from the output timing of the chip select signal for selecting the peripheral circuit as compared with the fetch or data output timing from the CPU. And the inability to access the ROM. For example, as shown in FIG. 7, when the phase shift of the clock signal between the emulator 1 and the target 2 is viewed, the clock signal 2 / 1CK (original oscillation) output from the oscillator (OSC) 3 in the target 2 includes: Clock signal 1 output via flip-flop (F / F) 4
/ 1CK (1/2 original oscillation) and a clock signal 1 / 1CK are transmitted via a buffer 5 in the emulator 1 to the CPU (Centra
l The clock signal 1 / 2CK (1/4 original frequency) output to the target 2 by being input to the Processing Unit 6 is input to the timing generator 7 in the target 2 as shown in FIG. , Clock signal 2 /
The clock signal 1 / 2CK supplied from the CPU 6 with respect to 1CK and the clock signal 1 / 1CK has a phase delay due to a path length between the CPU 6 and the timing generator 7, a voltage fluctuation, and the like. Signal 1
In a peripheral device whose operation timing is controlled by a strobe signal (STROBE) output from the timing generator 7 synchronized with the / 2CK, the operation timing is controlled by the other synchronized clock signals 2 / 1CK and 1 / 1CK. Synchronization with the peripheral device cannot be established, and the above-described problem occurs. The CS signal output from the timing generator 7 is a chip select signal for selecting a peripheral device.

[0006] The present invention provides a synchronous timing generation circuits for outputting a synchronizing clock signal in accordance with the processing speed of the various peripheral circuits to correct the phase deviation of the reference clock signal output from the CPU to the various peripheral circuits The purpose is to:

[0007]

According to the first aspect of the present invention,
A reference output from the system controller, which is connected between the system controller and various peripherals of various peripherals which operate in synchronization with a reference clock signal output from a system controller such as a CPU and have different processing speeds. A synchronous timing generation circuit for correcting a phase shift of a clock signal and outputting a synchronous clock signal synchronized with a reference clock signal according to a processing speed of each peripheral device, wherein a reference clock signal input from the system control device is provided. And a phase difference detection circuit that detects a phase difference between the correction clock signal input from the counter circuit and outputs a predetermined phase difference signal.
A voltage output circuit that outputs a predetermined DC voltage signal corresponding to the phase difference signal output from the phase difference detection circuit, and a voltage controlled oscillation that outputs an oscillation signal having a frequency corresponding to the DC voltage signal output from the voltage output circuit A correction clock signal for correcting the phase difference by counting up and down according to the oscillation signal output from the voltage controlled oscillation circuit to the phase difference detection circuit, and the frequency of the oscillation signal is equal to the frequency of the reference clock signal. when matched with a counter circuit for outputting a synchronizing clock signal of a plurality of frequencies corresponding to the processing speed of the various peripheral devices each synchronized with the reference clock signal, Cow
Based on the synchronous clock signal output from the
Output multiple shift clock signals with different phases
And the various peripheral devices operate.
Out of the shift clock circuit during the reset period
Corresponding to multiple input shift clock signals
A plurality of shift clock signals are generated by a clock selection signal.
It is characterized by comprising a gate circuit for outputting alternatively selected to.

[0008]

According to the first aspect of the present invention, a phase shift of a reference clock signal output from the system control device is connected between the system control device and various peripheral devices to correct the processing speed of each peripheral device. A synchronous clock signal synchronized with the reference clock signal, and detects a phase difference between the reference clock signal input from the system controller and the correction clock signal input from the counter circuit, and , A voltage output circuit that outputs a predetermined DC voltage signal corresponding to the phase difference signal output from the phase difference detection circuit, and a DC voltage signal output from the voltage output circuit A voltage-controlled oscillation circuit that outputs an oscillation signal having a frequency corresponding to the frequency, and a phase that counts up and down according to the oscillation signal output from the voltage oscillation circuit. Output to the phase difference detection circuit, and when the frequency of the oscillation signal matches the frequency of the reference clock signal, a plurality of clocks corresponding to the processing speed of each of the various peripheral devices synchronized with the reference clock signal are output. a counter circuit for outputting a synchronizing clock signal having a frequency, a synchronous clock signal output from the counter circuit
Multiple shift clocks with different phases as reference
A shift clock circuit for outputting a signal;
Shift clock during the reset period when the device is not operating
Multiple shift clock signals output from the circuit
The plurality of shift clocks are
A gate circuit which alternatively selects and outputs a click signal, is provided, a phase shift of the reference clock signal outputted from the system control unit is corrected, a plurality of shift clock signal synchronized with the reference clock signal Is supplied to various peripheral devices.

[0009]

[0010]

Therefore, a shift clock signal synchronized with the reference clock signal can be supplied to various peripheral devices by correcting a phase shift of the reference clock signal output from the system control device. Even when separated, the operation timing can be reliably synchronized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments. FIG. 1 is a diagram showing an embodiment of an emulation device to which a synchronization timing generation circuit serving as a reference of the present invention is applied. FIG. 1 is a block diagram of an emulation device 10. The emulation device 10 includes an emulator unit 11 and a target unit 12. The emulator unit 11 includes a CPU 13 and a buffer 14, and the target unit 12 includes an oscillator. 15, a flip-flop 16, a synchronous timing generation circuit 17, a multiplexer 18, a timing generator 19, a control circuit 20, and a CPU 21. Each of the CPU 13 and the target unit 12 of the emulator unit 11 has a data bus (not shown). And an address bus.

A CPU 13 in an emulator unit (system control device) 11 receives a clock signal CK from an oscillator 15 in a target unit 12 via a flip-flop 16 and a buffer 14.
A reference clock signal 1 / 2CK is generated by a clock signal 1 / 1CK input to IN, and a clock output CKOU is generated.
From T, it outputs to the synchronization timing generation circuit 17 in the target unit 12.

An oscillator (OSC) 15 in the target unit (peripheral device) 12 outputs an original clock signal 2 / 1CK to a flip-flop 16 and a multiplexer 18, and a flip-flop (F / F) 16 outputs an original clock signal. The signal 2 / 1CK is output to the emulator unit 11 and the multiplexer 18 as a 1/2 cycle original clock signal 1 / 1CK of 1/2 cycle.
The synchronization timing generation circuit 17 includes a phase comparator 22, a low-pass filter 23, a voltage controlled oscillator 24, and an up / down counter 25.

A phase comparator (phase difference detection circuit) 22 is constituted by an exclusive OR circuit (XOR), and a reference clock signal 1 / 2CK input from the emulator unit 11 and a correction input from the up / down counter 25. Clock signal 1
/ 2CK ′ and detects a phase difference, and outputs a predetermined phase difference signal to the low-pass filter 23. The low-pass filter (LPF) (voltage output circuit) 23 converts the phase difference signal input from the phase comparator 22 into a predetermined DC voltage signal and outputs it to the voltage controlled oscillator 24.

A voltage controlled oscillator (VCO: Voltage Co.)
The ntrolled oscillator 24 outputs to the up / down counter 25 an oscillation signal whose oscillation frequency is changed according to the DC voltage signal input from the low-pass filter 23.
The up / down counter (counter circuit) 25 is composed of a counter circuit having a number of stages n, and counts up and down in accordance with a change in the frequency of the oscillation signal input from the voltage controlled oscillator 24, and counts the frequency of the reference clock signal 1 / 2CK. A phase comparator compares the corrected clock signal 1 / 2CK 'according to the fluctuation.
22 and a timing generator 19, and outputs a plurality of synchronous clock signals 1 / 1CK 'and 2 / 1CK' synchronized with the original clock signal 2 / 1CK by the outputs of the multi-stage counter circuit for each stage number n. Output to

In this embodiment, when the phase difference between the reference clock signal 1 / 2CK input by the phase comparator 22 and the corrected clock signal 1 / 2CK 'disappears and matches, the phase difference signal output becomes "0". Is designed to be
The DC output voltage of the low-pass filter 23 at that time determines the oscillation frequency of the voltage controlled oscillator 24, and the up-down counter
It is designed such that the frequency of the correction clock signal 1 / 2CK 'counted by 25 is synchronized with the frequency of the reference clock signal 1 / 2CK.

The synchronous clock signal 1 synchronized with the reference clock signal 1 / 2CK in the synchronous timing generation circuit 17
The processing time until / 1 / CK 'and 2 / 1CK' are output is designed to converge during the reset period in which each peripheral device is not operating. A multiplexer (MPX) (clock selection circuit) 18 is provided with a mode selection signal (emulator mode: EMU MO) input from the emulator unit 2.
DE), the original clock signal 2 / 1CK input from the oscillator 15 and the flip-flop 16, the 1/2 original clock signal 1 / 1CK, and the synchronous clock signal 1 / 1CK 'input from the up / down counter 25, The two clock signals of the original oscillation side or the synchronization side are selected from / CK1 ′ and output to the timing generator 19.

The timing generator 19 selects various peripheral devices, such as a ROM and a RAM, connected by a chip select signal CS, and outputs the original clock signals 2 / 1CK and 1/2 original clock corresponding to the various peripheral devices. Clock signal 1/1
CK or synchronous clock signal 1 / 1CK ', 2 / 1C
A strobe signal STROBE based on K 'is output to a peripheral device (not shown).

The control circuit 20 controls the transfer of data to and from a register, for example, as another peripheral device connected to the outside.
The PU 13 controls transmission and reception of data of the designated register address via the data bus and the address bus. CP
U21 is originally a CPU that controls the operation timing of each unit in the target unit 12, and enters a sleep state by a mode selection signal input from the emulator unit 11,
The control right of 21 is transferred to the CPU 13 of the emulator unit 11, and C
Various emulation tests in the target unit 12 are executed under the control of the PU 13.

Next, the operation will be described. Emulator section 11
When an emulation mode signal is input to the target unit 12 as a mode selection signal from the CPU 21, the CPU 21 enters a sleep state, and each unit in the target unit 12
Under the control of the CPU 13. Under this control, the reference clock signal 1 generated in the CPU 13 by the flip-flop 16 from the oscillator 15 during the reset period.
/ 2CK is a phase comparator in the synchronous timing generation circuit 17
When a phase difference is generated between the input clock signal 22 and the corrected clock signal 1 / 2CK 'input from the up / down counter 25, a phase difference signal of the phase difference is output to the low-pass filter 23 and the DC voltage signal When the oscillation signal of the predetermined oscillation frequency is input to the up / down counter 25 by the voltage controlled oscillator 24, the corrected clock signal 1 / 2CK 'is output from the up / down counter 25 to the phase comparator 22 again, In the timing generation circuit 17, up-down count processing is executed until the phase difference between the reference clock signal 1 / 2CK and the corrected clock signal 1 / 2CK 'in the phase comparator 22 disappears and coincides with each other, and is synchronized with the reference clock signal 1 / 2CK. Synchronized clock signals 1 / 1CK 'and 2 / 1CK' having different frequencies are generated and output to the multiplexer 18.

In the multiplexer 18, when the emulation mode signal is valid, the synchronous clock signal 1 / 1CK
', 2 / 1CK' is selected and the timing generator
When the emulation mode signal is invalid, the original clock signal 2 / 1CK and the 1/2 original clock signal 1 / input from the oscillator 15 and the flip-flop 16 are output.
1CK is selected and output to the timing generator 19.

In the timing generator 19, the input synchronous clock signal 1 / 1CK 'or synchronous clock signal 2 / 1CK' is supplied to a peripheral device selected by the chip select signal CS, and an emulation mode test is performed. Therefore, in the target unit 12, by connecting the synchronization timing generation circuit 17,
The phase shift of the reference clock signal 1 / 2CK output from the CPU 13 in the emulation unit 11 is surely corrected, and the synchronous clock signal 1 / synchronized with the reference clock signal 1 / 2CK.
1CK 'and 2 / 1CK' can be supplied to a peripheral device (not shown), so that even if the peripheral device is faster than the operation speed of the CPU 13, synchronization can be achieved.

FIG. 2 shows the emulation device of FIG.
10 is a diagram showing an example of applying the A SIC, 2
Now, the flip-flop 16, the multiplexer 18, and the timing generator in the target unit 12 shown in FIG.
19. The control circuit 20 and the CPU 21 are connected to the CPU core ASIC (A
SIC) 30 configuration, and the synchronous timing generation circuit 17
It can be connected to the multiplexer 18 in the U-core ASIC 30. The mode selection signal allows the clock signal 2 / 1CK, 1 / 1CK on the original side of the oscillator 15 and the synchronous clock signal 1 / 1CK ', 2 on the synchronous timing generation circuit 17 side. / 1CK
'Is easily selectable between the and its features the time the.

With the configuration of the CPU core ASIC 30 as described above, a phase shift occurs before the reference clock signal 1 / 2CK supplied from an external system such as the CPU 13 in the emulator section 11 is input to the CPU core ASIC 30. And the reference clock signal supplied from the external system and the synchronous clock signal corrected for the phase shift of the reference clock signal can be switched more easily than the mode selection in the multiplexer 18. In this case, an emulation device can be easily constructed.

FIGS. 3 to 6 are diagrams showing an embodiment of the synchronization timing generation circuit according to the present invention . FIGS. 3 and 4 are diagrams showing a circuit configuration of the synchronization timing generation circuit 31. In FIGS. 3 and 4, the same components as those of the emulation device 10 shown in FIG. Omitted.

3 and 4, the synchronous timing generation circuit 31 includes a gate circuit 32, an OR circuit 33, and a shift register 34.
And flip-flops F0 to F7,
In the present embodiment, it is designed such that eight types of synchronous clock signals each slightly different in phase synchronized with the reference clock signal are generated. As shown in FIG. 5, the gate circuit (clock selection circuit) 32 includes a NOR circuit NOn (n =
0 to 7) and an AND circuit ANn (n = 0 to 7) correspond to eight types of synchronization signals.
Circuits for the number of bits are provided, and as inputs to the NOR circuit NOn, six Qn outputs excluding the target Qn signal among the Qn outputs from the flip-flops F0 to F7 are input. 4 shift register
The clock signal CKn (n = 0 to 7) output from 34 is input to the AND circuit ANn, and the logical product output is output to the clock input CK of the flip-flops F0 to F7 as the clock signal CKAn (n = 0 to 7). It is configured to be.

The gate circuit 32 is designed to output a target clock signal CKAn when all Qn signals other than the target Qn signal are "0".
In the OR circuit 33, the Q from the flip-flops F0 to F7
The n outputs are input, and one of the synchronous clock signals CK0 to CK7 is selected and output by the OR output.

Shift register (shift clock circuit) 34
The original clock signal 2/1 inputted from the oscillator 15
The synchronous clock signal 16 / 1CK that is eight times the original clock input from the CK and the synchronous timing generation circuit 17 is input, and the original signal 2 / 1CK is divided into eight by the synchronous clock signal 16 / 1CK. , Eight kinds of synchronous clock signals CK0 to CK7 each having a different phase
Output to 32.

Next, the operation will be described. During the reset period in which the peripheral device is not operating as in the sequence shown in FIG. 6, the reset signal CKRESET is output from the flip-flop F0.
F7 reset input R, flip-flop
The Qn outputs of the top F0 to F7 are all "0" and the gate
Input to the gate 32 and then to the gate circuit 32
8 types with different phases input from the
First rising of the synchronous clock signals CK0 to CK7
The output clock signal is output as CKAn. Sand
Chi, only the clock signal CKA0~7 is one closest to the time of rise of the reset signal CKRESET signal is selected in the flip-up circuit F0~F7 clock input CK
All the Qn outputs other than the Qn outputs of the flip-flops F0 to F7 to which the selected clock signals CKA0 to CKA7 are input become "0" and are input to the OR circuit 33, and the selected clock signals CKA0 to CKA0 are selected. 7 are finally output from the OR circuit 33 to peripheral devices (not shown).

Therefore, during the reset period, the clock signal C closest to the rising of the reset signal CKRESET is set.
KA0 to KA7 can be selected as synchronous clock signals, and by controlling the input timing of the reset signal CKRESET according to the peripheral device, a synchronous clock signal having a different phase synchronized with the reference clock signal can be supplied to the peripheral device. Can be.

3 and 4, the Qn outputs of the flip-flops F0 to F7 and the synchronous clock signals CK0 to CK7 from the shift register 34 do not have to coincide with each other. Is used as a selection bit to select a synchronous clock signal CK0 to CK7, a synchronous clock signal synchronized with a reference clock signal having an arbitrary phase can be generated by the circuit of FIG. It is possible to provide a synchronous timing generation circuit 31 that provides a synchronous clock signal corresponding to the device.

Therefore, the synchronous clock signal output from the synchronous timing generation circuit 31 is processed by a circuit in which logics such as frequency division and gates are combined, so that the CPU
A timing circuit synchronized with the operation timing can be configured, and even when various peripheral devices are separated from the system control device, the operation timing can be reliably synchronized with the CPU.

[0034]

According to the first aspect of the present invention, a phase shift of a reference clock signal output from the system control device, which is connected between the system control device and the various peripheral devices, is corrected, and each of the various peripheral devices is corrected. A synchronous timing generation circuit that outputs a synchronous clock signal synchronized with a reference clock signal in accordance with a processing speed, wherein the synchronous timing generation circuit detects a phase difference between a reference clock signal input from a system control device and a correction clock signal input from a counter circuit. A phase difference detection circuit that detects and outputs a predetermined phase difference signal; a voltage output circuit that outputs a predetermined DC voltage signal corresponding to the phase difference signal output from the phase difference detection circuit; A voltage-controlled oscillation circuit that outputs an oscillation signal having a frequency corresponding to the DC voltage signal, and an up-down converter that outputs an oscillation signal that is output from the voltage-controlled oscillation circuit. And outputs a correction clock signal for correcting the phase difference to the phase difference detection circuit, and when the frequency of the oscillation signal matches the frequency of the reference clock signal, the processing for each of the various peripheral devices synchronized with the reference clock signal. a counter circuit for outputting a synchronizing clock signal of a plurality of frequencies corresponding to the speed, the synchronization output from the counter circuit
Multiple signals with different phases with respect to the clock signal
A shift clock circuit that outputs a shift clock signal;
During the reset period when the various peripheral devices are not operating
Multiple shift clocks output from the shift clock circuit
Clock signal in response to the clock signal.
A gate for selectively selecting and outputting a number of shift clock signals
Comprising a chromatography preparative circuit, and by correcting the phase shift of the reference clock signal outputted from the system controller, since a plurality of shift clock signal synchronized with the reference clock signal is supplied to the various peripheral devices, the system control A shift clock signal synchronized with the reference clock signal can be supplied to various peripheral devices by correcting a phase shift of a reference clock signal output from the device, and various peripheral devices can be supplied from the system controller.
, The operation timing can be reliably synchronized.

[0035]

[0036]

[Brief description of the drawings]

1 is a block diagram of an emulation device according to the synchronous timing generating circuit.

FIG. 2 is a block diagram of an emulation device according to the A SIC.

FIG. 3 is a block diagram showing a configuration of a gate circuit unit of the synchronous timing generation circuit according to the present invention .

FIG. 4 is a block diagram showing a configuration of a shift register unit of the synchronization timing generation circuit according to the present invention .

FIG. 5 is a diagram showing a circuit configuration in the gate circuit of FIG. 3;

FIG. 6 is a view showing a sequence of a reset signal input to the flip-flop in FIG. 3;

FIG. 7 is a diagram showing a connection configuration between a conventional emulator and a target.

FIG. 8 is a diagram illustrating a state of a phase shift of a clock signal input to the timing generator of FIG. 7;

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/06 H03L 7/00 H04L 7/04

Claims (1)

(57) [Claims] A system control device connected to the peripheral device, which operates in synchronization with a reference clock signal output from a system control device such as a CPU and has a different processing speed, between the system control device and the peripheral device; A synchronization timing generation circuit that corrects a phase shift of a reference clock signal output from the controller and outputs a synchronization clock signal synchronized with the reference clock signal in accordance with the processing speed of each peripheral device; A phase difference detection circuit for detecting a phase difference between the reference clock signal and the correction clock signal input from the counter circuit, and outputting a predetermined phase difference signal; and responding to the phase difference signal output from the phase difference detection circuit. A voltage output circuit for outputting a predetermined DC voltage signal, and an oscillation signal having a frequency corresponding to the DC voltage signal output from the voltage output circuit. A voltage-controlled oscillation circuit for outputting, and a correction clock signal for correcting a phase difference by counting up and down according to an oscillation signal output from the voltage-controlled oscillation circuit to a phase difference detection circuit, and the frequency of the oscillation signal is when matched with the frequency of the reference clock signal, a counter circuit for outputting a synchronizing clock signal of a plurality of frequencies corresponding to the processing speed of the various peripheral devices each synchronized with the reference clock signal, a synchronous clock signal output from the counter circuit Criteria and
To generate multiple shift clock signals with different phases
A shift clock circuit for outputting, during a reset period in which the various peripheral devices are not operating.
Multiple shift clocks output from the shift clock circuit
Clock signal in response to the clock signal.
A gate for selectively selecting and outputting a number of shift clock signals
Synchronization timing generating circuit comprising: the over preparative circuit.