JP2000082955A - Phase locked loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed operation, to execute a normal operation without being affected by the delay quantity in a delay circuit and to eliminate jitters in the permissible phase difference of an intra-chip clock by providing a phase comparison circuit outputting a phase synchronizing signal. SOLUTION: A delay circuit 101 outputs clocks delayed in respective gate circuit units from the output terminals of respective gate circuits. A phase comparison circuit 102 compares the phases of an intra-chip clock and a system clock and outputs L when the phase of the intra-chip proceeds as an up down counter control signal and outputs H when the phase is delayed. When the intra-chip clock is within the permissible phase difference, L is outputted as a phase synchronizing signal from a phase synchronizing signal output terminal 109 and H when it is out of the permissible phase difference. An up/down counter 103 outputs the count value of the up down counter control signal. A selection circuit 104 selects output corresponding to the count value and outputs it from the clock output terminal 108 of a phase locked loop.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a phase locked loop, and more particularly to a digital phase locked loop using a delay circuit.

[0002]

2. Description of the Related Art Digital computers and the like generally have a plurality of semiconductor chips, and signal transmission between the chips is transmitted in one cycle of a clock in synchronization with a system clock supplied to the plurality of chips. Is done. Today, as the operating frequency of the system clock exceeds 100 MHz, it is indispensable to minimize the phase difference between the system clock and the clock in the chip as much as possible in order to realize signal transmission with this high-speed clock. on the other hand,
With the increase in chip size, a multi-stage clock buffer that supplies clocks to thousands of places in the chip becomes indispensable, but the delay caused by this clock buffer causes a large phase difference between the system clock and the clock in the chip. This hindered both large scale and high speed. This becomes more remarkable as the system clock becomes faster and the chip becomes larger. One of the techniques for minimizing the phase difference between the system clock and the on-chip clock is a phase synchronization circuit. Since the phase synchronization circuit functions to match the phases of the two clocks, a phase synchronization circuit 701 is inserted between the system clock input terminal 703 and the multi-stage clock buffer 702 as shown in FIG. By feeding back the clock output from the output terminal 704 to the phase synchronization circuit 701, the delay of the multi-stage clock buffer 702 can be eliminated, and the phase difference between the system clock and the on-chip clock can be minimized. One of the phase locked loop circuits that can be relatively easily realized by a gate array is a digital phase locked loop circuit using a delay circuit. This phase synchronization circuit minimizes the phase difference between the system clock and the on-chip clock by delaying the on-chip clock one clock cycle ahead using the delay of the delay circuit.

FIG. 6 shows a block diagram of a conventional technique of this phase locked loop circuit. 6, reference numeral 101 denotes a delay circuit;
01 is a phase comparison circuit, 103 is an up / down counter,
104 is a selection circuit, 105 is a system clock input terminal, 106 is a clock input terminal in the chip, and 108 is a clock output terminal of the phase synchronization circuit. Delay circuit 101
Is composed of a multi-stage gate circuit in which gate circuits are connected in series and an output terminal of each gate circuit, and outputs a clock delayed for each gate circuit from the output terminal of each gate circuit. The phase comparison circuit 601 compares the phase of the system clock with the phase of the on-chip clock, and outputs L as an up / down counter control signal when the phase of the on-chip clock is advanced and H when the phase is delayed. The up / down counter 103 counts up when the up / down counter control signal is L and counts down when the up / down counter control signal is H, and outputs the count value. Selection circuit 1
Reference numeral 04 selects an output corresponding to the count value of the up / down counter 103 from the output terminals of the respective gate circuits of the delay circuit 101, and outputs the output from the clock output terminal 108 of the phase-locked loop. Here, as the count value of the up / down counter 103 increases, the delay circuit 1
It is assumed that an output terminal having a large delay of 01 and an output terminal having a small delay as the count value is small are selected. As described above, by using the delay of the delay circuit 101, when the phase of the clock in the chip is advanced, the output terminal of the delay circuit 101 having a large delay is sequentially selected to delay the phase. By sequentially selecting smaller output terminals and advancing the phase, and delaying the on-chip clock by one clock cycle, the phase difference between the system clock and the on-chip clock is reduced to within the delay of each gate circuit unit of the delay circuit 101. Can be

[0004]

However, in the prior art, the phase comparator 601 outputs only signals when the phase of the clock in the chip is advanced and delayed, and the clock in the chip is not allowed. A signal when the phase difference was within the range, that is, a phase synchronization signal was not output. For this reason, the time required for the clock in the chip to be within the allowable phase difference cannot be accurately determined, and it is necessary to secure this time as necessary and sufficient, and there is a problem that high-speed operation cannot be realized. Further, when the output terminal with the minimum delay and the output terminal with the maximum delay are selected from the output terminals of the respective gate circuits of the delay circuit 101, that is, the up-down counter 103
No control circuit is provided when the minimum and maximum count values are selected. Therefore, the phase of the clock in the chip is delayed, and the up-down counter 103
The count value of is the minimum value, and when it counts down next,
The count value becomes the maximum value, and the output terminal of the delay circuit 101 having the maximum delay is selected. Here, when the total delay amount of the delay circuit 101 is equal to one cycle of the clock, the clock in the chip is delayed in phase, so the up / down counter 103 counts down from the maximum value, and the output terminal of the delay circuit 101 Are sequentially selected from the output terminal with the largest delay to the output terminal with the smallest delay, and operate normally. However, the delay circuit 101 needs to have a delay amount of one cycle or more under the operating condition where the delay amount is maximum because the delay amount needs one cycle of the clock under the entire operating environment of the chip. become. For this reason, when the delay amount becomes 1.5 cycles or more under the operating condition in which the delay amount is the maximum, the clock in the chip is advanced in reverse, and the up-down counter 103 counts up from the maximum value, that is, As a result of selecting only the minimum value and the maximum value, there is a problem that the device does not operate normally. Conversely, the phase of the clock in the chip advances, and the up-down counter 103
Has the same problem when the count value is the maximum value and the next up-count is performed. Furthermore, the up / down counter 103 cannot be stopped when the clock in the chip is within the allowable phase difference. For this reason,
Even when the phase difference is within the allowable phase difference, the phase of the clock in the chip always fluctuates, that is, there is a problem that jitter occurs.

Therefore, the present invention is to solve such a problem, and an object of the present invention is to enable high-speed operation and normal operation without being affected by the delay amount of the delay circuit. Another object of the present invention is to provide a phase synchronization circuit free from jitter when the clock in the chip is within the allowable phase difference.

[0006]

According to the first aspect of the present invention,
A phase synchronization circuit including a delay circuit, a phase comparison circuit, an up / down counter, and a selection circuit, characterized by including a phase comparison circuit that outputs a phase synchronization signal.

A second aspect of the present invention is characterized in that, in the first aspect, a control circuit for forcibly counting up and down the up / down counter is provided.

According to a third aspect of the present invention, in the second aspect, there is provided an up-down counter for stopping the counting operation by the control signal and holding the count value at that time, and the control signal is the phase synchronization signal. Features.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the first aspect of the present invention. In FIG. 1, 101 is a delay circuit, 102 is a phase comparison circuit, 103 is an up / down counter, 104 is a selection circuit, 105 is a system clock input terminal, 106 is an on-chip clock input terminal, 107 is a reset signal input terminal, and 108 is Clock output terminal of the phase locked loop, 109
Is a phase synchronization signal output terminal. The delay circuit 101 includes a multi-stage gate circuit in which gate circuits are connected in series and output terminals of each gate circuit, and outputs a clock delayed by each gate circuit from the output terminal of each gate circuit. The phase comparison circuit 102 compares the phase of the clock in the chip with the phase of the system clock, and outputs L as an up / down counter control signal when the phase of the clock in the chip is advanced and H when the phase is delayed. Further, L is output from the phase synchronization signal output terminal 109 as a phase synchronization signal when the clock in the chip is within the allowable phase difference. When the phase difference is outside the allowable phase difference, H is output. The up / down counter 103 counts up when the up / down counter control signal is L and counts down when it is H, and outputs the count value. The selection circuit 104
Among the output terminals of each gate circuit of the delay circuit 101, an output corresponding to the count value of the up / down counter 103 is selected, and the output is selected as the clock output terminal 10 of the phase synchronization circuit.
8 to output. Here, it is assumed that the larger the count value of the up / down counter 103 is, the longer the output terminal of the delay circuit 101 is, and the smaller the count value is, the smaller the delay terminal is. In the phase synchronization operation, when the reset signal is L, the operation is stopped. As described above, by using the delay of the delay circuit 101, when the phase of the clock in the chip is advanced, the delay circuit 101
Are sequentially selected to delay the phase, and when the phase is delayed, the output terminals having a small delay are sequentially selected and the phase is advanced to delay the clock in the chip one clock cycle ahead. As a result, the phase difference between the on-chip clock and the system clock is
Can be adjusted within the delay of each gate circuit unit.

FIG. 2 is a circuit diagram showing one embodiment of the phase comparison circuit 102. In FIG. 2, the phase comparison circuit 102
Are a system clock input terminal 105, an on-chip clock input terminal 106, a reset signal input terminal 107, an H level signal input terminal 201, an up / down counter control signal output terminal 202, and a phase synchronization signal output terminal 10.
9 and forward logic delay circuit 203 and forward logic delay circuit 2
04, inverter circuit 11, NAND circuit 12, and AND
It comprises a circuit 13, an OR circuit 15, and a flip-flop circuit 16, and outputs L from the up / down counter control signal output terminal 202 when the phase of the clock in the chip is advanced, and outputs H when the phase is delayed. Further, the phase synchronization signal output terminal 109 outputs L when the phase difference between the system clock and the on-chip clock is equal to or less than the delay amount of the delay circuit 203, and outputs H when the phase difference is equal to or greater than the delay amount. That is, by setting the delay amount of the delay circuit 203 within the allowable phase difference of the clock in the chip, the phase synchronization signal can be output within the allowable phase difference. By having the phase comparison circuit that outputs the phase synchronization signal in this way, it is possible to accurately determine the time when the clock in the chip is within the allowable phase difference, and it is not necessary to secure the time sufficiently and sufficiently. High-speed operation can be realized.

(Embodiment 2) FIG. 3 is a block diagram showing an embodiment of a phase locked loop circuit according to the second aspect of the present invention. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 3, reference numeral 301 denotes a control circuit for forcibly counting up and down the up / down counter. FIG. 4 shows the control circuit 3
FIG. 1 is a circuit diagram showing one embodiment of the present invention. In FIG. 4, the control circuit 301 includes an in-chip clock input terminal 106, a reset signal input terminal 107, and an H level signal input terminal 20.
1, an up / down counter control signal input terminal 402, an up / down counter output signal input terminal 4030-403n, an up / down counter control signal output terminal 404, an inverter circuit 11, an AND circuit 13, and a NOR circuit 14. An up-down counter control signal output terminal 404 comprises an OR circuit 15 and a flip-flop circuit 16.
When the signal of the phase synchronization signal input terminal 401 is H and the count value of the up / down counter is the minimum value, L is output regardless of the signal of the up / down counter control signal input terminal 402, and H is output when the count value is the maximum value. . Further, when the signal of the phase synchronization signal input terminal 401 is L or when the count value of the up / down counter is other than the minimum value and the maximum value, the signal of the up / down counter control signal input terminal 402 is output. That is,
When the minimum value is output from the up / down counter, the up / down counter can be forcibly counted up until the phase is synchronized, and when the maximum value is output, the down count can be forcibly counted down until the phase is synchronized. When the phase synchronization signal is output, the forced operation is released, and the up / down counter can be controlled by the up / down counter control signal of the phase comparison circuit. Here, the minimum value of the counter value of the up / down counter 301 is all L, and the maximum value is all H. in this way,
By having a control circuit for forcibly up-counting and down-counting the up-down counter, the up-down counter can be forcibly controlled and phase-synchronized, so that it is not affected by the delay amount of the delay circuit.
The phase locked loop can operate normally.

(Embodiment 3) FIG. 5 is a block diagram showing an embodiment of a phase locked loop circuit according to the third aspect of the present invention. In FIG. 5, the same portions as those in FIGS. 1 and 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 5, 5
Reference numeral 01 denotes an up / down counter which stops the count operation by a control signal and holds the count value at that time, and uses the phase synchronization signal as the control signal. The up / down counter 501 stops the counting operation when the phase synchronization signal is output, and holds the count value at that time. That is, when the clock in the chip is within the allowable phase difference, the count value of the up / down counter 501 does not change, so that the phase of the clock in the chip does not change. As described above, the up / down counter is an up / down counter that stops the counting operation by the control signal and holds the count value at that time, and uses the phase synchronization signal as the control signal. It is possible to realize a phase synchronization circuit in which the phase does not change and has no jitter.

[0014]

According to the first aspect of the present invention, there is an effect that a phase locked loop circuit capable of high-speed operation can be provided.

According to the second aspect of the present invention, not only the same effects as those of the first aspect of the invention are obtained but also a phase enabling normal operation without being affected by the delay amount of the delay circuit. This has the effect of providing a synchronous circuit.

According to the third aspect of the present invention, it is possible to provide a phase-locked loop circuit which has the same effect as that of the second aspect and has no jitter when the clock in the chip is within an allowable phase difference. It has the effect of.

[Brief description of the drawings]

FIG. 1 is a block diagram according to the first embodiment;

FIG. 2 is a circuit diagram according to the first embodiment.

FIG. 3 is a block diagram according to the invention described in claim 2;

FIG. 4 is a circuit diagram according to the invention described in claim 2;

FIG. 5 is a block diagram according to the invention of claim 3;

FIG. 6 is a block diagram showing a conventional technique.

FIG. 7 is a diagram showing an example of use of a phase locked loop.

[Explanation of symbols]

101 delay circuit 102 phase comparator 103 up / down counter 104 selection circuit 105 system clock input terminal 106 in-chip clock input terminal 107 reset signal input terminal 108 phase synchronization circuit Clock output terminal 109 ··· phase synchronization signal output terminal 201 ··· H level signal input terminal 202 ··· up / down counter control signal output terminal 203 ··· delay circuit 204 ··· delay circuit 301 ··· control circuit 401 ··· phase synchronization Signal input terminal 402 Up-down counter control signal input terminal 4030 to 403n Up-down counter output signal input terminal 404 Up-down counter control signal output terminal 501 Up-down counter 601 Phase comparison circuit 801 Phase synchronization circuit 802 Multi-stage clock buffer 803 System clock input terminal 804 Clock output terminal in chip 11 Inverter circuit 12 NAND circuit 13 AND circuit 14 NOR circuit 15 OR circuit 16 ..Flip-flop circuits

Claims (3)

[Claims] 1. A phase synchronization circuit having a delay circuit, a phase comparison circuit, an up / down counter, and a selection circuit, comprising a phase comparison circuit for outputting a phase synchronization signal. 2. A phase locked loop circuit according to claim 1, further comprising a control circuit for forcibly counting up and down the up / down counter. 3. A phase synchronization apparatus according to claim 2, further comprising an up / down counter for stopping a count operation by a control signal and holding a count value at that time, wherein said control signal is said phase synchronization signal. circuit.