JPH05268020A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To prevent noise from being generated at switching. CONSTITUTION:When a selection signal at a low level is inputted, a terminal S of a selector 8 selects a clock 1 inputted to a terminal A, and when selection signal at a high level is inputted, the terminal S of the selector 8 selects a clock 2 inputted to a terminal B on the other hand, and the selected signal is outputted from a terminal Y as a clock 9. Integration circuits 4, 5 each consists of a resistor and a capacitor and integrate respectively the clocks 1, 2. An AND circuit 6 ANDs output signals of the integration circuits 4, 5 and outputs a clock resulting from delaying the clock 1 (2). A flip-flop 7 fetches a switching signal 3 at the leading of the output signal of the AND circuit 6 and gives the signal 3 to the terminal S of the selector 8 as the selection signal 71. As a result, the selection signal 71 is selected while the level of the clocks 1, 2 is stable at all times and the production of noise is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for switching clocks.

[0002]

2. Description of the Related Art Conventionally, a clock switching circuit as shown in FIG. 3 has been used in a semiconductor integrated circuit or the like. This circuit comprises a selector 8, a clock 10 is input to its input terminal A, a clock 11 is input to its input terminal B, and a switching signal 12 is input to its selection signal input terminal S. Then, as shown in the timing chart of FIG. 4, when the switching signal 12 is at the low level, the selector 8 selects the clock 10 and outputs it as the clock 13 from the output terminal Y. On the other hand, when the switching signal 12 is at the high level, the selector 8 selects the clock 11 and outputs it as the clock 13 from the output terminal Y.

[0003]

However, in such a conventional clock switching circuit, since the switching signal 12 is directly input to the selector 8, the logical level of the switching signal 12 falls (falls) of the clocks 10 and 11. If it changes in the vicinity of (rising), the clock 13 may have a noise N as shown in the figure due to a slight deviation between the clocks 10 and 11.
Occurs, causing a malfunction in the circuit to which the clock 13 is supplied.

An object of the present invention is to solve the above problems and provide a clock switching circuit in which noise is not generated during switching.

[0005]

A clock switching circuit according to the present invention includes a selector which receives first and second clocks and outputs one of the two clocks based on a predetermined selection signal, and the selector. First and second integrator circuits for integrating and outputting the first and second clocks, respectively,
An AND circuit which receives the output signals of the first and second integrator circuits, a predetermined switching signal and an output signal of the AND circuit are respectively received as data and a clock, and the output signal is supplied to the selector as the selection signal. And a flip-flop that operates.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a clock switching circuit according to the present invention. When a low-level selection signal is input to the terminal S, the selector 8 selects the clock 1 input to the terminal A and outputs it as the clock 9 from the terminal Y, while the high-level selection signal is input to the terminal S. When a signal is input, the clock 2 input to the terminal B is selected and output as the clock 9 from the terminal Y. The integrating circuits 4 and 5 are
The clocks 1 and 2 are respectively integrated by resistors and capacitors. The AND circuit 6 takes the logical product of the output signals of the integrating circuits 4 and 5. Flip flop 7
Receives the switching signal 3 as data at the terminal D and the output signal of the AND circuit 6 as a clock at the terminal C. Then, the switching signal 3 is fetched at the rising edge of the output signal of the AND circuit 6 and supplied to the terminal S of the selector 8 as a selection signal.

Next, the operation will be described with reference to the timing chart of FIG. Clocks 1 and 2 are clocks having a predetermined cycle as shown in the figure. Since the integrator circuits 4 and 5 integrate the clocks 1 and 2, respectively, their output signals 41 and
51 has a dull waveform as shown in the figure.

The AND circuit 6 outputs a high level signal when both the signals 41 and 51 exceed the threshold level from low level to high level, and conversely, either of the signals 41 and 51 is high level. When the threshold level from to low level is exceeded, a low level signal is output. As a result, the output signal 6 of the AND circuit 6
1 is obtained by slightly delaying the clocks 1 and 2.

Since the switching signal 3 is taken into the flip-flop 7 at the rising edge of the output signal 61, when the switching signal 3 goes high at the timing T1 as shown in the figure, the timing T of the next rising edge of the output signal 61 is reached.
At 2, the flip-flop 7 outputs the high-level selection signal 71. Therefore, the selector 8 selects the clock 1 and outputs it as the clock 9 before the timing T2, but selects the clock 2 and outputs it as the clock 9 after the timing T2. The level of the selection signal 71 changes in a stable steady state in which the clocks 1 and 2 are completely at the high level, so that no noise is generated in the clock 9 as shown in the figure.

[0010]

As described above, the clock switching circuit of the present invention has a selector which receives the first and second clocks and outputs one of the two clocks based on a predetermined selection signal. A first and second integrator circuit for integrating and outputting the second and second clocks, an AND circuit for receiving the output signals of the first and second integrator circuits, and a predetermined switching signal and an AND circuit. And a flip-flop for receiving the output signal as a data signal and a clock and supplying the output signal as a selection signal to the selector.

Therefore, in the clock switching circuit of the present invention,
A clock obtained by delaying the first and second clocks is output from the AND circuit, and the flip-flop fetches the switching signal based on the clock. Therefore, the selection signal output from the flip-flop does not change in the transient state in which the logic levels of the first and second clocks change, and the first and second clocks are completely set to high level or low level and stable. It changes depending on the condition. As a result, the clock output from the selector does not include any noise associated with the clock switching, and it is possible to prevent the circuit from malfunctioning.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a clock switching circuit of the present invention.

FIG. 2 is a timing chart showing an operation of the clock switching circuit of FIG.

FIG. 3 is a circuit diagram showing an example of a conventional clock switching circuit.

FIG. 4 is a timing chart showing the operation of the clock switching circuit of FIG.

[Explanation of symbols]

 4, 5 Integration circuit 6 AND circuit 7 Flip-flop 8 Selector

Claims (2)

[Claims] 1. A selector which inputs first and second clocks and outputs one of the two clocks based on a predetermined selection signal, and outputs by integrating each of the first and second clocks. A first and second integrator circuit, an AND circuit that receives the output signals of the first and second integrator circuits, and a predetermined switching signal and an output signal of the AND circuit as data and a clock, respectively. A clock switching circuit comprising: a flip-flop that supplies an output signal as the selection signal to the selector. 2. The switching circuit according to claim 1, wherein each of the first and second integrating circuits comprises a resistor and a capacitor.