JPS6117636Y2 - - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a counter capable of phase synchronization.

An example of a conventional decimal counter is shown in Figure 1a. The figure shows a BCD (binary coded decimal) output decimal counter 1, its input clock pulse 11, and outputs 21, 22, 23 and 24 from the lower digit to the upper digit. FIG. 1b shows a time chart of this counter. Normally, the 10 phase states of each output of this counter are numbered from 0 to 9 as shown in the figure. Here, let's focus on the seventh phase as an example. The signal _Φ7 is a positive logic "1" only in the seventh phase, and is "0" in other phases. On the other hand, suppose that a periodically repeating phase synchronization pulse SYNC is applied from outside this decimal counter. however,
It is assumed that this phase synchronization pulse is obtained from the input clock 11. That is, among the output phase states of the counter 1, one phase is "0" and the others are "1". An example of such a synchronizing pulse can be produced from another counter 1' having the same structure as the decimal counter 1 and a two-input NAND gate 2, as shown in FIG. 1c.

When a phase synchronization pulse SYNC is given, one of the conventional methods of matching the phase of the seventh phase φ ₇ of the counter in FIG. The solution is to use one that allows you to set the value of each digit from the outside. An example is shown in FIG. 2a. 13 is input 3 of each digit of counter 3
Logic “0” with control signal for setting 1 to 34
Inputs 31 to 34 are connected to the flip-flops of each digit of the counter, and are read by input clock pulses. 13
is given the phase synchronization pulse SYNC shown in FIG. Here, 31 to 33 are logic “0”, 3
4 is set to logic "1". The time chart at this time is shown in FIG. 2b.

However, if a decimal counter is used in which the value of each digit cannot be set, the above method cannot solve the problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase-locked counter in which the internal movement of the counter can be synchronized to external phase-locked pulses by means of a logic circuit external to the counter.

Let's explain again using the case of synchronizing _φ7 with SYNC as an example. A specific circuit diagram is shown in FIG. 3a. 4 is a logic inversion circuit, and 5 is an AND gate, whose output 14 becomes "1" at the seventh phase, and is a signal that coincides with _φ7 . 6 is an OR gate, and 7 is an AND gate. By these two gates and the signal φ ₇ , the phase of φ ₇ of the counter is synchronized with the phase synchronization pulse (SYNC) 13.

To demonstrate the principle, first, as shown in Figure 3b,
Consider the case where φ ₇ (waveform 14) and SYNC (waveform 13) are not synchronized. In this state,
When SYNC 13 is input to OR gate 6, its output 15 becomes a logic "0", resulting in the output of the AND gate (or the input clock pulse of counter 1).
16 is also logic “0”, as shown in waveform 16,
One pulse disappears. Therefore, the internal phase state of counter 1 will be delayed by one clock pulse with respect to SYNC13. That is, gate 5
The output pulse 14 of is generated with a delay of one clock. Since the phase synchronization pulse SYNC is repeatedly input periodically, the internal phase is shifted until the phases of pulse 14 and pulse 13 match. At this time, output 1
5 is always "1" and the loss of one clock pulse no longer occurs. That is, this point is a phase-synchronized state, and as shown in the time chart c of the same figure, _φ7 is phase-synchronized with SYNC.

According to the present invention, the counter 1 can be used without any modification by simply adding external logic circuits 4, 5, 6 to 7.

The general form of the present invention can be shown as shown in FIG. In the same figure, 11, 13, 6, 7, 15 and 16 are the same as the explanation in Figure 3, but 8 is a counter for the number of digits (or number of stages), and 21, 22, 23...24 are from the lower digits. Each output to the upper digit, 9, is composed of a combination of logic gates, and the output 21 to each digit of the counter 8
24 as an input and outputs a pulse 14' which takes a logic value "1" at one internal phase of the counter 8. In the example of FIG. 3, the combination of the inverting circuit 4 and the gate 5 corresponds to the logic circuit 9, and _φ7 is used as the internal phase.

The present invention is not limited to a decimal counter, but may be a counter with a general number of digits (stages), and the phase to be synchronized is not limited to _φ7 , but may be any phase. The present invention can also be applied when the repetition frequency of SYNC is an integer fraction of the frequency of the output of the counter. For example, by applying a phase synchronization pulse SYNC as the input 13 in FIG. 3a in which only one out of every 60 clock pulses 11 that is common as the output of a sexagesimal counter becomes logic "0", this pulse can be given φ ₇ ( decimal counter output) can be synchronized. This principle is exactly the same as that described in FIG.

[Brief explanation of the drawing]

Figures 1a and b show a conventional decimal counter and its time chart, Figure 1c shows a conventional circuit for creating phase-locked pulses, and Figures 2a and b show conventional input settings. Figures 3a, b, and c show an embodiment of a phase synchronized counter and its time chart according to the present invention, and Figure 4 shows a general embodiment of the present invention. shows. 1 is a decimal counter, 11 is a clock pulse input,
13 is phase synchronization pulse input.

Claims (1)

[Scope of utility model registration request] a counter, a logic circuit that receives the output of each digit of the counter and obtains an internal phase pulse with a logical value of "1" corresponding to one internal phase of the frequency division process of the counter; A logical sum circuit that calculates the logical sum with a phase synchronizing pulse of logical value "0" given from the outside, and a logical product of the output of this logical sum circuit and a clock pulse given from the outside in synchronization with the phase synchronizing pulse. and an AND circuit that drives the counter by this AND output,
A phase synchronization counter characterized in that the internal phase is synchronized with the phase synchronization pulse.