JPS62191910A - Clock control system - Google Patents

Abstract

PURPOSE:To unify the logic levels of stop clocks by forming a control circuit for stopping a clock with a resetting flip flop using the output of a synchronizing circuit as input and with a basic clock stop signal generating flip flop which uses the output of the former flip flop as input. CONSTITUTION:The flip flops 3-5 are synchronizing circuits and serially connected, and a stop signal B is inputted to the flip flop 3. The flip flop 7 is a stop signal generating flip flop which generates a basic clock stop signal. A AND gate 2 is a one for controlling a basic clock, outputs a clock output signal F using the output signal A of the clock T of a driver 1 as one input and the output signal E of the stop signal generating flip flop 7 as the other input, and simultaneously supplies the signal F to a frequency dividing circuit 8. The circuit 8 inputs the output signal F to a clock input terminal and outputs clocks 2T, 4T and 8T obtained by frequency-dividing the connected T clock F.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock control system, and particularly to a clock control system for a combinator or the like having a plurality of clock periods.

[Conventional technology]

Conventionally, this type of clock control method has been controlled by synchronizing a clock stop signal with a clock. However, in recent years, due to advances in technology, the clock period in ultra-high-speed computers has become on the order of several nanoseconds. This L
It is very difficult to input a clock stop signal in synchronization with the clock in a system with a fast lock cycle.

For this reason, the clock stop signal is input as a signal asynchronous to the clock, and the synchronization circuit is used to control the clock in synchronization with the clock.

[Problem that the invention seeks to solve]

When stopping the divided clock using the t-clock control method described above, the signal level of the clock in the stopped state is
It is not possible to specify whether it will be 1" or logic 10#, and subsequent clock control will be subject to major restrictions. For example, using negative logic, from logic ``0# to logic 10#" A system using an edge-trigger type flip-flop, in which the switching of the clock is used as a clock edge.In this type of system, it is assumed that 10,000 clocks are input to an AND circuit that is distributed to individual units.

The other is used as a control signal to control each unit. In this case, it is desirable that the clock be stopped at a logic ``0'' which is applied to the stop signal. If the clock is stopped at logic @"O", even if the individual control signals operate, the clock is fixed at logic @Om and stopped. However, when the clock reaches the stop signal, the L logic 'm
If the clock stops at 1#, the clock moves when each control signal operates, so the control of each control signal is severely restricted.

[Means for solving problems]

In a clock system in which the clock control method of the present invention includes a basic clock, one or more types of frequency-divided clocks obtained by frequency-dividing the clock, and a stop signal for stopping all the above-mentioned clocks, a synchronization circuit constituted by a plurality of stages of flip-flops that receive the stop signal that is asynchronous with the clock; and a frequency divider circuit that receives the output of the synchronization circuit and whose output is a frequency-divided clock. It consists of a reset flip-flop connected to a reset input, and a flip-flop for generating a basic clock stop signal that receives the output of the reset flip-flop as an input.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows -'! of the present invention. i! An example is shown. In FIG. 1, this embodiment is a driver 1 which inputs a basic clock T and distributes it to each part of the corresponding basic clocks A and A'7.
and flip-flops 3 to 7 to which the basic clock AI-f from the driver 1 is input.

AND gate 2 which inputs basic clock Ai from driver 1 and sends out basic clock Ft;
The frequency dividing circuit 8 divides the frequency of the basic clock Fi from .

Flip-flops 3 to 5 are synchronization circuits, each of which is connected in series, and is configured such that a stop signal B is input to flip-flop 3. Flip-flop 6 is a reset signal generation flip-flop that generates a reset signal D=i, and flip-flop 7 is a stop signal generation flip-flop 70 that generates a basic tarlock stop signal. The AND gate 2 is a gate for basic clock control, and inputs the /T clock output signal A'i-10,000 of the driver 1, and inputs the output signal Ek% of the stop signal generating flip-flop 7, which receives the clock. In addition to outputting the output signal PI, this signal F'fr:
The signal is configured to be supplied to the frequency dividing circuit 8. The frequency dividing circuit 8 connects the output signal F-i of the AND gate 2 to the output signal D'k of the reset flip-flop 6.
It is connected to be input to the upper set output terminal of IJ, and outputs 2T, 4T, and 8T clocks obtained by dividing the T clock F, respectively.

FIG. 82 shows a time chart in one embodiment of the present invention. Referring to FIG. 2, the operation of this embodiment will be explained. Signals A and J are shown in FIG. 1 and show waveforms at each section. Note that, for the sake of simplicity, it is assumed that there is no delay time of each element.

When the stop signal B is input asynchronously with respect to the basic clock A, the stop signal C synchronized by the knobs 3 to 5 of the synchronization flip 70 is sent out as the output of the synchronization circuit at timing T1. However, since asynchronous signals are synchronized, this time chart is just an example, and the timing at which the synchronized stop signal appears may be different from @2, but in any case, it is synchronized to the basic clock T. has been done. At timing T2 after IT, the reset signal is set so that the output waveform of the reset 71J block flop 6 shows the output signal. Timing T3 after 1/2 T
Then, the clock edge of the basic clock T enters as the clock input signal F of the frequency divider circuit 8, and the frequency divider circuit 8 is reset to logic @O'' as shown by the output signals G, H, and J. /2 At timing T4 after T, the output signal E of the basic clock stop signal flip-flop 7 is set to logic 10'', and this signal E is output to the AND gate 2.
Therefore, at timing T5 after 1/2 T, the clock signal F of the basic clock T cannot be switched to the logic "1" and remains at the logic "0".

With the operation explained above, you can convert the basic clock T, divided clocks 2T, 4T, 8T, and all clocks into logic "IO".
It can be stopped at m.

In addition, in this embodiment, the reset signal Di logic ""0
It is also possible to stop all the clocks at logic @1 by using a frequency divider circuit that provides logic '1'.

〔Effect of the invention〕

As explained above, the present invention includes a synchronization circuit that receives a stop signal gold input, and a reset flip-flop that receives the output of the synchronization circuit and whose output is connected to the reset input of the frequency division circuit for creating a frequency division clock. By configuring a control circuit for stopping the clock with 7 circuits and 70 circuits for generating a basic clock stop signal which input the output of the reset flip-flop, the logical level v'' of the stop clock can be adjusted.
It has the effect of being able to unify o' and ke11#.

[Brief explanation of drawings]

The first figure is an embodiment of the present invention? The configuration diagram shown in FIG. 2 is a diagram showing a time chart in this embodiment. 1... Driver, 2. , , , AND gate, 3 to 7...Flip-flop, 8...
...Frequency divider circuit, A. A', F, T...Basic clock, B...
・Stop signal, C...Set signal, D...
- Reset signal, E...Basic clock stop signal %G, J...Divided clock. ,,,->,1. Agent Patent Attorney Uchihara ゛ ／＋, Throat ω

Claims (1)

[Claims] In a clock system that has a basic clock and one or more types of divided clocks obtained by dividing the frequency of the clock, and has a stop signal that stops all the types of clocks, the clock is in an asynchronous relationship with the clock. A synchronization circuit consisting of a plurality of stages of flip-flops that receives the stop signal as an input, and a reset flip-flop that receives the output of the synchronization circuit as an input and whose output is connected to a reset input of a frequency divider circuit for creating a frequency divided clock. and a flip-flop for generating a basic clock stop signal which receives the output of the reset flip-flop as input.