JPH0429409A - Clock signal generation circuit - Google Patents

Abstract

PURPOSE:To dispense with an oscillator and a frequency dividing circuit operated at high frequency by generating plural clock signals with phases different little by little, and selecting the clock signal provided with the phase optimum for a signal set as reference. CONSTITUTION:The frequency of an original oscillation circuit 2 is N.fs(N: integer) generally assuming a sampling frequency as fs, and phase comparison between M clock signals obtained by a multi-phase clock generation circuit 3 and a horizontal synchronizing signal set as reference is performed at a clock selection circuit 4, and the signal with the optimum phase is selected. As the multi-phase clock generation circuit, such configuration that plural(M) delay circuits are cascade-connected can be considered. In such a case, it is permitted to set the frequency of the generation circuit equal to N=one sampling frequency. Assuming the delay time of the delay circuit as (d), it is desirable that the frequency of the oscillation circuit 2 satisfies d*M>=1/fs.

Description

[Detailed description of the invention] (b) Industrial application field The present invention relates to a clock signal generation circuit.

(b) Conventional technology Broadcasting technology book 5 rVTR technology, pp. 121-12
2, prepare an original oscillation clock (denoted as N times the sampling clock) with a higher frequency than the sampling clock (denoted as fs), and reset the N frequency divider circuit with a horizontal synchronization signal etc. to obtain 1/(fs- A method for obtaining a sampling clock having a constant phase with a horizontal synchronization signal within a range of N) seconds is shown.

(c) Problems to be Solved by the Invention A PLL with only a feedback system cannot follow sudden phase changes. If high accuracy is to be obtained using the frequency division method described in the latter half of the prior art, it requires an oscillator and a frequency division circuit that operate at a high frequency, which has a limit.

(d) Means for Solving the Problems The present invention has a configuration that includes means for creating a plurality of clock signals with slightly different phases and selecting a tarokk signal having an optimal phase with respect to a reference signal. It becomes.

(e) Effect: Since the optimal phase is selected from multiple clock signals with different phases, there is no need to use high-speed operation devices such as oscillators and frequency dividers required for clock generation. .

(f) Example Hereinafter, the present invention will be described in detail with reference to the drawings.

Fig. 1 is a block diagram showing the overall outline, Fig. 2 is a block diagram of the multiphase clock generation circuit, Fig. 3 is a block diagram of the selection circuit, Fig. 4 is a waveform diagram for explaining the operation, Fig. 5 , FIG. 6 is a circuit block diagram showing another embodiment.

1 is a circuit that separates a horizontal synchronizing signal from an input video signal. 2 is an original oscillation circuit, and 3 is a multiphase tarlock generation circuit. The frequency of the original oscillator circuit 2 is generally N fs (N is an integer), where fs is the sampling frequency, and N is 3.
It is determined by the method of the multiphase tallock generation circuit. 4
is a tarok selection circuit. 3 Multiphase tallock generation circuit 3
The optimal one is selected and output from among the M clocks obtained.

As the multiple clock generation circuit 3, for example, as shown in FIG. 2, a configuration in which a plurality (M) of delay circuits 5-1 to 5-M are connected in a subordinate manner can be considered. In this case, the frequency of the oscillation circuit 2 is
N=1, that is, it may be equal to the sampling frequency. If the delay time of delay circuits 5-1 to 5-M is d, oscillation circuit 2
It is desirable that the frequency satisfies d*M≧1/fs. In the second case, the accuracy is the delay time d.

The selection circuit 3 compares the phases of these M clock signals and a reference horizontal synchronization signal, and selects the optimum one. For example, the configuration shown in FIG. 3 can be considered. In the configuration shown in Fig. 3, M tarok signals are used as data input,
M latch circuits 6 using horizontal synchronization signals as clock signals
-1 to 6-M (D-type flip-flops) and a logic circuit 7 that performs a selection operation based on their outputs.

Let M tarock signals be φ1, φ2, φ, .

...Let it be QM. The condition for selecting φ1 at this time is Q1
*Q, = 1 (* represents logical product, 1 represents true), φ.

The condition for selecting (Q 1's Q * ) ” (Q
t*Q r )=1. In general, φ, (1≦
The conditions for selecting 6M) are as follows.

al Letting the finally selected clock be φ, the general formula for φ is as follows, using π as the symbol for logical product and Σ as the symbol for logical sum.

(=1) The meaning of the conditional expression (1) above is as follows. If the logical product of negating only one of the latch outputs regarding adjacent clock signals is I (true), then the edge of the horizontal synchronizing signal The timing should be between these two clock signals.At this time, the phase difference between the clock signal and the horizontal synchronization signal is within the delay time d.

However, if only the condition (Qb*Qh+1)=1, d
*If M>1/f, there may be two or more phases for which the condition is satisfied. So, from φ, φ8, φ3,...
・By assigning priorities in the order of φ, φ
Clock signals up to 1 are no longer selected. As for the device, it is preferable to increase the value of d*M so that it can be applied to a wide frequency range, especially to a low frequency sampling clock.

FIG. 5 shows a clock generation circuit according to another embodiment.

Here, a 2fs oscillation signal is supplied from the oscillation circuit 10 (having a frequency of 2fs) to the operational amplifier 11 to create signals having a phase difference of 180 degrees.

Furthermore, based on this signal, the latch circuit 12.13.1
4, a four-phase lock signal φ with a phase difference of 90 degrees is generated.
1, φ8, φ3, and φ4 are created.

In this case, since d = 1/4 f s and M = 4, there is only one clock signal that satisfies the condition cl*M = 1/f S%QkIQ, +1 = 1, so the configuration of the selection circuit is simple. become.

FIG. 6 shows a block diagram of a selection circuit corresponding to FIG. 5. Here, each clock signal φ, ~φ is latched in the latch circuits 21 to 24 at the rising edge of the horizontal synchronization signal, and the logical product of Qk*Qk+1 is calculated from the output of this latch (Q and Q).
It is determined by AND gates 25-28. In order to avoid unnecessary glitches, the output of each NAND gate is
After latching with , (latches 29-32), φ2 is selected with NAND gates (33-36). And NAN
A final lock output is obtained from the D gate 37.

In the case of the second configuration, when controlling with an accuracy of 1/4 fs, an oscillation frequency of 2 fs is sufficient, and a high-speed circuit is not required.

In addition to the above configuration, the oscillation circuit may be synchronized using a reference signal (horizontal synchronization signal) and a PLL.

(G) Effects of the Invention As described above, the present invention is effective because it can accurately control a clock signal synchronized with a reference signal without requiring high-speed operation.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the outline of the embodiment, Fig. 2 is a block diagram of a multiphase Cronk generation circuit, Fig. 3 is a block diagram of a selection circuit, Fig. 4 is a waveform diagram, Figs. 5 and 6. FIG. 2 is a block diagram showing a second embodiment. 3... Multiphase clock generation circuit, 4... Selection circuit.

Claims (1)

[Claims] (1) A clock signal generation circuit comprising means for generating a plurality of clock signals having different phases, and selection means for selecting one of the plurality of clock signals according to a reference signal.