JPH04270404A - Synchronizing circuit and synchronizing system - Google Patents

Abstract

PURPOSE:To obtain the synchronizing circuit to shorten output time reducing a logical amount. CONSTITUTION:The three steps of shift registers (SRL) using twophase clocks are linked, an asynchronous signal is inputted to the first step of the shift register (latch means) and latched, and a stable signal having no ringing is obtained by utilizing time difference between the two-phase clocks at the two D latches of the second step of the shift register. Then, a synchronized signal is outputted at the third step.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synchronization circuit for digital circuits.

0002

2. Description of the Related Art FIG. 3 shows an example of a conventional synchronization circuit. Here, we will take as an example a circuit that takes out an output for only one cycle. In the figure, 1 is a synchronization circuit, 2 is a JK flip-flop, 3a, 3b, 3c are D flip-flops, 4 is a gate, 5 is a data input terminal, 6 is a data output terminal, 7 is a clock A terminal, 8 is a clock B The signal at the data input terminal 5 is A, the Q output signal of the JK flip-flop 2 is B, the Q output signals of the D flip-flops 3a, 3b, and 3c are C, D, and E, and the signal at the data output terminal 6 is F. The signal at the clock A terminal 7 is defined as A, the signal at the clock B terminal 8 is defined as B, and the signal at the K input terminal of the JK flip-flop 2 is defined as N. A timing chart of each signal is shown in FIG.

Next, the operation will be explained. The signal A input from the data input terminal 5 is 1 synchronized with the clock A.
It is a pulse signal. The signal outputted to the data output terminal 6 is a one-pulse signal synchronized with the clock B. “H” for each signal is High level (2.0V or more), “
"L" is defined as a low level (0.8V or less). The region from 0.8V to 2.0V is called metastable and is an undefined region.The signal changes from "L" to "H" or "H".
In analog terms, it takes several seconds to change from to "L". In this case, metastability exists. J
When the input signal of K flip-flop 2 and the input signal B of D flip-flop 3a are in a metastable state, when clocks A and B are input, ringing occurs in each output signal B and C, and it takes several tens of ns to stabilize. It takes. Clock A and clock B are signals with different phases and periods. The D flip-flop 3a generates ringing in the output signal C when these two types of clocks change closely. The D flip-flop 3b is provided to latch the stable signal after ringing. The D flip-flop 3c and the gate 4 are differentiating circuits for outputting one pulse to the data output terminal 6.

0004

[Problems to be Solved by the Invention] Since the conventional synchronization circuit is configured as described above, the flip-flop 4
When data is output from the data input terminal 5 to the data output terminal 6, a minimum time of 2 clocks+α is required in terms of clock B. Here, α is the time difference between signals B and C as shown in the figure.

The present invention was made to solve the above-mentioned problems, and provides a synchronization circuit and a synchronization method that can reduce the amount of logic and shorten the output time.
The object of the present invention is to obtain a synchronization circuit that has almost no restrictions on the synchronizable frequency of asynchronous signals to be synchronized.

[0006]

[Means for Solving the Problems] A synchronization circuit according to the present invention has the following elements. (a) clock means for supplying a two-phase flock, (b
) latching means for latching the asynchronous signal; (c)
A shift register that inputs a two-phase flock and latches it when the latched asynchronous signal becomes stable.

Further, the synchronization method according to the present invention has the following steps. (a) A clock step that supplies two-phase clocks that do not turn on at the same time but turn on with a predetermined time lag; (b) a first latching step that latches a signal from an asynchronous signal with one of the two-phase clocks; (c) ) A second latching step that latches the signal from the first latching step with the other clock of the two-phase clock.

[0008]

[Operation] The synchronization circuit in this invention consists of a shift register consisting of two D latches, which supplies each clock of the two-phase clock to the synchronization circuit, and obtains a stable signal without ringing by using the difference between the clocks. This reduces the amount of logic used and shortens the time required to obtain stable output by one clock.

Furthermore, in the synchronization method according to the present invention, since the first latch process and the second latch process are operated by two-phase clocks supplied by the clock process, ringing can be prevented from occurring by using two two-phase clocks. A stable output signal is latched.

0010

[Example] Example 1. An embodiment of the present invention will be described below with reference to the drawings. Figure 1
, 1 is a synchronization circuit, 10 is a master clock terminal for clock A, 11 is a master clock terminal for clock B, 12a, 12b, 12c are SRLs (shift registers), 13a, 13b are D latches, and 4a, 4b are gates. It is. The other synchronization circuits 2, 5, 6, 7, and 8 function the same as or equivalent to conventional synchronization circuits. SRL1
2a, 12b, 12c are two D latches 13a, 13
It is composed of b. The SRL 12a is an example of the latch means of the synchronization circuit according to the present invention. The master clock terminal 11 of the clock B is connected to the clock input T of the D latch 13a of the SRL 12b, and the slave clock terminal 8 of the clock B is connected to the clock input T of the D latch 13b. This is an example of a clock. Similarly, the clock input T of the D latch of the JK flip-flop 2 is connected to the master clock terminal 10 of the clock A and the slave clock terminal 7 of the clock A, respectively. D flip-flops 3a and 3c are SRL
12b and 12c are substituted. JK flip flop 2
is substituted by the SRL 12a and the gate 4a.

FIG. 2 shows a timing chart of the synchronization circuit. Signals A, B, H, H, and N are the same as before. Signal AM is the master clock signal of clock A,
Master clock signal of signal BM clock B, signal AS
is a slave clock signal of clock A, signal BS is a slave clock signal of clock B, and signal L is an output signal of D latch 13a in D flip-flop 3a.

Next, the operation will be explained. First, the JK flip-flop 2 latches and generates the signal B from the asynchronous signal A. Next, the D flip-flop 3a (or SRL 12b) is composed of D latches 13a and 13b, and the D latch 13a executes the first latch step of the synchronization method of the present invention, and the D latch 13b executes the first latch step of the synchronization method of the present invention. Execute the second latching process. That is, when the input signal L of the D latch 13a is metastable, ringing occurs in the output signal L. However, the signal L is stabilized by the action of the two-phase clock as described above before the D latch 13b operates, so the output signal H of the D latch 13b becomes a stable output. The D latch operates while the clock is “H”.
It outputs the same data as the input data, and holds the input data when changing from "H" to "L" while it is "L". Therefore, the following two conditions are required as conditions for clock B, which is a two-phase clock, to be supplied to the SRL 12. 1. Master clock BM of clock B and clock B
The slave clock BS of both devices must not become “H” at the same time. 2. The interval between the master and slave clocks is longer than the time required for the ringing of the output of the D latch 13a to become stable. Due to these two conditions, ringing disappears and the signal of the D latch 13a becomes stable by the time the D latch 13b operates. In Figure 2, β is 2
It is sufficient to supply two-phase clocks that indicate the time difference until the phase clocks turn on and satisfy β>ringing time. Note that the D flip-flop 3c and the gate 4b are differentiating circuits equivalent to the conventional ones.

In the above circuit, from the data input terminal 5 to the data output terminal 6, the clock B is converted to a slave clock by 1 clock + α. This saves one clock compared to the conventional method.

Furthermore, when the synchronization circuit of the present invention is used in an LSI or the like, the logical amount per SRL and the logical amount per D flip-flop are equivalent, so the number of flip-flop stages is reduced from the conventional four stages to three stages. It is expected that the amount of logic will be saved by doing this.

In the synchronization circuit of the present invention, there is almost no frequency restriction on the data input terminal 5 in order to output a stable output to the data output terminal 6. In other words, the operating limit frequency of the first stage D latch inside the JK flip-flop 2 is the maximum frequency. Conversely, there is no minimum frequency limit.

As described above, in the above embodiment, the synchronization circuit and synchronization circuit synchronizes asynchronous signals of different phases and different periods with stable output by connecting three stages of SRLs (shift registers) using two-phase clocks. A synchronization circuit has been described which is characterized by having almost no restrictions on the synchronization method and the frequency at which asynchronous signals can be synchronized.

Example 2. Although SRL is used in the above embodiment, by inputting an inverted clock of clock B to the D flip-flop 3a of the conventional synchronization circuit, it is possible to shorten the time until output by one clock. However, in terms of logic amount, it is equivalent to the conventional synchronization circuit and cannot be saved.

Example 3. Furthermore, in the above embodiment, the circuit was designed to obtain a stable output for one pulse, but if it is only necessary to maintain a stable output level, it can be realized by removing the differentiating circuits 3c and 4b. . That is, SRL12C may be deleted.

Example 4. Further, in the above embodiment, the SRLs 12a, 12b, 12c
Embodiment 3. was connected in three stages. As mentioned in S.
Only RL12a and 12b may be used, but SRL12a is
The JK flip-flop 2 shown in the conventional example may also be used. In other words, the first stage only needs to have a means to generate a signal port, and in this sense, it is sufficient to have a first stage latch means to latch the asynchronous signal.

[0020]

[Effects of the Invention] As described above, according to the present invention, since the synchronization circuit is constituted by a shift register, it is possible to shorten the time until output by one clock and save the logical amount equivalent to one flip-flop. be.

[Brief explanation of the drawing]

FIG. 1 is a logic diagram showing a synchronization circuit according to one embodiment of the invention.

FIG. 2 is a timing chart diagram of FIG. 1;

FIG. 3 is a logic diagram showing a conventional synchronization circuit.

FIG. 4 is a conventional timing chart.

[Explanation of symbols]

1 Synchronization circuit 2 JK flip flop 3a, 3c D flip-flop 4a, 4b Gate 5 Data input terminal 6 Data output terminal AS Clock A slave clock BS Clock B slave clock AM Clock A master clock BM Clock B master clock 12a, 12b, 12c SRL 13a, 13b D latch

Claims (2)

[Claims] Claim 1: A synchronization circuit (a) having the following elements:
(b) clock means for providing a two-phase clock;
A latch means for latching an asynchronous signal, (c) inputting the signal from the latch means and the two-phase signal from the clock means, and latching and outputting the signal from the latch means when the signal from the latch means is stable. shift register. Claim 2: A synchronization method (a) comprising the following steps:
(b) a clock step for supplying two-phase clocks that are turned on at predetermined intervals and not turned on at the same time; (b)
A first latching step of latching the asynchronous signal with one of the two-phase clocks, (c
) A second latching process that latches the signal from the first latching process with the other of the two-phase clocks.