JPS60525A - Control circuit of clock signal - Google Patents

Abstract

PURPOSE:To obtain a clock signal controlling circuit provided with a clock signal stoppage delaying function by suppressing a clock stopping operation by the number of preset cycles of a clock signal by a control signal after a clock stop signal is inputted. CONSTITUTION:When a clock signal CLK is inputted into FFs 1a and 1b and a clock stop signal STOP is inputted into the FF1a asynchronously to the CLK signal, H-level signals are inputted into an AND gate from the Q2 output of the FF1b by the prescribed number of cycles of the CLK signal. A control signal inputted next is identified by a decoder 2 and the signal is held by the number of cycles of the CLK signal previously set in FFs 1c and 1d, then, each output of the decoder 2, FF1c, and FF1d is inputted into an NOR gate. When each output of the decoder 2, FF1c, and FF1d is at H level, the output of the NOR gate is at an L level, and the signal STOP from the Q2 output of the FF1b is suppressed. After each input signal of the NOR gate attains to L level, the signal STOP is outputted from an OR gate.

Description

DETAILED DESCRIPTION OF THE INVENTION tal Technical Field of the Invention The present invention relates to the control of clock signals in data processing systems, and particularly to the transmission stop function thereof.

(bl) Technology's I!f data processing system is usually constructed from a logic circuit consisting of a large number of semiconductor devices.The logic circuit is composed of interlocking circuit elements such as NAND and NOAH and registers.

A data processing system, such as a central processing unit (CPU), consists of a group of logic circuits for storing data and a data transfer path connecting them. data block,
It is composed of a control block consisting of a group of logic circuits that controls the transfer sequence within the data block, the type of operation in each operation cycle, the operation execution sequence, etc. In order to facilitate control of these logic circuit groups, particularly sequential circuits, the logic circuits are controlled at a constant repetition period or in synchronization with the L° turn signal ζ.

(C1 Prior Art and Problems - F) The clock signal in a data processing system is basically sent out continuously and is used for tlti control of the synchronous operation of each logic circuit. Therefore, the clock signal may be partially controlled to open or close directly. Queuing is applicable when stopping the execution of a program by controlling the volume of the program, or when switching to a single step mode in which instructions are executed step by step in order to check the operating status of a logic circuit every cycle of operation. Stop the clock signal applied to the logic argument.

Conventionally, when a stop signal for this stop operation is applied at random, the target logic argument may malfunction depending on the timing with the clock signal. A bow/stage is commonly used that synchronizes with the signal and applies it to the logic circuit to be stopped. FIG. M1 is a block diagram of a conventional clock signal control circuit equipped with a clock signal stop function, and FIG. 2 is a time chart thereof. In the figure, la and lb are D-type flip block circuits (k'F), and OR is a logic tree 1 circuit. Clock stop signal (STOP) is FF
When the data input (1't) of 1a is manually input, it is set at the rising edge of the clock signal ((J, to) by the next timing, the positive output (Q,) is triggered, and the data input (1't) of li'F1b is set. FFxb operates in the same way, and its positive output (Qz) is applied to Oit, so the clock stop signal is applied to the rising edge of the clock signal in the rising interval. cycle 1
．． A new target clock signal (CLK, ) is obtained in which the clock signal is stopped at cycle 2.3, which is delayed by one cycle for a two-cycle period of 2.2.

On the other hand, there are logic circuits such as combinational circuits, which have a simple configuration and operation, fast switching operation, and whose output data is determined within one cycle of a clock signal when input data is applied, and sequential circuits, which have simple configuration and operation, and have fast switching operations. There are cases in which the determination of output data upon application of the clock signal extends over the next cycle or multiple cycles of the clock signal. Also, due to control issues, in some cases, such as when operating a memory circuit, when a software write command is issued, the circuit is
Write control signal (wg) and address selection signal (Al) to be added to lJ + write data (1) AT A
Compared to the case where the WE generation is easily executed in the case of IN), the latter may be delayed due to the computation time. Therefore, immediately after the write command, the clock signal is stopped and AI) Do, n or/and 1) A'l'AIN are not generated.
There are cases where o, n, and IJATAIN are accessed in an undefined manner and execute a write operation, damaging other write data and causing a failure such as system down.

(dl Purpose of the Invention) In order to eliminate the above-mentioned drawbacks, the present invention has the function of directly stopping the clock signal even if the clock stop signal is applied. An object of the present invention is to provide a clock signal control circuit having a function of suppressing a stop function in a clock signal for a required number of cycles to continue the clock signal, and then activating the stop function to stop the clock signal.

tel M configuration of the invention The purpose of this is to generate a synchronization stop signal in synchronization with a clock signal separately received in conjunction with a clock stop signal input to Jμ synchronization, and to escape the clock signal for a period corresponding to the input of the clock stop signal. decoding means for identifying a control signal in a clock signal control circuit for stopping a clock signal, and means for holding an output signal of the decoding means in accordance with the number of cycles of a clock signal for which a synchronous operation is to be continued upon generation of the control signal.

and a first gate means for obtaining a NOR of the output signal of the holding means, and a second gate means for obtaining an AND of the output signal of the first gate means and the synchronization stop signal, and the control circuit receives the clock signal, stops the clock, receives the control signal, and obtains the output signal of the control signal by the decoding means. By providing a click signal control circuit which is characterized in that it suppresses the clock signal from being stopped for a set number of cycles, and continues sending out the clock signal for the set number of cycles regardless of the human power of the clock stop No. 45. It can be achieved.

(f+ Embodiment of the Invention An embodiment of the invention will be explained below with reference to the drawings.

FIG. 3 shows a block diagram of a clock signal control circuit with a clock signal stop/delay function in an embodiment of the present invention. In the figure 18. ib, IC, ld (a flip-flop circuit (FF); 2 is a decoder for identification by a control signal; OR is an OR circuit; ANI) is an AND circuit; NOR is an NOR circuit. Constituent members of the face wood embodiment having the same reference numerals as the conventional one in FIG. 1 have the same characteristics and functions as the conventional one. Therefore, when the corresponding control signal is not input and the output signal of the decoder 2 is not sent out, the output of the NOR operated by the FFIC and td is kept constant at an unmanned high level. Q of FF1b corresponding to 1 to 4, a high level is obtained as a synchronization stop signal in cycles 2 to 5 with a one-cycle delay as an output signal, so the clock signal between cycles 2 to 5 is similar to the conventional operation (not shown in the figure). However, in the configuration of one embodiment of the present invention, the control signal is input, the output signal of the decoder 2 is obtained in cycle 2, and the FFs 1c and ld are set to hold the 2nd cycle. If the output signal of NOR is provided, a low level can be obtained between cycles 2 to 4, so the synchronization stop signal from Q! of FF1b input to AND is suppressed during cycles 2 to 4. , the cycles in which the clock signal stops are 2 to 4 from cycles 2 to 5.
There is only cycle 5 excluding . Furthermore, decoder 2 and F
There is no overflow in the operation timing of F1c and ld, and depending on the variation in switching time at the switching timing, a minute noise pulse may be superimposed on the output signal of N (JR, AND) shown in the figure, but the high level period of CLKt It is generated only in CLK2 and is not superimposed on CLK2.

Since this embodiment is configured in this way, when the clock signal is stopped in advance, it is delayed by a necessary cycle, and for example, the clock signal is stopped immediately after the write command in the aforementioned storage circuit, resulting in a system down. Necessary control can be achieved without any hassle. Although one control signal has been described above, it goes without saying that the setting of a plurality of control signals or the number of delay cycles required for delay can be similarly implemented arbitrarily.

(2) As described in detail, according to the present invention, in addition to the conventional clock signal stop function, when a preset control signal is applied together with a clock signal and a stop signal, the clock signal is clocked for the required number of cycles according to the setting. It is possible to provide a useful clock control circuit with a stop function that suppresses the stop function in the signal, continues the clock signal, and then activates the stop function.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional clock signal control circuit, FIG. 2 is a time chart thereof, FIG. 3 is a block diagram of a click signal control circuit in an embodiment of the present invention, and FIG. 4 is a time chart thereof. be. In the figure la
, lb, Ic, ld are flip-flop circuits (FF),
2 is a decoder, OR is a logical sum circuit, AND is a logical product circuit, and N (JR is a negative logical product circuit).

Claims (1)

[Claims] Control No. 18 is implemented in a clock control circuit that generates a synchronization stop signal in synchronization with a clock signal that is separately received in conjunction with a clock stop signal that is input asynchronously, and stops transmitting the clock signal for a period corresponding to the input of the clock stop signal. decoding means for identifying; means for holding the output signal of the decoding means in accordance with the number of cycles of the clock signal to continue synchronous operation upon generation of the control signal; and negation of the output signal by the holding means in the case of the decoding means. The control circuit comprises a first gate means for obtaining a fill-in sum, and a second gate means for obtaining an AND of the output signal of the first gate means and a @routing stop signal, and the control circuit is configured to perform a clock signal. ＼Clock 1 is stopped and the control signal is received and the decoding means 0 is received.
When the output signal of the clock control is obtained, the holding means and the first and second gate means suppress the stop operation by a preset number of cycles of the clock signal, and input the clock stop signal. A clock signal control circuit whose purpose is to continue sending a clock signal for a set number of cycles regardless of the conditions.