JP2583501B2 - Data transmission circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit, and more particularly to a data transmission circuit used as a component of a network that enables data transmission between a plurality of asynchronous systems, for example. is there.

[Conventional technology]

Conventionally, as a method of performing data transmission between asynchronous systems, a method of using a FIFO (first-in first-out) memory as a buffer between systems has generally been used. However, since this FIFO memory only has a data buffer function, if such a FIFO memory is used for data transmission between asynchronous systems, a plurality of asynchronous systems can be connected only in series. Therefore, the entire system connected to the FIFO memory merely constitutes a pipeline processing mechanism by a simple cascade connection, and there is a problem that the degree of freedom is extremely low.

On the other hand, the present applicant has already developed a data transmission device that can provide a large degree of freedom when constructing an entire system by connecting asynchronous systems. Hereinafter, this data transmission device will be described.

FIG. 5 is a diagram showing a system of the data transmission device. In the figure, 5 is a data transmission path, 2a to 2c are branch parts,
3a to 3c are merging sections, 1a to 1c are processing elements, 4 is an interface, and packet data flowing in from an external system via the interface 4 is processed while circulating between the network elements 3a and 2a to 2c. 1c and distributed processing by the processing elements 1a to 1c.
The processing results are collected by 3b and 3c and sent out again to the external system via the interface 4.

In this data transmission device, an asynchronous free-running shift register is used as the data transmission line 5. This asynchronous free-running shift register is a register in which input data is automatically shifted in the output direction without using a shift clock, provided that the next-stage register is empty. Has a buffer function. The asynchronous self-running shift register is configured as shown in FIG. 6, and each stage includes a parallel data latch L and a two-stage transfer control element (hereinafter, referred to as a "transfer control element") for applying a rising edge trigger to the parallel data latch. , C elements). Each of the C elements is configured as shown in FIG. 7, for example, and outputs C, (which is an inverted signal of C) for two inputs X and Y, but operates according to the following logical value table. . In the following logical value table, “1” and “0” indicate the high level and the low level of the signal value, respectively.

When the C output of the C element is 1, the gate of the parallel data latch corresponding to this C element is opened, and the data of the preceding stage is propagated.
It is assumed that valid data is held. Conversely, when the C output of the C element is 0, it is assumed that the gate of the parallel data latch corresponding to this C element does not open, does not propagate data of the preceding stage, and does not hold valid data. That is, C
Only the parallel data latch corresponding to the C element whose output is 1 holds valid data, and the parallel data latch corresponding to the C element whose C output is 0 holds no meaning even if it holds data. Data.

Here, in the above example, the transfer control circuit is a two-stage C element C ₁ , C
_Since it is composed of _two , the following four states exist according to the output states of the two C elements.

That is, when the C output (g,) of at least one of the C elements C ₁ and C ₂ is 1, the data latch holds significant data, so that the two C elements C ₁ and C ₂ Data retention / non-retention is represented as follows by the combination of the outputs g and r.

Hold: (g, r) = (1,0) (0,0) or (1,1) Non-hold: (g, r) = (0,1) These four states are input (G, R) 8th with the change of
Transition as shown.

Hereinafter, this state transition will be briefly described. In the data non-hold state (g, r) = (0, 1), the state is maintained as long as the transmission request G from the preceding stage is 0 (state transition a in FIG. 8). In this state, if there is a transmission request from the preceding stage (G = 1), the data from the preceding stage is latched (r =
1) Transition to the data holding state (g, r) = (0, 0) and data being latched in its own stage (r = 0)
To the preceding stage (state transition b). In this case, if there is no signal indicating “data empty” (R = 1) from the next stage, the state is maintained (state transition c).

In this state, when a signal (R = 1) indicating “data available” is input from the next stage, a response is returned to the next stage (g =
1), transition to state (g, r) = (1,0) (state transition d). In this case, the state is maintained as long as the transmission request G from the preceding stage is 1 (state transition e), and when the transmission request G from the preceding stage becomes 0, the state (g, r) = (1, 1) (State transition f), and returns a response to the previous and next stages. In this case, the first-stage C element C ₁ outputs “empty” (r = 1), but the second-stage C element C ₂ still outputs “data holding”.
Since the output is (g = 1), data from the preceding stage is not accepted.

In this state, if the response R from the next stage is 0, that is, if a signal indicating that the data of the own stage has been transferred to the next stage is input, the state transits to the first state (g, r) = (0,1). (State transition g,
h), it is ready to accept data from the previous stage.

[Problems to be solved by the invention]

However, in the data transmission path as described above, since two C elements are arranged for one stage of the data latch, the number of elements increases and the circuit scale increases. Further, there is a problem that the data transfer capability (data throughput) per unit time is small, and there are four internal states represented by a combination of outputs of two C elements, which is redundant.

Further, since the internal state r indicating data retention and the data latch signal are the same signal, for example, when data is jammed on the line, as shown in the data transmission line in FIG. 6, each data latch signal (internal All state signals r) are 1
It may be. In such a state, when a transparent type data latch that outputs an input state when the data latch signal is 1 is used, there is a possibility that the data is connected and the preceding data is rewritten. Therefore, in order to prevent this, it is necessary to use an edge-triggered type data latch in which the data latch signal retains and outputs the input state at the point where the data latch signal changes from 0 to 1, which is compared with a transparent data latch. Therefore, there is a problem that the circuit scale is large.

The present invention has been made in view of the above circumstances, and has as its object to obtain a data transmission circuit having a small circuit size and a large data throughput.

[Means for Solving the Problems] The data transmission circuit according to the present invention comprises a plurality of stages of data storage means, and one data storage unit for each of the plurality of stages of data storage means.
And a shift register including a plurality of stages of transfer control means for controlling the data storage means of the own stage in accordance with a control signal from the transfer control unit of the adjacent stage. The internal state signal next to the stage and the control signal output to the adjacent stage include the state of the transmission request signal G from the previous stage, the state of the signal R indicating the empty or clogged state of data from the next stage, and the state of the own stage. And the current state Q of the internal state signal q corresponding to whether or not the data storage means holds significant data, the internal state signal q and the output signal g, r of the own stage are obtained according to the following state transition table. It is configured to be controlled.

[Operation] In the present invention, one transfer control means is provided for one stage of the data storage means, so that the circuit scale is small and the data throughput is large, and the data holding information is one-to-one with the data latch signal. Since the data is stored by the corresponding internal state signal, the data latch signal does not need to hold “1” during the entire data holding period, and when data on the line is jammed, the data latch signal of the jammed line is latched. Since all the signals are in the state of "0", it is possible to use a transparent latch having a small circuit scale as the data latch.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of two stages of a data transmission circuit according to one embodiment of the present invention. In the drawing, L is a data latch as data storage means, and in this embodiment holds 40-bit parallel data. It is configured as follows. Reference numeral 50 denotes a transfer control circuit comprising one C element (hereinafter simply referred to as a C element). This circuit controls the current state Q of the internal state signal
And the state of the transmission request signal ▲ ▼ (data latch signal: Gi) from the adjacent stage and the signal Ri indicating the empty / busy state of the next stage data, the output signals ▲ ▼ and ri and the next internal state of the own stage. q is controlled. Specifically, as shown in the figure, two-input NAND circuits 51, 52, and three-input NAN
It comprises a D circuit 53 and inverter circuits 54 to 56.

Next, the operation will be described focusing on the C element 50 with reference to the state transition diagram of FIG. Although positive logic is used in the state transition diagram and negative logic is used in the circuit diagram, the meaning of each signal is the same. For example, q = 1 in the transition diagram and ▲ ▼ = 0 in the circuit diagram indicate that data is held. Is shown.

In FIG. 1, in the initial state in which the signal ▲ ▼ is inputted, no significant data is held in each data latch, and the internal state signal ▲ ▼ and each input / output ▲
The signals ▼, ▲ ▼, ▲ ▼, and ri are all 1. In a state where significant data is not held in such a data latch (▲ = 1), unless there is a transmission request from the previous stage, that is, unless ▲ becomes 0, a data reception response (Ri ), The state is maintained (see state transition A in FIG. 2), and the outputs ▼, ri to the adjacent stage remain 1.

In this state (▲ = 1), if there is a transmission request from the previous stage (▲ = 0), the transmission request to the next stage is not made (▲
▼ = 1), a signal (ri = 0) indicating that the own stage is “data clogging” is output to the preceding stage, and a transition is made to the “data holding” state (state transition B). That is, when ▲ = 0, the output of the NAND circuit 52 becomes 1, and when ▼ = 1, the output is inverted by the inverter circuit 55.
The output of the NAND circuit 51 is 1 irrespective of the state of Ri, so that the internal state signal becomes a state indicating "data holding" (デ ー タ = 0). The data transmitted in this manner is latched by the data latch Li, and information indicating that the latch Li holds data is signal ▲.
Stored in ▼.

In this state of “data holding” (▲ = 0), unless the signal from the next stage becomes “empty” (Ri = 1), the state (▲) regardless of the transmission request signal ▼ from the previous stage. ▼ = 0) is held (see state transition C in FIG. 2). In other words, if the data at the next stage is
Since Ri = 0, the output of the NAND circuit 51 becomes 1. Also, since ▲ ▼ = 0, NA regardless of the state of Gi
The output of the ND circuit 52 becomes 1, whereby the output of the NAND circuit 53, ie, the internal state signal ▼ becomes 0, and the circuit is held.

Next, when a signal indicating “empty” is input from the next stage in the state of “data holding” (▲ = 0) (Ri = 1), a transmission request to the next stage is made (▲ = 0). , Outputs a signal (ri = 0) indicating that the own stage is "data clogged" and the internal state signal is "no data"
(▲ = 1) (see state transition D in FIG. 2). That is, when the next stage is “empty”, the signal Ri becomes 1 and the output of the NAND circuit 51 becomes 0 because ▲ = 0. At this time, since the internal state signal 信号 = 0, the output of the NAND circuit 52 becomes 1 regardless of the state of the transmission request signal ▼ from the previous stage, and therefore the internal state signal ▲
▼ changes to 1 to indicate “no data”.

Thus, in the present embodiment, the transmission request signal G
And a signal R indicating "empty" and "data jam" from the next stage and the internal state signal at that time, the internal state q
And the outputs g, r to the adjacent stages are controlled, and these are summarized as shown in FIG. Then, when a Carnot diagram is created from the above state transition diagram, the result is as shown in FIG. 4, from which the following logical expressions can be derived.

= QR + (+ R) Here, since GR is redundant, the circuit shown in FIG. 1 is configured to satisfy this logical formula in consideration of the minimum cover q = QR + GQ.

In this embodiment, since the transfer control circuit is constituted by one C element for one stage latch, the number of elements is reduced, the circuit scale is reduced, and the data throughput is increased. For example, in the conventional circuit shown in FIG. 6, the logic gate is delayed by one gate and the inverter is reduced by 1/2.
Assuming that the logic gate delay is 9 gate delays per data, the circuit of this embodiment has a 7 gate delay, and the data throughput is correspondingly increased. Also, the number of internal states is two (1 bit), and the redundancy is improved as compared with the conventional one. Also, the reset circuit can be formed by a very simple circuit.

Further, in the case where the C elements are connected in multiple stages, the transmission request input G from the preceding stage when the target stage does not hold data (q = 0).
Becomes "1", the state shifts to the data holding state (q = 1), and a signal r = 0 indicating that the own stage (stage of interest) is "data clogging" is output from the previous stage. G remains in response to this, and cannot be G = 1 as long as the target stage is in a data holding state, that is, r = 0.

Therefore, of the inputs (G, R) for transitions C and D shown in FIG. 2, (1, 0) and (1, 1) are redundant inputs that cannot occur. Therefore, the state transition table shown in FIG. 3 can be rewritten as shown in FIG. 9, and the state transition for the redundant input is not specified.

Further, in the present embodiment, when the data is stopped and the transfer is stopped, the information of the data holding is stored in the internal state signal q, so that the latch signal G may be at a low level. It is not necessary to use an edge trigger type latch having a large circuit scale, a transparent latch can be used, and the circuit scale can be further reduced.

Note that, of the logical expression = QR ++ R, which represents the function of the C element of the present invention, R is redundant and therefore omitted in the logic circuit of the above embodiment (FIG. 1). In order to avoid this, it is also possible to construct a circuit including this term, and make a circuit as shown in FIG.

In the embodiment of FIG. 10, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and among the two-input NAND gates 51, 52, and 57, the gate 57 is the gate corresponding to the above-described GR. The basic circuit operation is the same as that of the C element 50 shown in FIG.

Further, it can be understood that the logical expression = QR ++ R representing the function of the C element of the present invention is equivalent to q = G + G + Q by taking the part of q = 1 (= 0) in FIG. FIG. 11A shows a circuit configured to satisfy this logical expression. This circuit is composed of two-input NAND gates 61 to 63 and a three-input NAND gate 6.
4, a NOR gate 65, inverters 66 and 67, and a NAND gate 68 having a negative logic input. Also in this circuit,
The three-input NAND gate 64 can also be realized by a series connection of a wired OR and an inverter as shown in FIG. 11 (b).

Further, in the above equation [q = G + G + Q], GR is a redundant term, and a circuit corresponding to the minimum covering q = G + Q excluding this term is also possible. That is, FIG. 11 (a)
, The two-input NAND gate 62 can be omitted.

FIG. 1 shows an example in which the initialization of each C element is performed simultaneously by the master reset signal (▲). However, even if the master reset is omitted, the 3-input NAND gate 53 can be changed to a 2-input NAND gate. In the data transmission circuit according to the present invention, the R input of the last stage is held at the high level for a considerable time so that the blank reading is continuously performed and the initialization is completed. No additional circuit is required for initialization.

Further, in the state transition table of FIG. 9, the transitioning signal is assigned to the safe side so as to indicate the data holding state, but the period signal r is normal if there is an output determined only in a stable state that is not in transition. Since data transmission is performed, Q is 0
The output r during the transition corresponding to the change from → 1 or 1 → 0 can be a redundant output, and the state transition table in FIG. 9 can be rewritten into the state transition table shown in FIG.

From the state transition table of FIG. 12, it can be seen that a simple circuit in which r is all assigned to 1 when Q = 0 can be realized. That is, the circuit configuration shown in FIG. 13 in which the inverter 56 is omitted in the circuit shown in FIG.

The circuit shown in FIG. 14 is obtained by omitting the master reset of the circuit shown in FIG. 13 and adding a two-dot chain line,
This is to prevent the oscillation phenomenon that occurs when the pulse width of the transmission request signal 長 い is long, that is, the phenomenon that two or more output signals ▼ are generated for one transmission request pulse ▼. is there.

That is, as shown in the timing chart of FIG. 16, when the transmission request signal ▲ ▼ pulse width is long, the time t ₁ and
Since the signal ▲ ▼ is not yet in the non-active state ( "1") at a time point t _2, the internal state signal ▲
▼ (ri), the output signal ▲ ▼, and the like change their logic levels, causing an oscillation phenomenon.

Therefore, in the embodiment shown in FIG.
▼ is input not only to the NAND circuit 52 but also to the NAND circuit 51,
Propagation of the output signal ▼ to the next stage is suppressed until the signal ▼ changes to the non-active state, that is, until the rising time T of the signal ▼ as shown in FIG. Even when the pulse width of 幅 is long, the oscillation phenomenon as shown in FIG. 16 can be prevented.

Further, in the present embodiment, it is possible to increase only the propagation delay time Tf of the transmission request signal ▲ ▼ in the data transfer direction while keeping the propagation delay time Tr of the response signal ri in the direction opposite to the data transfer direction constant. Therefore, when Tr << Tf and Tr is relatively negligible, the number of data latch stages occupied by one word approaches one stage.

Thus, considering the so-called pipeline processing in which processing is performed between data latch stages by increasing Tf within a range that satisfies the required processing rate, the size of processing performed between data latch stages is reduced. Since the number of pipeline stages can be increased, the number of pipeline stages is reduced as a whole.

 The use efficiency of the data latch is improved.

The effect is obtained. This effect can be obtained in each of the above embodiments.

 Here, this effect will be described in detail.

In general, in a transfer path in which transfer control circuits configured using speed independent logic circuits as shown in the above embodiments are connected in multiple stages, the delay time per stage of the transmission request signal in the data transfer direction is represented by Tf, Assuming that the delay time per one stage of the occupied signal in the direction opposite to the transfer direction is Tr, the data sequence input with a period T of (Tf + Tr) or more is sequentially transferred. It is also shown in the paper "Elastic Storage Devices with Asynchronous Delay Lines" published in IEICE Magazine Vol. 50, No. 11, pp. 84-91.

In a data transfer path composed of m stages, the period T
When data is input / output at (T ≧ Tf + Tr), the effective number of buffer stages in this transfer path is (Tf × m) / T (1). This is obvious when considering that the time from the input to the input data arriving at the output is Tf × m, during which one data is input every time T.

The above equation (1) indicates that the smaller the closing cycle T, the larger the effective number of buffer stages. That is, the maximum value is (Tf × m) / (Tf + Tr) (2). Equation (2) is So that Tr << Tf, and if Tr can be ignored,
It can be seen that the effective number of buffer stages gradually approaches m stages.

On the other hand, when the transfer control circuit 50 shown in FIG. 14 is modified, the transfer control circuit 50 is shown as shown in FIG. 17 (a), and propagates in the data transfer direction, that is, four gate delays from the input to the output. It can be seen that propagation, that is, operation from the R input to the r output with two gate delays. If this is indicated by the above-mentioned time Tf, Tr, Tf = ++++ (4a) Tr = + (4b) where is the logic gate delay.

From equations (4a) and (4b), it can be seen that the inverter delay is included in Tf but not in Tr, and
By increasing the inverter delay as compared to the other delays as shown in FIG. 7B, the ratio of Tr to Tf (Tr / Tf) decreases, and from the above equation (3), the number of effective buffer stages approaches m. You can see that.

Therefore, as shown in FIG. 18, if the control circuit of the present invention is used as a data transfer control circuit of a pipeline processing mechanism for improving a processing amount by dividing a series of processing into multiple stages, data input of required specifications can be performed. For a rate T, T
By increasing Tf in the range of> Tf + Tr, the propagation delay time per pipeline stage increases, so the critical path of the combinational logic 70 becomes longer, and the number of pipeline stages can be reduced as a whole. The hardware scale can be reduced by omitting the corresponding data latch unit and the like. In particular, in the case of performing the loop pipeline processing as shown in FIG. 19, by setting Tf >> Tr, the number of data existing in the system can be made substantially equal to the number of pipeline stages. Buffer mechanism can be effectively used.

That is, if Tf >> Tr in each of the above embodiments, the buffer mechanism can be used effectively, and although it is an asynchronous data transfer circuit that does not use a clock, it is almost the same as a synchronous circuit. The effect is obtained.

In each of the above embodiments, the internal state of the transfer control circuit and the output to the adjacent stage are controlled by two inputs from the adjacent stage and the internal state of the own stage.
Since the transfer control circuit for the stage is constituted by one C element, there is an effect that the circuit scale can be reduced and the operation can be speeded up.

Further, in each of the above embodiments, the transfer control circuit can change the propagation delay time Tf in the data transfer direction independently of the propagation delay time Tr in the opposite direction, so that the range that satisfies the required processing rate is satisfied. By increasing the above Tf, the size of the processing executed between the data latch stages in the so-called pipeline processing can be increased, the number of pipeline stages can be reduced as a whole, and the use efficiency of the data latch can be improved.

Further, in each of the above embodiments, initialization can be performed only by keeping the R input of the last stage at a high level in the data transmission path, and therefore, an additional circuit for initialization is not particularly required. .

〔The invention's effect〕

As described above, according to the data transmission circuit of the present invention, a plurality of stages of data storage means and one for each of the plurality of stages of data storage means are provided. A shift register comprising a plurality of stages of transfer control means for controlling the data storage means of the own stage in response to a control signal from the own stage, wherein the transfer control means comprises: an internal state signal next to the own stage; The control signal to be output to the first stage is the state of the transmission request signal G from the previous stage, the state of the signal R indicating the empty or clogged state of data from the next stage, and the data storage means of the own stage holds significant data. In accordance with the current state Q of the internal state signal q corresponding to whether or not the internal state signal q and the output signal g, r of the own stage according to the following state transition table:
Is controlled, whereby one transfer control means can be provided for one stage of the data storage means, whereby the circuit scale can be reduced and the operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transmission circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a state transition thereof, and FIG. 3 is a diagram showing input / output signals and internal state signals of a transfer control circuit in the data transmission circuit. FIG. 4 is a diagram showing the relationship, FIG. 4 is a Carnot diagram derived from FIG. 3, FIG. 5 is a diagram showing the overall configuration of a data transmission device already developed by the inventor of the present invention, and FIG. , FIG. 7 is a diagram showing a configuration example of a C element applied to the data transmission line, FIG. 8 is a diagram showing a state transition of a transfer control circuit used in the data transmission line of FIG. FIG. 10 is a diagram showing a state transition table obtained by rewriting the state transition shown in FIG. 3, and FIGS. 10 and 11 (a) and (b) are diagrams showing another embodiment of the present invention. The figure shows the state transition table obtained by rewriting the state transition table shown in FIG. 9, and FIG. 13 shows the state transition table shown in FIG. FIG. 14 shows another embodiment of the present invention obtained from the transition, FIG. 14 shows another embodiment of the present invention obtained by modifying the embodiment of FIG. 13, FIG. 15 and FIG. Is a diagram for explaining the operation and effect of the embodiment shown in FIG. 14,
FIGS. 17 (a) and (b) are logic circuit diagrams obtained by modifying the embodiment shown in FIG. 13, and FIGS. 18 and 19 are diagrams showing application examples of each embodiment. L: data latch, 50: transfer control circuit (C element),
G, R: transfer control input, g, r: transfer control output, q: internal state signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Katsuhiko Asada 4-1-1-4 Higashi-Namba-cho, Amagasaki-shi (56) References JP-A-61-190627 (JP, A) JP-A-62-9448 (JP, A )

Claims (2)

(57) [Claims] 1. A data storage means for a plurality of stages, and one for each stage of the data storage means for a plurality of stages, wherein the data of its own stage are provided in response to a control signal from a transfer control unit of an adjacent stage. A shift register comprising a plurality of stages of transfer control means for controlling the storage means, wherein the transfer control means comprises:
The control signal output to the adjacent stage includes the state of the transmission request signal G from the previous stage, the state of the signal R indicating the empty or clogged state of the data from the next stage, and the data storage means of the own stage stores significant data. The internal state signal q and the output signals g and r of the own stage are controlled according to the current state Q of the internal state signal q corresponding to whether the signal is held or not according to the following state transition table. Data transmission circuit. 2. The data transmission circuit according to claim 1, wherein said transfer control means includes: a transmission request signal G from a preceding stage; a signal R indicating a vacant or jammed state of data from a following stage; An inverted signal of the internal state signal Q corresponding to whether or not the data storage means of the stage currently holds significant data is input, the current internal state signal Q is “data holding”, and the signal R is “ Vacant "
A first gate for outputting a first control signal g for a transmission request to the next stage on condition that the transmission request signal G is in a non-active state; and a transmission request signal G, And the current internal state signal Q as an input, and outputs a second control signal which becomes active when at least the internal state signal Q is "no data" and the transmission request signal G does not request transmission. A second gate, having the first and second control signals as inputs, at least when the current internal state signal Q indicates “no data” and the transmission request signal G indicates an active state, And the current internal state signal Q is "data holding"
And a third gate for outputting the internal state signal q as "data holding" when the transmission request signal indicates a non-active state and the signal R from the next stage indicates "data jam". A data transmission circuit characterized by comprising: