JPS6128426Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a clock supply circuit, and in particular to a mode switching signal such as a preset command signal or an up/down signal.
The present invention relates to a clock supply circuit suitable for use in digital circuits and the like that require a so-called removal time with a predetermined time difference from input of a down command signal to input of a clock signal.

An example of a digital circuit that requires removal time is a presettable counter. A case in which a conventional clock supply circuit is applied to this presettable counter will be described with reference to FIG.

In Figure 1, 1 is an oscillator, 2 is a frequency division counter for dividing the master clock signal from oscillator 1 to generate a clock signal with a lower frequency, and 3 is an inversion of the output of frequency division counter 2. This is an inverter for supplying the clock signal to the clock terminal CK of the D-type flip-flop circuit 4. The input terminal D of the flip-flop circuit 4 is connected to an external input terminal 5 to receive a preset enable signal, and its output terminal Q is connected to a preset terminal PE of a presettable counter 6 to control the output signal of the flip-flop circuit 4 into a mode. The switching signal is output as a preset command signal, for example. Further, the inverting output terminal of the flip-flop circuit 4 is connected to one input terminal of a gate circuit, for example, an AND gate 7. The other input terminal of the AND gate 7 is the frequency dividing counter 2.
is connected to output terminal Q _{2 of} , and also connected to AND gate 7
The output terminal of the AND gate 7 is connected to the clock terminal CK of the presettable counter 6, and the output signal of the AND gate 7 is supplied to the presettable counter 6 as a clock signal having a predetermined time difference from the preset command signal. In this way, the oscillator 1
The reason why the frequency of the master clock signal of the oscillator 1 is divided and supplied to the presettable counter 6 is because the frequency of the master clock signal of the oscillator 1 is too high, and if it is supplied as is, the presettable counter 6 will not operate.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the signal waveforms shown in FIG. 2.

The master clock signal from oscillator 1 is frequency-divided by frequency division counter 2, and its output terminals Q ₀ , Q ₁ and Q ₂ receive clock signals whose frequency has been divided into 1/2, 1/4 and 1/8, respectively. can get. Here, the output terminal
It is assumed that the signal appearing at _Q2 , that is, the clock signal _S1 whose frequency is divided to 1/8 as shown in FIG. 2A, is used. This clock signal _S1 is the AND gate 7
The signal is supplied to the other input terminal of the flip-flop circuit 4, is inverted by the inverter 3, and is supplied to the flip-flop circuit 4.

On the other hand, a preset enable signal _S2 is supplied to the input terminal D of the flip-flop circuit 4.
This signal _S2 is output to the output terminal Q and the inverted output terminal after a predetermined time delay when the clock signal _S1 is input, and is outputted to the output terminal Q and the inverted output terminal as shown in FIG. 2 C and D, respectively. signals S ₃ and S ₄ appear. The signal _S3 appearing at the output terminal Q is supplied as a preset command signal to the preset terminal PE of the presettable counter 6, and the signal _S4 appearing at the inverting output terminal is converted into a signal from the frequency dividing counter 2 by the AND gate 7. The clock terminal CK of the presettable counter 6 is output as a clock signal _S5 which is logically processed with _S1 and has a removal time _t1 as shown in FIG _. 2E for the signal S3.
supplied to This presettable counter 6 takes in the preset input in the preset state when the preset command signal _S3 is at a logical high level.
When the level is low, it enters the counting state.

Normally, the presettable counter 6 will malfunction if there is no removal time between the preset command signal and the clock signal, but as mentioned above, the preset command signal
Since the clock signal S5 is supplied after the removal time _t1 after _S3 is input, the presettable counter 6 starts counting the clock signal _S5 from this point on _, enters the counting state, and resumes normal operation. This means that it can be maintained.

However, in the case of a conventional clock supply circuit, a delay means such as a D-type flip-flop circuit is required to synchronize the preset command signal with the clock signal in order to obtain the removal time, which makes the circuit complicated, and the amount of delay is limited by one stage of flip-flop circuit. However, since the removal time is also limited, there are drawbacks such as the inability to obtain an arbitrary removal time.

In view of these points, the present invention provides a clock supply circuit which has a simple circuit configuration and can obtain any desired removal time as required.

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4.

FIG. 3 shows the configuration of a clock supply circuit according to the present invention. Parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In the present invention, the frequency division counter 2 is reset by the mode switching signal supplied to the presettable counter 6, that is, the preset command signal in this case, and the output terminal Q2 of the frequency division counter 2 is connected to the output terminal _Q2 shown in FIG. The clock terminal CK of the presettable counter 6 is connected to the clock terminal CK of the presettable counter 6 without using any delay means such as the D-type flip-flop circuit used in the above.

Next, the operation of this clock supply circuit will be explained with reference to the signal waveforms shown in FIG. Now, dividing counter 2
Although the master clock signal _S6 shown in FIG. 4A is supplied from the oscillator 1, the mode switching signal, that is, the preset command signal _S7 shown in FIG. 4B from the preset enable terminal 5 is not logical. When it is at one level, eg, high level, it is in a reset state and does not generate an output signal. When the preset command signal _S7 from the preset enable terminal 5 logically reaches the other level, for example, a low level, the frequency dividing counter 2 is released from the reset state and generates a frequency divided clock signal on its output side. do. For example, as shown in Figure 4C, the output terminal Q ₀ receives a clock signal S ₈ whose frequency is divided into 1/2,
Q ₁ has a clock signal S 9 whose frequency is divided by 1/4 as shown in Figure 4D, and output terminal Q ₂ has a clock signal S ₉ as shown in Figure 4E.
A clock signal _S10 whose frequency is divided by 1/8 as shown in FIG.

On the other hand, the preset command signal S7 is supplied from the preset enable terminal 5 to the preset terminal PE of the presettable counter 6, and the preset command signal _S7 of the presettable counter ₆ is logically set to one level, for example, a high level. When , the preset input is taken in advance in the preset state, and when the preset command signal S ₇ logically reaches the other level, for example, the low level, it enters the counting state, and the clock from the frequency dividing counter 2 obtained as described above enters the counting state. Counting starts when signal _S10 is applied. In this embodiment, corresponding to FIG. 1, if the signal appearing at the output terminal Q2 of the frequency dividing counter ₂ is the clock signal supplied to the presettable counter 6, this clock signal _S10 is as shown in FIG. 4E. Thus, the preset command signal _S7 is supplied to the presettable counter ₆ with a delay of the removal time t2.
This removal time _t2 can be arbitrarily varied depending on which signal appearing at each output terminal of the frequency dividing counter 2 is used as a clock signal to be supplied to the resettable counter 6.

As described above, according to the clock supply circuit according to the present invention, the frequency division counter that divides the frequency of a predetermined master clock signal to generate a clock signal with a reduced frequency is reset by the mode switching signal of the digital circuit. Since the mode switching signal supplied to the digital circuit and the clock signal are configured to have a predetermined time difference, that is, a removal time, it is no longer necessary to provide a delay means such as a flip-flop circuit, which was required in the past, in order to obtain such a removal time. Therefore, the configuration is simplified, and the removal time can be freely set within an arbitrary range, providing versatility.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional clock supply circuit, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the present invention. FIG. 4 is a signal waveform diagram for explaining the operation of FIG. 3. 1 is an oscillator, 2 is a frequency division counter, and 6 is a presettable counter.

Claims (1)

[Scope of utility model registration request] A frequency division counter is reset at one logic level of the mode switching signal and divides the clock signal at the other logic level, and a frequency division counter is preset to a predetermined value at one logic level of the mode switching signal and is preset at the other logic level. a presettable counter for counting the frequency-divided clock signal, and the mode switching signal and the frequency-divided clock signal are supplied to the presettable counter with a predetermined time difference. A clock supply circuit characterized by: