JP2775822B2 - Inverter on-delay circuit - Google Patents

Description

The present invention relates to an on-delay circuit of an inverter.

B. Summary of the Invention According to the present invention, first and second latch circuits in which first and second count number data are respectively set and first count number data are input, and the first Counts the clocks so as not to count their fractions.
And the second counter number data, and the second clock having a frequency which is n times higher than the first clock, from the rise of the gate signal to the rise of the first first clock, and the first counter circuit The dead time is obtained with the accuracy of the second clock by using a counter having a small number of bits by a second counter circuit that counts after counting up.

C. Prior Art Conventionally, an on-delay circuit is used to prevent a short circuit between a positive main circuit element and a negative main circuit element of an inverter. FIG. 3 shows an inverter. The on-delay circuit 32 is constructed as shown in FIG. 4, and is turned on by a resistor R and a capacitor C in response to a gate signal from the PWM generation circuit 31, for example, a U gate signal. A delay time, that is, a dead time is taken, and an inverter 34
Is controlled.

D. Problems to be Solved by the Invention However, when changing the delay time, the above-described on-delay circuit needs to change the constant of the resistor R or the capacitor C, and the change takes time and effort. Since the constant and threshold voltage of logic elements such as inverter elements always vary,
As a result, there are disadvantages in that an absolute error and a relative error occur in the delay time.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems of the conventional technology, and an object of the present invention is to provide an inverter on-delay circuit that can set or change a dead time easily and accurately by software. To provide.

E. Means for Solving the Problems In order to achieve the above object, an on-delay circuit of an inverter according to the present invention comprises a first and a second latch circuit in which first and second count data are respectively set. The first count number data is input from the first latch circuit, and the first counter circuit counts the first clock from the rising edge of the gate signal so as not to count a fraction thereof; 2 count number data is input, and after the first counter circuit counts up from the rise of the gate signal to the first rise of the first clock by the second clock having a frequency n times higher than the first clock. And a second counter circuit for counting.

F. Operation Each count number data set in the first and second latch circuits can be set and changed by software.

The first counter circuit starts counting from the first rising clock from the rising edge of the gate signal so as not to count the fraction of the first clock pulse, and counts the set count.

The second counter circuit outputs n from the first clock pulse.
The count number set from the rising edge of the gate signal not counted by the first counter circuit to the first rising edge of the first clock and the count number set after the count-up of the first counter circuit is counted by the second clock having the higher frequency.

Thus, the time during which the first and second counters are counting, that is, the dead time is (first clock cycle × count number + second clock cycle × count number).

Therefore, since the first clock cycle is n times larger than the second clock cycle, a dead time can be obtained with the accuracy of the second clock cycle by using a counter circuit having a small number of bits.

G. Embodiment An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a time chart showing an on-delay circuit, and FIG. 2 is a time chart showing a signal relation of each part of the circuit of FIG.

In Figure 1, the latch circuit 1, a clock CK by a microprocessor (not shown) by the write signal WR ₁
The count number of 1 is set. Similarly count clock CK2 in the latch circuit 4 by the write signal WR ₂ is set. The clock CK1 has a frequency of 1 / n of the clock CK2. The clocks CK1 and CK2 may be either synchronous or asynchronous.

The timing circuit 3 is a circuit to enable or disable the counter circuit 2, outputs an enable signal b ₁ at the rising edge of the earliest clock CK1 after the gate signal a rises. Enable signal
Counter circuit 2 with b ₁ is data that is set in the latch circuit 1 enters the counter circuit 2 is input to the counter circuit 2 is enabled.

When the counter circuit 2 is enabled, the clock CK1
It starts counting by counts up a predetermined number of counts, and outputs a carry signal C _1. The timing circuit 3 is to the counter circuit 2 stops the enable signal b ₁ receives this carry signal C ₁ is disabled.

The timing circuit 6 enables or disables the counter circuit 5, and includes a gate signal a and a clock signal.
And outputs the enable signal b ₂ by CK2. Then, stop the enable signal b ₂ when the enable signal b ₁ enters, and outputs an enable signal b ₂ a carry signal C ₁ is entered. Enable signal b ₂ enters the latch circuit 4 sets data counter circuit 5 to the counter circuit 5
And the counter circuit 5 is enabled. That is, the timing circuit 6 sets the counter circuit 5 to the gate signal a.
Is enabled, and the counter circuit 5 is enabled while the counter circuit 2 is disabled.

When the counter circuit 5 is enabled, the clock CK2
It starts counting by counts up a predetermined number of counts, and outputs a carry signal C _2.

Flip flop 7 is set by the carry signal C _2,
The reset is performed at the falling edge of the gate signal a, and the gate signal after the delay is output.

With the configuration described above, the counter circuit 5
Counts the clock CK2 from the rise of the gate signal a to the rise of the clock CK1. And
When the clock CK1 rises and the counter circuit 2 is enabled, the counter circuit 5 is disabled, and the counting is temporarily stopped while the count data remains unchanged.

Counter circuit 2 starts counting the counter circuit 5 to suspend the counting, become disabled state and outputs a carry signal C ₁ when a predetermined number of counts.

When the carry signal C ₁ is issued, the counter circuit 5, resumes counting, and outputs a carry signal C ₂ when a predetermined number of counts.

Thus, the delay time T _D from the rise of the gate signal a to the output of the carry signal C ₂ is equal to the clock CK.
1 cycle × count of counter circuit 2 + clock CK2 cycle × count of counter circuit 5

For example, when the clock CK1 has a cycle of 8 μsec and the clock CK2 has a cycle of 0.5 μsec, and the delay is performed using the 4-bit counting circuits 2 and 5, respectively, the maximum dead time is 0.5 μsec × 16 + 8 μsec × 16 = 136 μsec.

On the other hand, to obtain a dead time of 136 μsec with the same accuracy using one counter circuit, 0.5 μsec × 272 = 136 μsec, and a 9-bit binary counter is required.

Therefore, according to the present invention, a highly accurate dead time can be obtained by a counter circuit having a small number of bits.

H. Effects of the Invention Since the present invention is configured as described above, the following effects can be obtained.

Since the dead time can be set and changed by software, it can be easily adapted to various main circuit elements (power transistor, IGBT, FET, etc.) of the inverter.

Since the error of dead time is a maximum of one clock,
By using a clock having a short cycle, the variation or error of the dead time can be reduced.

Since it is constituted by a digital circuit, an error does not occur in dead time due to temperature, voltage, aging and the like.

If the data input to the first and second latch circuits is configured by hardware such as a dip switch and a write signal switch, the present invention can be applied to a control device that does not use a microcomputer.

Since the count clock can be arbitrarily selected according to the data of the second latch circuit, the delay time can be set over a wide range even when the count number (number of bits constituting) of the counter circuit is small.

The number of bits of each counter circuit can be reduced,
Since the error can be generated in the cycle of the second clock, an accurate dead time can be obtained by using a counter circuit having a small number of bits.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing a signal relation of each part of the circuit of FIG. 1, FIG.
FIG. 3 is a gate-on-delay circuit diagram for an arm.

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H02M 7/42-7/98 H03K 5/04-5/07 H03K 5/13-5/145

Claims (1)

(57) [Claims] A first latch circuit in which first and second count data are respectively set; a first count data input from the first latch circuit; A first counter circuit that counts the first clock so as not to count a fraction thereof; and a second count number data input from the second latch circuit, and a second counter having a frequency n times higher than the first clock. The second counter circuit counts from the rising edge of the gate signal to the first rising edge of the first clock by the clock and after the first counter circuit counts up. The second counter circuit counts up. An on-delay circuit for an inverter, which raises a gate pulse after the on-delay.