RU1802403C - Digital device for pulse delay - Google Patents

Abstract

Usage: field of automation and computer engineering, namely, devices for delaying rectangular pulses based on digital elements. The proposed device allows you to combine the implementation of the delay, both shorter and longer than the delayed pulses up to large delay values (from units of microseconds to units of seconds or more) with the accuracy determined by the filling frequency and the stability of the reproduction of the duration of the delayed rectangular pulses. The aim of the invention is to increase the accuracy of the reproduction of delayed pulses, in particular when this activity is several orders of magnitude less than the delay time. This goal is achieved in that the trigger that forms the delayed rectangular pulse is launched at the moment of the end of the pulse, the duration of which is equal to the specified delay, and is reset when the reverse counter returns to the O state during the counting of clock pulses recorded by this counter during instantly during the duration of the input (delayed) pulse during its supply. To solve this problem, a digital device for delaying pulses, containing a clock generator, an EXCLUSIVE OR element, a reversing counter, a first trigger, input and output buses, an additional controlled delay adjuster, the first and second AND elements, a second trigger, a short pulse shaper, and item is NOT. The device can be used in automation and computer equipment, requiring a delay of pulses in a wide range - for up to several seconds, with high accuracy of reproducing the duration of delayed rectangular pulses. 4 ill. SO with oo

Description

The invention relates to automation and computer technology and can be used to delay pulses in devices for various purposes, especially in cases where the delay is much longer than the pulse duration.

The aim of the invention is to accurately (within the step of discreteness) reproduction of the duration of the delayed rectangular pulses for any delay values.

Figure 1 shows a functional diagram of the proposed device; figure 2 shows the voltage sequence diagram in this circuit (in addition to the input signal UBX, the signals at the outputs of the elements of figure 1 with numbers 3, 4, 6, 8, 9 are also shown); Fig. 3 shows an exemplary embodiment of the element

2 (delay adjuster); figure 4 is an example implementation of a shaper of short pulses 8,

The digital device contains: a clock generator 1, a controlled delay unit 2, a first element And 3, a second trigger 4, a second element And 5, an element EXCLUSIVE OR 6, a reversible counter 7, a shaper of short pulses 8, the first trigger 9, the inverter 10, input bus 11 and output bus 12. As a controlled pulse generator, the duration of which is equal to the delay (2), one of the single-oscillator or digital shaper circuits can be used, for example, see Fig. 3 (in Fig. 1, the dashed line shows the connection counting input cx we fig.Z the generator 1), where the 13 - and 14 elementary encoder - programmable counter 564 IE15.

According to figure 1, the output of the clock 1 is connected to the first input of the second element And 5, the output of which

connected to the counting input „T of the reverse counter 7. The second input of the second element And 5 is connected to the direct output of the second trigger 4, R - the inputs of the first (9) and second (4) triggers and the reverse counter 7 are connected to the output of the short (fault ) pulses 8, the first input of which is connected to the output of the loan, and the second to the input of the counting direction (± 1) of the reverse counter 7, to the S-input of the second trigger and to the output of the first element And 3, the first input of the first element And 3 is connected to the input the device bus 11, to the control input delay setting 2 and to the second input of the EXCLUSIVE OR 6 element, the first input of which is connected to the output of the controlled delay setting 2. to the input of the element NOT 10 and to the second input of the first element AND 3, the output of the EXCLUSIVE OR element is connected to the enable (V) input of the reverse counter 7, the output of the element is NOT

. connected to the S-input of the first trigger 9, the output of which is connected to the output bus of the device 12.

The device operates as follows. In the initial state (), at both inputs of each of the elements And 3, 5 is logical O, at the outputs of the triggers 4, 9 and counter 7 are O (the initial installation circuit of the elements 4, 7, 9 in O is not shown in Fig. 1; zeroing of the indicated elements may

produced, for example, by a differentiated rising edge of the input signal UBX).

Delayed input pulse UBX (see figure 2) with its leading edge on

0

5

0

5

0

5

0

5

0

5

gives a delay adjuster 2, the output of which is a pulse U2 with a duration equal to the specified delay time Tzed. The supply of pulses UBX and Ua (delay) to the first and second inputs of element And 3 will lead to the appearance of logical 1 at the output of FROM, fed to S-input of the second trigger 4, as a result of which at the direct output of this trigger signal 1 is applied, supplied to the second input of the second element And 5. Thanks to this, the clock pulses from the output of the generator 1, supplied to the first input of the second element And 5, begin to arrive to counting input (T) reverse vnogo counter 7, simultaneously with the output of the first AND gate 3 signal 1 is input to ± 1 count direction down counter 7 (see FIG. 2 of) a job providing its direct mode account. At the same time, signals are supplied to the inputs of the EXCLUSIVE OR 6 element, as a result of which the output of the element 6 will be a logical O, allowing the pulse counting by the input V by the reverse counter 7. Two further cases are possible:

a) Gvh T2 (see Fig. 2a), i.e., the delay pulse And 2 will end earlier than the pulse of the input signal UBX and signals will be sent to the inputs of elements 3 and b. In this case, the signal through the inverter 10 in the form will be fed to the S-input of the first trigger 9, which will be overturned and the signal at its output (and hence, at the output bus 12) will become (see Fig. 2a). Further, although the pulses of the generator 1 will be fed to the input T of the reverse counter 7, and at the input ± 1 of this counter there will be a signal O corresponding to the countdown mode, that is, the operation of the counter 7 for subtraction, but at the input V it will be logical 1, which corresponds to the mode storage of information, i.e., absence of an account. As soon as the pulse of the input signal ends, that is, it becomes (see figa), the output of the EXCLUSIVE OR 6 element becomes, the output of AND 3 remains, that is, the signal at the direct output of the second trigger 4 is equal to logic 1 and the generator pulses go to the input T of the counter 7, but since the inputs are ± 1 and V are logical О, then the reverse counter 7 starts the countdown until it returns to its original state and the pulse arrives at its output, from which driver 8 will form a reset pulse Us; supplied to the R-inputs of the reset triggers 4.9 and counter 7, as a result of which the whole device returns to its original state, that is, the formation of the output

delayed pulse ends

So, the falling edge of the output signal (delayed pulse) appears at the output of the first trigger 9 at the time of the appearance of a short pulse at the output of the driver 8 (see Fig. 2a), and the rise front at the end of the delay pulse Da. As a result, a pulse is generated at the output of the device, the duration of which is equal to the duration of the input pulse, i.e., TVX, but shifted by the time Tzad.

b) GVH tead (see fig.2b). In contrast to case a, counter 7 is filled during the entire duration of the input pulse GVH, after which the counting stops until 1) (all arguments related to case a remain valid in case b except that the signals UBx and 1) 2 (rear) as if swapping).

At the end of signal U2, trigger 9 is triggered, starting to generate an output pulse. In this case, the countdown of counter 7 starts, which continues until the counter 7 returns to its original state at the moment of the appearance of the pulse at the loan output. Thus, in this case, at the output 12, a pulse of the same duration as at the input appears, but shifted with respect to the input pulse by a delay time, the value of which is limited in fact only by the capacity of the reverse counter 7 and the clock frequency, i.e. device dimensions and permissible discrete error.

The device compares favorably with the prototype and (known) analogues in that, with a relatively simple circuit, it can provide high accuracy of the delay and duration of the output pulses at any ratios between them (and not only for comparable values of G8hig3ad).

The frequency of the clock generator is selected taking into account that the maximum error in reproducing the duration of the input (delayed) pulse is equal to the period of the clock frequency (i.e., the step of measuring the pulse duration).

Claims (1)

SUMMARY OF THE INVENTION A digital device for delaying pulses, comprising a clock generator, an EXCLUSIVE OR element, a reverse counter, a first trigger, an input and output bus, characterized in that, in order to expand the scope of application by providing a delay of both shorter and longer duration of delayed pulses up to large values of the delay, a controlled delay adjuster, the first and second element And, the second trigger, the shaper of short pulses and the element NOT are additionally introduced into it, and you One clock pulse generator is connected to the first input of the second element And, the output of which is connected to the counting input of the reversible counter, the second input of the second element And is connected to the direct output of the second trigger, the reset R-input of which is connected to the R-input of the reverse counter, to R- the input of the first trigger and the output of the short pulse generator, the first input of which is connected to the output of the loan of the reverse counter, and the second input to the input of the direction of the count, ± 1 of the reverse counter, to the R-input of the second trigger and to the output of the first e element AND, the first input of which is connected to the input bus of the device, with the input of the control of the controlled delay switch and the second input of the element EXCLUSIVE OR. the first input of which is connected to the output of the controlled delay switch, to the second input of the first AND element and through the NOT element to the S-input of the first trigger, whose direct output is the output of the device, the output of the EXCLUSIVE OR element is connected to the enable V-input of the reverse counter. Fmg. 1 i Yu n