SU1677870A1 - Controlled frequency divider with fractional division coefficient - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computing devices and frequency synthesizers. The purpose of the invention — improving speed while increasing reliability — is introduced by introducing ZK-trigger 4, inverter 9, OR-NE 10 element, D-trigger into the device. 11 and the formation of new functional connections. In addition, the frequency divider contains the counter 1 pulses, the element And 3, accumulating adder 2, bus 7.5,5 and 8 input, the first code, the second code and output, respectively, 2 Il.

Description

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The invention relates to a pulse technique and can be used in computing devices and frequency synthesizers.

The purpose of the invention is to increase speed while improving reliability,

Figure 1 shows an electrical breaker circuit; 2 shows timing diagrams explaining its operation (2a is a timing diagram of the frequency of the input signal arriving at input 7 of the divider; 26 — time diagram at the output of the JK flip-flop 4; 2 at — the same at the C input recording the parallel code of the counter 1; 2g is the same, the direct output of the D-flip-flop 11, 2d is the same at the output of the accumulating adder 2).

A controlled frequency divider with a fractional division factor contains a pulse counter 1, accumulating adder 2, the overflow output of which is connected to the first input of the AND 3 element, JK flip-flop 4, the first and second code buses 5 and 6, the input bus 7, the output bus 8, inverter 9, element OR NOT 10, D-flip-flop 11; the counting input of the pulse counter 1 is connected to the input bus 7 and the input of the inverter 9, the output of which is connected to the C input of the D-flip-flop 11, the information inputs of the pulse counter 1 are connected to the first code bus 5, the write enable input to the output of the element OR NOT 10 the first input of which is connected to the direct output J of the K-flip-flop 4 and the D-input of the D-flip-flop 11, the inverse output of which is connected by the cj-in and the R-input of the JK-flip-flop 4, the C-input of which is connected to the output of the counter transfer 1 pulses, the direct output of the D-flip-flop 11 is connected to the second input element I 3, K-input m JK-flip-flop 4, the output bus 8 and the clock input accumulating adder 2, the information inputs of which are connected to the second code bus 6; the output element And 3 is connected to the second input of the element OR NOT 10.

The divider works as follows.

Under the action of pulses (Fig. 2a), which are fed through the input bus 7 to the counting input CT of the counter 1, they are usually recalculated in the addition mode. After recalculating the N pulses, the counter 1 is set to one, and at time ti, at its transfer output CR, a zero level appears that affects the synchronization C input of the JK flip-flop 4, setting its output to one (Fig. 2b). This signal is sent to the element OR-NOT 10, from the output of which acts as a zero level (Fig 2c) on

C-G5OUT recording parallel counter code 1. A parallel code equal to the recalculation coefficient K, enters the HaD-inputs of counter 1 via the code bus 5. The binary code of the recalculation coefficient K, corresponding to the established division factor of the integer part No, is defined by the following expression;

K 2m - No,

0 where m is the number of counter bits.

Figure 2 shows the time diagrams of frequency division with No 5.

After the end of the next impulse of the input signal at the time moment g, the direct output of D-flip-flop 11 is set to 1 in 1 (Fig. 2d), and the inverse is set to O. J-input JK-trigger 4, its output

0 is set to O. At the same time, the recording of the parallel code into counter 1 is stopped, and from this point on again the recalculation of the input pulses arriving at the counter input of the CT counter 1 is performed.

5The unit level of the direct output of the Dtrigger 11 from time t2 is fed to the output bus 8 and the clock input of accumulating adder 2 having capacity M. The content of accumulating totalizer 2 increases with each clock step by the amount a of the fractional ratio received on code bus 6 of the fractional part.

After the end of the next pulse

5, the input signal at time t3 turns off the D-flip-flop 11 (FIG. 2d), i.e. a zero level appears at its direct output, and a unit level appears at the inverse. Simultaneously with the shutdown of the D-flip-flop 11, the formation of a pulse of the output signal is stopped. By recalculating the pulses in the interval te-ts), the input part is divided by the integer part of the division factor equal to the value of the diode No code received on the code bus 5 to the D inputs of counter 1. The interval duration (t2, ts) is NoT, where T - the period of the input frequency.

If the next value 0, recorded in accumulator adder 2, equals or exceeds the capacity M of the adder, it overflows the division factor of the device becomes equal to Na + 1 by the time of one division cycle.

5 So, for example, after recalculation, JK-flip-flop 4 is sequentially coaxed at time TA and then D-flip-flop 11 at time ts, the unit level of which, affecting the clock input of accumulating adder 2, causes it to overflow and a single level appears its output (Fig.2d). At the same time, as a result of the coincidence of unit levels from the direct output of D-flip-flop 11 and from the output of accumulating adder 2 at the interval (t5, te), the duration of the negative pulse at the C input of the parallel counter code recording is increased (FIG. 2b) equal to the period of the input frequency. The division factor on the interval (ts, te) becomes Mo + 1. The interval duration (ts.te) is equal to (No + 1J x T. After recalculating No + 1 pulses, the consecutive erection is again performed at time tvJK-flip-flop 4, and at time t-D-flip-flop 11, the unit level of which affecting the clock input of accumulating adder 2 causes the accumulation of accumulator sum 2 to be qi + a M. In this case, the number f recorded in accumulative adder 2 does not cause it to overflow and at its output sets zero. 2e). With the arrival of the next impulse of the input signal in the moment The time interval tg turns off the D-flip-flop 11 (FIG. 2d), i.e., zero appears at its direct output and a unit level at the inverse.

At the moment t, 5 of the overflow of the accumulating adder 2 (figd), the actual number qi $ -M written in it, i.e. it is less than the previous value, equal to $ - a, by the value of M-a. Further change of the code in accumulative adder 2 begins with the value of qi.

Since, from M division cycles, the coefficient No + 1 and (M-a) are set once - the coefficient No, the average division factor is (M0 + 1) -a + M0 (M-a) m.

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N

M

M

If M 2. where n is an integer equal to

the number of bits accumulating sum 2, then N is a binary fraction.

The proposed divider with increased speed and stability of work can be built on

5 10 15 20 25 30

35

40

45 50

low-frequency elements, since the delay time gz of the transfer pulse at the output CR of counter 1, and consequently, the response of the JK flip-flop 11, can reach more than half the period of the input frequency (Fig. 26) without disturbing the work of the divider.

The fractionality in the proposed divider is achieved by correcting the output frequency using the additional effect of the D-flip-flop 11 and accumulating adder 2 through the AND 3 and OR-NOT 10 elements on the C-in of the parallel counter code 1 recording. These features of the proposed divider provide a significant increase in speed and stability of his work.

Claims (1)

Claims of the invention A controlled frequency divider with a fractional division factor, containing a pulse counter, accumulating adder, the overflow output of which is connected to the first input of the And element, the first trigger, the first and second running tires, and the input and output buses, differing in that increase the speed while improving the reliability of operation, the JK-trigger is used as the first trigger and the inverter, the element OR-NOT, the second trigger, which is used as the D-trigger, and the counting input The pulse counter is connected to the input bus and the inverter input, the output of which is connected to the C input of the second trigger, the information inputs of the pulse counter are connected to the first code bus, the write enable input to the output of the OR-NOT element, the first input of which is connected to the forward output the first trigger and the D input of the second trigger, the inverse output of which is connected to the J-BXO house and the R input of the first trigger, whose C input is connected to the transfer output of the pulse counter, the second output of the second trigger, To the input of the first trigger, the output bus and the clock input of the accumulating adder, the information inputs of which are connected to the second code bus, and the output of the AND element is connected to the second input of the OR-NOT element. Fig 2