SU1660136A2 - Pulse signal delay device - Google Patents

Description

The invention relates to discrete delay lines. The purpose of the invention is to expand the functionality by forming a square-varying delay of the signal reference pulse — achieved by introducing into the device a second buffer register 10, a binary adder 11, a second delay circuit 12, a third And element, and a second Control input Upr.2. In addition, the device includes the first buffer register 1, accumulating adder 2, binary counter 3, element OR 4, trigger 5. first and second elements AND 8 and 6, first delay circuit 7, oscillator 9, first control input "Upr. The introduced elements provide the possibility of changing from the tact to the tact of following the delay of the reference signal in quadratic dependence with the possibility of programmatically changing the rate of rise. 1 Il.

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1660136

The invention relates to discrete delay lines, is intended to create a quadratically varying delay of the reference pulse signal and is an improvement of the device according to the author. St. No. 1224988.

The aim of the invention is to expand the scope by forming a quadratically varying delay of the reference pulse signal.

The drawing shows the functional diagram of the device

The device contains a buffer register 1, accumulating adder 2, counter 3, element OR 4, trigger 5, second element AND 6, delay circuit 7, first element AND 8, clock generator 9, second buffer register 10, binary adder 11, second circuit 12 delays and the third element AND 13. Buffer register 1, accumulating adder 2 and pulse counter 3, are connected in series, the overflow output of which is connected to the output bus of the device and through the OR 4 element is connected to the zero input of the trigger 5, the And 6 element, the delay element 7, element And 8, generat p 9 clock pulses, the input bus device connected to the input of the delay element 7 and the first input element And 6, the second input of which is connected to the control bus, and the output of the element And 6 connected to the clock input accumulating adder 2, the installation input of which is connected to the installation bus the initial state, the second input element OR 4 and the installation input of the counter 3, the synchronization input of which is connected to the output element, 7 delay and a single input trigger 5, the output of which is connected to the first input element And 8, the second input of which is connected to the output of the generator 9 clock pulses, and the output of the element And 8 is connected to the counting (subtractive) input of the counter 3, the second buffer register 10 and the binary accumulator 11, the output of which is connected to the first buffer register, are connected in series, the output of which is connected to the second input of the binary adder 11, the installation bus of the initial state is connected to the installation inputs of the first buffer register 1 and the binary adder 11, the third element And 13, the output of which is connected to the clock input of the first buffer register 1, the first input of the third AND gate 13 is the second control input and its second input is connected to the input device, which is also connected to a second input of delay circuit 12, the output

which is connected to the input of the first circuit 7

delay and the second input of the first element And 6.

The delay device of the pulse signals works as follows.

To set the initial state, an impulse is fed to the input of the device "Device.", Which sets to zero the binary adder 11, the first buffer register 1, the accumulating adder 2, the counter 3 and the trigger 5. Since the trigger 5 is set to zero (low level), the clock pulses from the generator 9 do not pass through the element And 8 to the subtracting input of the counter 3 and the device is in the initial state. Upon the arrival of the first input pulse (high level at the second control input) in the first buffer register 1 the delay code stored in the second buffer register 10 will be remembered and will appear at the output of register 1 after a certain delay time. Then the synchronization pulse delayed by time τ in the second delay circuit 12 is longer than the delay time in buffer 1 and adder 11, this code is summarized in accumulating adder 2. This information will appear on its output after a delay time of accumulating adder 2 and access preset inputs counter 3. Then the synchronization pulse delayed in the first delay circuit 7 for a time g longer than the accumulator adder 2 delay time, this code will be overwritten into counter 3, at the same time the same delayed pulse will set to "1" (high level) trigger 5, which will allow the pulses from generator 9 through element AND 8 to pass to the subtractive input of counter 3, the counting time of counters 3 is determined by the code recorded from the pre-installation inputs of counter 3, and the period of clock pulses from generator 9. at the end of the counting from the overflow output of the counter 3, a pulse will appear that is delayed relative to the synchronization pulse for a time of 1h = nT, where η is the code recorded in the counter 3; T - period of clock pulses. This pulse is the output pulse of the device. At the same time, this pulse through the element OR 4 sets the trigger 5 to "O", which prohibits the further passage of the clock pulses from the generator 9 through the element 8 to the subtracting input of the counter 3. The device is in the waiting state. The second input pulse, passing through the element And 13, will change the state of the first buffer register 1 to the value Δ stored in the second buffer register 10, since the register 1 and binary 1660136

The new adder 11 is formed by an accumulating adder, the sum code stored in register 10 over the synchronization pulse.

This information after a time less than m will appear at the input of the accumulating sum of 5 torus 2, and the synchronization pulse delayed by r will change the state of the accumulating adder by the value of A and its state will be equal to the previous one, plus the code from the register 1 output. This information again in time τ will be recorded as a synchronization pulse in counter 3, which will set trigger 5 in "G". The clock pulses through element 8 will go to the subtracting input of counter 3, which will 15 already count the time Δ ΐ = Δ · T, where Δ is a jump . T - period of clock pulses. The third input pulse will change the state of register 1 again to the value of Δπ its state will be 2 Δ, and the previous state of the adder 2 Δ will be added to the register code 1 and the state of the adder 2 will be equal to Δ + 2-Α. Again, after this time, this information is recorded by the synchronization pulse in counter 3, which will count the time Δΐ = 3Δ ·. The next input pulse will write to the counter 3 code Δΐ = 6Δ T, then Δΐ = 10Δ ·. Then Δΐ = 15 Δ · T. It can be seen that the delay code increases with the quadratic dependence of the delay on the number of the input pulse.

This is repeated until adder 2 overflows, and if an integer increment is placed in the capacity of adder 2, overflow of adder 2 is equivalent to setting the initial state, if not, it will return not to the zero state, but to the state equal to the remainder, and the operation of the device will continue. If this situation is undesirable, then it is necessary to provide for the installation of adder 2 in the "0" for its overflow.

The bit width of the register 1, the binary adder 11 and the register 10 must be less than the capacity of the adder 2 and it is necessary not to overflow the register 1.

The device has a “Stop” mode when a low level “0” is applied to the first control bus, which prevents the input pulse from passing through the AND 6 element to the synchronization input of the adder 2. In this mode, the state of the adder 2 remains unchanged, which is equivalent to a fixed delay TsadO = kT, where K is the state of accumulating adder 2, It is also possible to switch from a quadratically varying delay to a linear delay, when a low level is applied to the second control bus of the device, which prohibits changing the code at the output of the re istra 1, and there is a linear variation of the delay with a speed stored in the volatile registers 1.

Claims (1)

Claim Delay device pulse signals auth. St. No. 1224988, characterized in that, in order to expand the scope by providing the possibility of forming a quadratically varying delay of the reference pulse signal, a second buffer register connected in series and a binary adder, whose output is connected to the first buffer register, are entered into it binary adder, the third element And, the output of which is connected to the clock input of the first buffer register, the first input is the second control input, and its second input d connected to an input device, which second delay circuit is connected to the input of the first delay circuit and a second input of the first AND gate, the tire setting an initial state is connected to the inputs of the first mounting buffer register and a binary adder.