JP2690113B2 - Frequency multiplier circuit - Google Patents

Description

The present invention relates to a frequency multiplier circuit using a delay circuit composed of a resistor and a capacitor.

[Conventional technology]

Conventionally, when a delay circuit composed of an inverter, a resistor, and a capacitor as shown in FIG. 4 and an output of the delay circuit and an input signal are subjected to waveform synthesis by exclusive OR, it is doubled with respect to the input signal. It is possible to obtain the output of the frequency of.

[Problems to be solved by the invention]

In the case of the conventional frequency multiplying circuit described above, the pulse width of the output waveform of the multiplying circuit is not constant due to variations in the resistance value used and the capacitance value of the capacitor.

Especially when it is attempted to realize it on an integrated circuit, individual parts cannot be selected, and the output pulse width of the frequency multiplication circuit may vary, resulting in malfunction.

[Means for solving the problem]

In the present invention, in order to solve such a problem, by detecting the operation stop state of the circuit operating with the multiplied output signal and controlling the delay amount of the delay circuit that determines the output pulse width of the frequency multiplying circuit, It is to provide a frequency multiplier circuit that compensates the output pulse width of the multiplier circuit and compensates the operation of the entire circuit. That is, the frequency multiplier circuit according to the present invention includes an input terminal for receiving an input signal, a first and a second terminal.
A first exclusive OR circuit having an input terminal and an output terminal, first connecting means for connecting the input terminal and the first input terminal, and connecting the input terminal and the second input terminal Second connecting means, a plurality of capacitive elements each having one end connected to a power supply terminal, and a plurality of transfer gates respectively connected between the other end of the corresponding capacitive element and the second connecting means. And an operation stop detection circuit that receives signals from the first input terminal and the output terminal and controls the conduction state of each of the transfer gates based on the signals, and detects the operation stop. A circuit includes a binary flip-flop that receives a signal from the output terminal, a second exclusive OR circuit that receives an output signal of the binary flip-flop and its delayed signal,
When the output of the second exclusive OR circuit is at the first logic level, the detection end is filled, and when the output is at the second logic level different from the first logic level, the detection end is discharged. The potential of the charging / discharging means and the detection end is detected, and when the potential reaches a predetermined potential, a counting operation is performed in response to a signal from the first input end, and the potential becomes a predetermined potential. A control means for stopping the counting operation regardless of the signal from the first input terminal when it has not reached, and a control means for controlling the number of the transfer gates to be conducted based on the count value by the counting operation. It is characterized by including.

〔Example〕

 Hereinafter, the present invention will be described in more detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The pulse width of the output of the frequency multiplier circuit is determined by the time constant of the delay circuit composed of the resistor and the capacitor in the frequency multiplier circuit.

The frequency multiplication circuit of the present invention is provided with a plurality of capacitors (C _{1 to} C _n ) for determining the time constant, and transfer gates TG _{1 to} TG _n composed of N-channel insulated gate FETs are provided at one end of each capacitor. By connecting the transfer gate to make the transfer gate conductive, and selecting a capacitor connected to the transfer gate, the time constant can be changed and the pulse width of the output of the frequency multiplication circuit can be changed. The control signal of the transfer gate connects the output signals A _{1 to} A _n of the operation stop detection circuit.

Next, an embodiment of the operation stop detection circuit is shown in FIG. The EX1 output of the exclusive OR gate (hereinafter referred to as EXOR) of the frequency multiplier circuit is connected to the clock input of the binary flip-flop BF1, and the Q output of BF1 is a delay composed of an inverter, a resistor and a capacitor. It is connected to the circuit and the input of EXOR (EX2), and the output of EXOR (EX2) is connected to the gate of N channel insulated gate type FET T3. The source and substrate of the N-channel insulated gate FET T3 are connected to GND, and the drain is connected to one end of the resistor R12 and capacitor 12 and the input of the AND gate (ND1).

The other end of the resistor R12 and the capacitor C12 is connected to the V + power supply. The input signal IN2 is connected to the input of the AND gate (ND1), and the output of the AND gate (ND1) is connected to the clock inputs of the data flip-flops DF1, DF2, ... DFn. The data input of DF1 is connected to the V + power supply, and the Q output of DF1 is DF2.
Data, and the Q output is sequentially connected to the data input of the next data flip-flop. Q output of DF1 is A
The outputs of A2 and DFn to the Q output of 1 and DF2 are An and become the operation stop detection circuit output signal.

In the above circuit configuration, if BF1 does not operate due to variations in the pulse width of the output signal of the frequency multiplier circuit, EXOR
The output of (EX2) becomes GND level, the N-channel insulated gate FET is cut off, and the potential at point A becomes V + power supply level. The input signal IN2 is input to the clocks of the data flip-flops DF1, DF2, ... Change and change the pulse width of the output. When the pulse width of the frequency multiplier circuit output changes and BF1 operates, a pulse signal is output from EXOR (EX2) by the same operation as in FIG. EXOR (EX
When the output signal of 2) is V + power supply level, the N-channel insulated gate FET T3 becomes conductive and the potential at point A becomes GND level. Next, when the output signal of EXOR (EX2) becomes GND level, N-channel insulated gate type FET T3 is cut off and the potential at point A changes depending on the time constant of C12 and R12. The threshold voltage is never exceeded, the input signal IN2 is not output from the AND gate (ND1), and the outputs of DF1, DF2 ... DFn (A _{1 to} A _n ) are the pulses with the optimum frequency multiplication circuit output. Fixed with width compensation.

[Effect of the Invention] According to the present invention, by detecting the operation stop state of the circuit operating with the output signal of the frequency multiplication circuit and changing the output pulse width of the frequency multiplication circuit, the pulse width is compensated and the entire circuit There is an effect of preventing the malfunction of.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a detailed view of the transfer gate. FIG. 3 is a detailed diagram of the operation stop detection circuit. FIG. 4 is a diagram for explaining the operation of the frequency multiplier circuit. C _{1 to} C _n , C ₁₁ , C ₁₂ ...... Capacitor, I ₁ , I ₂ , I ₃ , I ₄ , I ₂₁ ......
Inverter, R ₁ , R ₁₁ ...... Resistance, TG _{1 to} TG _n ...... Transfer gate, EX1, EX2 ...... Exclusive OR circuit, T ₁ ...... P
Channel insulated gate FET, T ₂ , T ₃ …… N channel insulated gate FET, BF 1 …… Binary flip-flop,
DF1 to DFn …… Data flip-flop, ND1 …… AND gate, A1 to An …… DF11 to DF1N Q outputs, 1 …… Input signal terminal, 2 …… Frequency multiplication circuit output terminal, 3 …… Operation Stop detection circuit.

Claims (1)

(57) [Claims] 1. An input terminal for receiving an input signal, and first and second input terminals.
A first exclusive OR circuit having an input terminal and an output terminal, first connecting means for connecting the input terminal and the first input terminal, and connecting the input terminal and the second input terminal Second connecting means, a plurality of capacitive elements each having one end connected to a power supply terminal, and a plurality of transfer gates respectively connected between the other end of the corresponding capacitive element and the second connecting means. And an operation stop detection circuit that receives signals from the first input terminal and the output terminal and controls the conduction state of each of the transfer gates based on the signals, and detects the operation stop. A circuit includes a binary flip-flop that receives a signal from the output terminal, a second exclusive OR circuit that receives an output signal of the binary flip-flop and its delayed signal,
When the output of the second exclusive OR circuit is at the first logic level, the detection end is filled, and when the output is at the second logic level different from the first logic level, the detection end is discharged. The potential of the charging / discharging means and the detection end is detected, and when the potential reaches a predetermined potential, a counting operation is performed in response to a signal from the first input end, and the potential becomes a predetermined potential. A control means for stopping the counting operation regardless of the signal from the first input terminal when it has not reached, and a control means for controlling the number of the transfer gates to be conducted based on the count value by the counting operation. Frequency multiplication circuit characterized by including.