JP2690516B2 - Ring counter - Google Patents

Description

The present invention relates to a ring counter used in a semiconductor memory having a serial access function.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional example of this kind of N-stage ring counter, FIG. 5 is a circuit diagram showing the conventional example of FIG. 4 in more detail, and FIG. 6 is an operation of the conventional example of FIG. It is a time chart shown.

The N-stage ring counter is controlled by four-phase clocks CLK1, CLK2, CLK3, and CLK4, which are control signals, and serially arranges N-stage pulse outputs φ ₁ , φ ₂ , ..., φ _N in time series at regular intervals. Output to. The buffer 40 receives the output φ _N of the final stage of the shift register. The OR circuit 20 takes the OR of the set signal SET and the output of the buffer 40 and outputs it to the shift register 10.

The shift register 10 includes SR flip-flops 11 ₁ , 11 ₂ , ...
11 _N and AND circuits 12 ₁ , 12 ₂ , ..., 12 _N. SR flip-flop 11 ₁ is reset by the clock CLK3, is set by the output of the OR circuit 20. The AND circuit 12 ₁ ANDs the clock CLK1 and the output of the SR flip-flop 11 ₁ and outputs the result as the output signal φ ₁ . The SR flip-flop 11 ₂ and the AND circuit 12 ₂ take in the output signal φ ₁ and output it as the output signal φ ₂ in synchronization with CLK2. Similarly, in the subsequent stages, the output of the previous stage is taken in and the output signal is output in synchronization with the input clock signal. The output φ _{N of the} final stage is fed back to the SR flip-flop 11 ₁ of the first stage via the buffer 40, the connection line 60, and the OR circuit 20.

Next, the operation of the conventional example shown in FIGS. 4 and 5 will be described with reference to FIG.

Since the clocks CLK3 and CLK4 become logic level high (hereinafter referred to as “H”) between the times t ₀ and t ₁ , the RS flip-flop 11 ₁ ,
11 ₂ is reset. Since the set signal SET becomes “H” between the times t ₁ and t ₃ and the clock CLK1 becomes “H” between the times t ₂ and t ₃ , the two inputs of the AND circuit 12 ₁ are connected to the times t ₂ and t. “H” between ₃
Then, the output signal φ _{1 of the} first stage becomes “H” between times t ₂ and t ₃ . "H" of this output signal φ ₁ is RS flip-flop 11 ₂
Is taken up by. Set signal SET and the clock CLK1 at time t ₃ becomes a logic Reberurou (hereinafter "L" and referred to) in since the output signal φ ₁ is also "L". Clock K3 between times t ₃ and t ₄
Goes high, the RS flip-flop 11 ₁ is reset. When the clock CLK2 becomes “H” between times t ₄ and t ₅ , RS
Since the flip-flop 11 ₂ outputs "H", the AND circuit 12 ₂ sets the output signal φ ₂ to "H". In this way, the output signals φ ₁ , φ ₂ , ... φ _N are output with a pulse width T and a period 2T. The final stage output signal φ _N is fed back to the RS flip-flop 11 ₁ via the buffer 40, the connection line 60, and the OR circuit 20, and is output again in the order of output signals φ ₁ , φ ₂ , ..., φ _N. .

[Problems to be solved by the invention]

In the above-mentioned conventional ring counter, the output signal φ _{N at} the final stage is fed back via the connection line 60. Since the connection line 60 is as long as the chip total length and has a large load capacity, the feedback is performed. Therefore, a buffer 40 having a large current capacity must be provided, and this buffer 40 has a drawback that an operation delay occurs and a high-speed cycle operation cannot be performed.

[Means for solving the problem]

The ring counter of the present invention comprises N (N is an integer of 2 or more) SR flip-flops,
The output of each SR flip-flop is ANDed with the control signal, and the N-stage shift register consisting of N AND circuits that serially outputs the result to the output line and the N-stage shift register that outputs the control signal After the output signal is sequentially output to each stage of the shift register and the (N-1) th output signal is output, the RS flip-flop of the first stage is operated from the time when the output signal is stopped until the Nth output signal is stopped. Control means for sending a set signal to the group.

[Action]

By the control means, (N-
1) Since the feedback set signal is given to the first stage of the N-stage shift register from the fall of the output signal of the stage to the fall of the output signal of the N-stage, the output signal of the (N-1) -th stage The time from the fall to the rise of the output signal of the Nth stage can be used to cover the operation delay, and high speed operation is possible even if there is a circuit delay such as a buffer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the ring counter of the present invention, FIG. 2 is a circuit diagram showing the embodiment of FIG. 1 in more detail, and FIG. 3 is an embodiment shown in FIGS. It is a time chart which shows operation of an example.

This embodiment is different from the conventional example shown in FIG.
And a NOR circuit 50 are added.

The input terminal D of the D flip-flop 30 is a shift register
The output terminal Q is connected to the output terminal of the AND gate 12 _N-1 of 10 and the input terminal of the buffer 40, respectively. The NOR circuit 50 takes the NOR of the clocks CLK1 and CLK2 and applies the output to the clock terminal C of the D flip-flop 30.

Next, the operation of this embodiment will be described with reference to FIG.

Except for the feedback set signal φ _FB , the description is omitted because it is similar to the conventional example of FIG.

Between times t ₁₁ and t ₁₂ , clock CLK1 is “H”, clock CL
K2 is at "L", the clock CLK or between the time _{t 12, t 13 "L"} , the clock CLK2 is "L". Therefore, time t
_{At 12} , the output of NOR circuit 50 rises. The D flip-flop 30 outputs the output signal φ at the rising edge of the output of the NOR circuit 50.
Latch “H” of _N-1 . Similarly, at time t ₁₄ , the output signal φ
Latch “L” of _N-1 .

Therefore, the feedback set signal φ _FB which is the output of the D flip-flop 30 can be raised earlier than the conventional time by the time T, so that even if it is output via the buffer 40, the operation delay does not occur in correspondence with the output φ ₁ of the first stage.

〔The invention's effect〕

As described above, according to the present invention, the control means controls the N
By giving the feedback set signal to the first stage of the N-stage shift register from the fall of the (N-1) -th stage output signal of the stage shift register to the fall of the N-th stage output signal,
-1) There is an effect that the operation delay can be covered and the high-speed cycle operation can be performed in the time from the falling edge of the output signal of the first stage to the rising edge of the output signal of the Nth stage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the ring counter of the present invention, FIG. 2 is a circuit diagram showing the embodiment of FIG. 1 in more detail, and FIG. 3 is an embodiment shown in FIGS. A time chart showing the operation of the example, FIG. 4 is a block diagram showing a conventional example of this type of N-stage ring counter, FIG. 5 is a circuit diagram showing the conventional example of FIG. 4 in more detail, and FIG. 4 is a time chart showing the operation of the conventional example of FIG. 10 ... Shift register, 11 ₁ , 11 ₂ , ~, 11 _N ...... RS flip-flop, 12 ₁ , 12 ₂ , ~, 12 _N ...... AND circuit, 20 ...... OR circuit, 30 ...... D flip-flop, 40 …… buffer, 50 …… Noah circuit, 60 …… connection line.

Claims (1)

(57) [Claims] 1. N (N is an integer of 2 or more) number of SR flip-flops, and an AND of the output of each SR flip-flop and a control signal is taken, and the result is serially output to an output line. After the N-stage shift register including an AND circuit and the control signal are output to sequentially output the output signals to the respective stages of the N-stage shift register, the (N-1) th stage output signal is output. A ring counter having a control means for sending a feedback set signal to the RS flip-flop at the first stage from the time it is stopped until the output signal at the Nth stage is stopped.