JPH03244217A - Parallel/serial conversion circuit for data - Google Patents

Abstract

PURPOSE:To simplify circuit configuration and to reduce energy consumption by always supplying a logic level 1 to the second data input terminal of a D-flip-flop(DFF) in the first step and supplying the output of the DFF in the final step to a serial data output terminal. CONSTITUTION:A load signal LDP is normally supplied at '1' and once inverted to '0' concerning four clocks. On the other hand, since the logic level of a second data input terminal D in a first DFF 1 is '0' at all times, the Q outputs of DFF 1-DFF 3 are turned to '0' after the passage of three clocks. Next, when a clock signal CLK is ended while setting the signal LDP to '1', the data applied to inverse phase parallel data input terminals, (-PD1)-(-PD4) are respectively latched to the DFF 1-DFF 4 and successively serially outputted from an output terminal SD. In such a case, since a gate is not provided on a critical path between the respective DFF,, the number of elements can be decreased and the energy consumption can be reduced.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a data parallel/serial conversion circuit, and in particular reads n-bit parallel data in synchronization with a clock signal and multiplexes it in a time division manner. This is suitable for use in semiconductor circuits that output serially.

<Prior Art> A semiconductor circuit is known that converts n-bit data provided in parallel into serial data and outputs the serial data. FIG. 3 is a circuit diagram showing a conventional example of a circuit for converting 4-bit parallel data into serial data. In the circuit shown in FIG. 3, one D-flip-flop DFE and one selector SL are provided for each bit, and there are four in total. The output terminals of the selectors SLI to SL4 are connected to the data input terminals of the D-flip-flops DFI to DF4, respectively. Further, the output terminal of the D-flip-flop in each stage is connected to the second input terminal of the selector in the next stage, and the output terminal of the D-flip-flop DF4 in the final stage is connected to the serial data output terminal SD.

This parallel/serial conversion circuit has four parallel signal input terminals PDI to PD4. A load signal input terminal LD and a clock signal input terminal CL are provided, and each parallel signal input terminal PDI to PD4 is provided.

It is connected to the first data input terminals of the first to fourth selectors SLI to SL4. Also, load signal input terminal L
D is connected to the control signal input terminal of each of the selectors SLI to SL4, and the clock signal input terminal CL is connected to the clock signal input terminal of the first to fourth D-flip-flops DFI to DF4. Here, the first to fourth D-flip-flops DFI to DF4 output the logic level of the applied data signal when the clock signal CLK falls, and the first to fourth selectors SLI to SL4 outputs the logic level of the data signal applied to the first data signal input terminal when the logic level of the control signal is "1", and when the logic level of the control signal is "O", It is assumed that the logic level of the data signal applied to the second data signal input terminal is output.

Next, the operation of the parallel/serial conversion circuit shown in FIG. 3 will be explained according to the operating waveform diagram shown in FIG. 4. In addition, in the operation waveform diagram of FIG. 4, the horizontal axis is the time axis, and each time point to-1. The logic level of each part corresponding to is shown.

In FIG. 4, time t. When the logic level of the load signal input terminal LD becomes "1" during ~t1, the logic level of each output terminal 11 to 41 of the first to fourth selectors SLI to SL4 becomes equal to that of each parallel signal input terminal PDI to PD4. They become the same as the logic levels, and become L1 to L4, respectively.

Next, when the clock signal CLK becomes "0" at time t1, the logic levels of the output terminals of the first to fourth D-flip-flops DFl to DF4 change to the respective output terminals 11 to 11 of the first to fourth selectors. The logic levels are the same as those of 41, and are respectively L1 to L4. Therefore, in this case, the logic level of the serial data output terminal SD becomes L4. Furthermore, the fourth
Since the logic level of the output terminal of the D-flip-flop DF4 is the same as that of the serial data output terminal SD, it is omitted in FIG.

When the logic level of the load signal input terminal LD becomes "0" between time points t□ and t2, the logic levels of the output terminals 21 to 41 of the second to fourth selectors become the logic levels L1 to L1, respectively.
It becomes equal to L3. Therefore, at time t2, the second
and the output terminal 22.3 of the third D-flip-flop.
The logic level of the serial data output terminal SD is equal to the logic level L1 and L2, respectively, and the logic level of the serial data output terminal SD is equal to the logic level L3.

At time t3, the logic level at the output terminal 32 of the third D-flip-flop becomes equal to the logic level Ll, and the logic level at the serial data output terminal SD becomes equal to the logic level L2. Further, at this time, the output terminal 41 of the fourth selector becomes at a logic level equal to the logic level L1. Then, at time t4, the serial data output terminal SD reaches a logic level equal to the logic level Ll.

Next, between time points t4 and t8, the load signal input terminal LD
Since the logic level of becomes “L”, the state of each part changes to the time t.
. The state returns to the same state as in the period from t1 to t1, and the above-described operations are repeated thereafter.

In this way, when the logic level of the load signal input terminal LD is "L", the data parallel/serial conversion circuit shown in FIG.
The data applied to the first to fourth parallel data input terminals PDI to PD4 are read, sequentially transferred in synchronization with the clock signal CLK, and output in serial from the serial data output terminal SD.

<Problems to be Solved by the Invention> In the circuit shown in FIG. 3, one selector SL and one D-flip-flop DF are provided for one parallel data input terminal, so that the number of parallel data to be multiplexed is reduced. The same number of these selectors SL and D-flip-flops were needed. By the way, if the selector SL is composed of only Nant gates, it usually requires four gates, so the conventional parallel/serial conversion circuit shown in FIG. 3 requires a large number of elements. Therefore, there is a problem in that the power consumption increases and the circuit configuration becomes larger. Furthermore, in this case, the number of gate stages on the critical path between flip-flops is two, which has been a bottleneck in improving the operating speed.

In view of the above-mentioned problems, it is an object of the present invention to provide a circuit that has low power consumption and is suitable for high-speed operation.

<Means for Solving the Problems> The data parallel/serial conversion circuit of the present invention has n external data inputs provided for inputting n-bit anti-phase parallel data to be parallel/serial converted. A terminal, a clock signal input terminal for inputting a clock signal that is a reference for the operation of parallel/serial conversion of the above-mentioned anti-phase parallel data, and a logic level of 0'' every n clocks of the above-mentioned clock signal. n load signal input terminals for inputting an inverted load signal, serial data output terminals for outputting serially converted data, and n pieces corresponding to each of the n data input terminals, The reverse phase parallel data input to each data input terminal above is the first
n NOR circuits are provided corresponding to each of the NOR circuits, and the load signal is provided to the second input terminal of the NOR circuit, and the data signals output from the NOR circuits are respectively provided. D has a first input terminal that is input to the input terminal and a second input terminal that is supplied with a data signal derived from the output terminal of a flip-flop provided in the preceding stage, and outputs the logical sum of the signals supplied to these terminals. - a flip-flop, and always supplies logic level "0" to the second data input terminal of the D-flip-flop provided in the first stage, and also supplies logic level "0" to the second data input terminal of the D-flip-flop provided in the final stage. The output is supplied to the serial data output terminal.

Another feature of the present invention is that n external data input terminals are provided for inputting n-bit anti-phase parallel data to be converted into parallel/serial data, and A clock signal input terminal for inputting a clock signal that serves as a reference for serial conversion operation, and a load for inputting a load signal that is inverted to logic level or "L" every n clocks of the above clock signal. A signal input terminal, a serial data output terminal for outputting serially converted data, and n serial data output terminals corresponding to each of the above n data input terminals, and inverse signals input to each of the above data input terminals. Phase parallel data is applied to the first input terminal, and the load signal is applied to the second input terminal.
n NAND circuits provided corresponding to each of the NAND circuits, and a first input terminal to which data signals output from the NAND circuits are respectively provided, and a flip-flop provided at the previous stage. It has a second input terminal to which a data signal derived from the output terminal of the flip-flop is applied, and a D-flip-flop that outputs the AND of the signals applied to these terminals, and is provided at the first stage. While constantly supplying the logic level "1" to the second data input terminal of the D-flip-flop,
The output of the D-flip-flop provided at the final stage is supplied to the serial data output terminal.

<Operation> A D-flip-flop that has first and second data input terminals and outputs the logical sum of signal levels supplied to these data input terminals, or outputs the logical product of the respective signal levels mentioned above. An n-bit shift register is formed using n D-flip-flops, and the data given in parallel is read into each D-flip-flop once every n clocks, and during the period when no data is being read, the above The read data is serially transferred to the next stage D-flip-flop in synchronization with the clock, and is output as serial data from the final stage D-flip-flop. As a result, by adding one gate circuit to each D-flip-flop, it is possible to select the data to be sent to the next D-flip-flop, and a gate circuit is added to the critical bus between each D-flip-flop. It becomes possible to configure a conversion circuit without intervening.

<Embodiment> FIG. 1 is a configuration diagram of a data parallel/serial conversion circuit showing an embodiment of the present invention, and FIG. 2 is a configuration diagram showing the circuit configuration of the D-flip-flop DFF in FIG. 1. be.

The data parallel/serial conversion circuit of the embodiment is configured as a circuit that multiplexes 4-bit data supplied in parallel and converts it into series, and has a clock signal input terminal CL, a load signal input terminal LD, and a 4-bit inverse Phase parallel data input terminals PDI to PD4. Input/output terminals such as serial data output terminal SD and four D-flip-flops DFFl~
It has DFF4 and four NOR gates N0R1 to N0R4.

The clock signal input terminal CL is connected to each D-flip-flop D.
It is connected to the clock terminal C of FF1 to DFF4, and the load signal input terminal LD is connected to the second input terminal of each NOR gate N0R1 to N0R4. In addition, each parallel data input terminal PDI to PD4 is a NOR gate N0.
The output terminals of the NOR gates N0R1 to N0R4 are connected to the first data input terminals D1 of the D-flip-flops DFFI to DFF4. First to third D-flip-flops DFF
The output terminals Q of 1 to DFF3 are respectively connected to the second to fourth D-
The fourth D-flip-flop D is connected to the second data input terminal D2 of the flip-flops DFF2 to DFF4.
The output terminal Q of FF4 is connected to the serial data output terminal SD. Also, the first D-flip frozzo DF
The second data input terminal D2 of F1 is grounded and always supplied with logic level 0''.

In addition, the 4D flip-flops DFFI to DFF4 are
It is composed of six NOR gates Nl to N6, and the clock terminal C is connected to the second and third NOR gates N2. It is connected to the second input terminal of N3. The first data input terminal DI is connected to the second input terminal of the fourth NOR gate N4, and the second data input terminal D2 is connected to the third input terminal of the fourth NOR gate N4.

Moreover, each output terminal of each of the first to fourth NOR gates Nl to N4 is connected as follows. That is, the output terminal of the first NOR gate Nl is connected to the first input terminal of the second NOR gate N2, and the output terminal of the second NOR gate N2 is connected to the second input terminal of the first NOR gate N1, the third and 5 Noah Gate N3. The output terminal of the third NOR gate N3 is connected to the first input terminal of the fourth NOR gate N4 and the second input terminal of the sixth NOR gate N6.

Further, the output terminal of the fourth NOR gate N4 is the first input terminal of the first NOR gate Nl and the third NOR gate)
The fifth NOR gate N5 is connected to the third input terminal of N5.
The output terminal of the sixth NOR gate is connected to the Q terminal and the first input terminal of the sixth NOR gate, and the output terminal of the sixth NOR gate N6 is connected to the second input terminal of the fifth NOR gate N5.

With this configuration, the D-flip-flops DFF1 to DFF4 of the embodiment change the logic of the first and second data input terminals D□ and D2 at the falling edge of the clock signal CLK applied to the clock terminal C. An edge-triggered type that outputs the OR of levels - acts as a flip-flop.

The load signal LDP supplied to the load signal input terminal LD in the data parallel/serial conversion circuit of the embodiment is normally supplied at "1" and is inverted to "0" once every four clocks. On the other hand, the first D-flip-flop DFF1
The logic level of the second data input terminal D2 is always “0”
Therefore, after the load signal LDP becomes "0" and 3 clocks have passed, the first to third D-flip-flops DFF
The Q outputs of DFF1 to DFF3 become "0". And then,
When the load signal LDP is "L" and the clock signal CLK falls, the first to fourth D-flip-flops DFFI
~DFF4 has a negative phase parallel data input terminal PDI~
The data given to PD4 are each latched. These data are transferred in synchronization with the clock signal CLK and are serially output from the serial data output terminal SD.

In the case of the circuit of the embodiment, no gate is provided on the critical path between the respective D-flip-flops DFF. Therefore, when operating as a data parallel/serial conversion circuit in this way, the The transfer speed can be significantly improved compared to the conventional circuit shown, and high-speed operation becomes possible. In addition, in the case of the circuit of the embodiment, the D-flip-flop DF per l bit
The circuit configuration can be simplified because it can be constructed by providing only one F and one NOR gate. Therefore, the number of elements can be reduced and power consumption can also be reduced.

It should be noted that the NOR gates N0R1 to N0R4 in FIG. A similar conversion operation can be performed by arranging that D2 is always supplied with "1" and the load signal input terminal LD is supplied with the load signal LDP which becomes "1" only once every four clocks.

<Effects of the Invention> As described above, the present invention has the first and second data input terminals, and in the invention of claim 1, the logical sum of the signal levels supplied to these data input terminals is output. D
- n flip-flops are used, and in the invention of claim 2, n D-flip-flops that output the AND of the respective signal levels are used, each forming an n-bit shift register, and the signals are provided in parallel. The data to be read is read into each D-flip-flop once every n clocks, and during periods when no reading is performed, the read data is serially transferred to the next-stage D-flip-flop in synchronization with the clock. Since the final stage D-flip-flop is output as serial data, one gate circuit is provided for each D-flip-flop.
By attaching individual D-flip-flops, it is possible to select the data to be sent to the next D-flip-flop, and it is also possible to configure a conversion circuit without intervening gates on the critical bus between each D-flip-flop. become.

Therefore, the circuit configuration can be simplified and the number of elements can be reduced, and power consumption can also be reduced. Furthermore, since the circuit is constructed without intervening gates between each flip-flop, high-speed operation is possible.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a data parallel/serial conversion circuit showing an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of the D-flip-flop in FIG. 1, and FIG. A circuit configuration diagram showing an example of a conventional data parallel/serial conversion circuit. FIG. 4 is an operation waveform diagram of each part of FIG. 3. PD...Negative phase parallel data input terminal. D□...First data input terminal. D2...Second data input terminal. C...Clock terminal. CLK...Clock signal. SD...Serial data output terminal. LDP...Load signal. DFF・-・D-Flip-flop. NOR...Noah Gate.

Claims (2)

[Claims] (1) n external data input terminals provided for inputting n-bit anti-phase parallel data to be converted into parallel/serial, and a clock signal serving as a reference for the operation of converting the above-mentioned anti-phase parallel data into parallel/serial conversion. A clock signal input terminal for inputting a clock signal, and a load signal input terminal for inputting a load signal whose logic level is inverted to "0" every n clocks of the above clock signal. A serial data output terminal is provided for outputting data, and n terminals are provided corresponding to each of the above n data input terminals. a NOR circuit to which the load signal is applied to a second input terminal; A D-flip-flop which has a second input terminal to which a data signal derived from an input terminal and an output terminal of a flip-flop provided in the previous stage is applied, and outputs a logical sum of the signals applied to these terminals. and the second D-flip-flop provided in the first stage.
A data parallel device characterized in that a logic level "0" is always supplied to the data input terminal of the device, and the output of a D-flip-flop provided at the final stage is supplied to the serial data output terminal. /Serial conversion circuit. (2) n external data input terminals provided for inputting n-bit anti-phase parallel data to be converted into parallel/serial, and a clock signal serving as a reference for the operation of converting the above-mentioned anti-phase parallel data into parallel/serial conversion. A clock signal input terminal for inputting the clock signal, and a load signal input terminal for inputting a load signal whose logic level is inverted to "1" every n clocks of the above clock signal. A serial data output terminal is provided for outputting data, and n terminals are provided corresponding to each of the above n data input terminals. and a first NAND circuit provided with n NAND circuits corresponding to each of the NAND circuits, each of which receives a data signal output from the NAND circuit. A D-flip-flop which has a second input terminal to which a data signal derived from an input terminal and an output terminal of a flip-flop provided in the preceding stage is applied, and outputs a logical product of the signals applied to these terminals. , the logic level "1" is always supplied to the second data input terminal of the D-flip-flop provided in the first stage, and the output of the D-flip-flop provided in the final stage is connected to the serial A data parallel/serial conversion circuit characterized in that the data is supplied to a data output terminal.