KR100242388B1 - Inner clock signal generating circuit - Google Patents

Abstract

The internal clock signal generation circuit that can effectively model a wide range of clock signals input from the outside and output the internal clock signal has an additional delay even when the locking range is widened due to the change in the period of the external clock signal CLOCK_IN. In order to eliminate the need for a stage, a delay circuit that outputs a delayed clock signal CLOCK_IND with a constant delay to the external clock signal CLOCK_IN can be added to make the locking range wider without adding a delay stage. Therefore, the clock access time and current consumption until outputting the layout area and the data of the memory chip can be reduced.

Description

Internal Clock Signal Generation Circuit

The present invention relates to an internal clock signal generation circuit, and more particularly, to an internal clock signal generation circuit capable of outputting an internal clock signal by effectively modeling a wide range of clock signals input from the outside.

As the technology of the memory device is gradually developed, the operating speed of the memory chip is getting faster.

However, since it has a certain delay time to receive an external clock signal and generate an internal clock signal suitable for operating the memory chip, the clock access time from the external clock signal to outputting the data of the memory chip. There is a limit to the reduction.

To solve this limitation, PLL (Phase Locked Loop) or DLL (Delay Locked Loop) is used to reduce the delay time of external clock signal and internal clock signal or to make the internal clock signal faster than external clock signal for very fast clock access. You can get the clock access time.

FIG. 1 is a conventional internal clock signal generation circuit diagram, and FIG. 2 is a timing diagram of the clock signal generation circuit of FIG.

The input external clock signal CLOCK_IN is input from the first delay stage (Delay Stage 1) of the first to n th delay stages (Delay Stage 1) connected in series with each flip-flop (FF1 to FFn). Is applied to the clock signal CLK and the input of the first N-type transmission switch TG1. The first N-type transmission switch TG1 and the first P-type transmission switch / TG1 have a gate grounded and an output terminal. This joint outputs the internal clock signal CLOCK_OUT.

The clock_data CLOCK_Di, which is an output between the first to nth delay stages (Delay Stage 1 to Delay Stage n), is the data D and the first to nth flip-flops FF1 to FFn, respectively. It is applied to the inputs of the 2nd to n + 1N type transmission switches (TG2 to TGn + 1). The outputs Q1 to Qn of the first to nth flip-flops FF1 to FFn are inverted through the first to nth inverters INV1 to INVn, respectively, to respectively the first to nth NOR gates NOR1 to NORn. ) And the outputs Q2 to Qn + 1 of the second to n + 1 flip-flops FF1 to FFn + 1 are directly input to the respective first to n-th NOR gates NOR1 to NORn. Outputs of the first to n-th NOR gates NOR1 to NORn include second to n + 1N-type transmission switches TG2 to TGn + 1 and second to n + 1 P-type transmission switches TG2 to TGn. It is input to the gate signal of +1), respectively. The outputs of the second to n + 1 N-type transmission switches (TG2 to TGn + 1) and the second to n + 1 P-type transmission switches (/ TG2 to / TGn + 1) are first to n-th P-type. It is applied to the input of the transmission switch.

The clock_data CLOCK_Di shown in the timing diagram of FIG. 2 is a signal obtained by delaying the input external clock signal CLOCK_IN in the first to nth delay stages (Delay Stage 1 to Delay Stage n). The clock data CLOCK_Di is clocked to the external clock signal CLOCK_IN to generate Qi, which is an output of the flip-flop.

Referring to FIG. 2, Q1 and Q2, which are outputs of the first flip-flop FF1 and the second flip-flop FF2 at time TO, are “LOW”, the third flip-flop FF3, and the fourth flip-flop FF4. Q3 and Q4, which are the outputs of the Q1, Q5 and Q6 and Q7, which are the outputs of “HIGH”, the fifth flip-flop FF5 and the sixth flip-flop FF6, and the seventh flip-flop FF7, are set to “LOW”. . Accordingly, the fifth N-type transmission switch TG5 connected to the fourth clock data CLOCK_D4 is turned on by comparison logic, and the fourth clock_data (5) is connected to the fifth P-type transmission switch / TG 5. After the CLOCK_D4 is applied, the fourth clock_data CLOCK_D4 is output as the internal clock signal CLOCK_OUT when the fifth P-type transmission switch / TG 5 is turned on.

That is, when the clock_data signal CLOCK_Di becomes "LOW" when the external clock signal CLOCK_IN rises, the output signal Qi of the flip-flop becomes "LOW", so Qi-1 is "HIGH" and Qi is The clock_data (CLOCK_Di) of the stage which is "LOW" is at the same timing as the external clock signal (CLOCK_IN). Accordingly, the signal “LOW” and Qi signal “LOW” in which Qi-1 is inverted by the n-1 inverter INVn-1 are inputted to the n-1 NOR gate NOR1 to output a “HIGH” signal. When the n-type transmission switch (TG n) is turned on, the clock_data (CLOCK_Di) signal, in which the external clock signal (CLOCK_IN) is delayed by a predetermined time, that is, the fourth clock_data (CLOCK_D4) signal is converted into the external clock signal (CLOCK_IN). Can be output as a faster internal clock signal (CLOCK_OUT). Where n = i.

Since the range in which the conventional circuit can be locked is determined by seven delay stages, a delay stage, a flip-flop (FF), and an inverter (INV) may be used to have a wider locking range. ), Transmission switches (TG, / TG) and NOR gates (NOR) should be added.

However, this method requires a large number of clock cycles to lock the external clock signal CLOCK_IN and the internal clock signal CLOCK_OUT, so the clock access time from the external clock signal to outputting the data of the memory chip. (clock access time) is long, the current consumption is high because the circuit has to be "on" even in the standby state without the external clock signal (CLOCK_IN) for a while.

Accordingly, an object of the present invention is that even if the external clock signal has a wide locking range, the clock access time from the external clock signal to the data output from the memory chip is not long, and the external clock signal is short for a while. The present invention provides an internal clock signal generation circuit that can reduce current consumption by “off” the circuit even in a standby state without (CLOCK_IN).

In order to achieve the above object, the internal clock signal generation circuit according to the present invention has a delay stage, a flip-flop, a NOR gate, a tristate buffer, a tristate inverter, and an external clock signal CLOCK_IN. It also includes a delay circuit section that, even with a wide range, does not require the installation of additional delay stages.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a conventional internal clock signal generation circuit diagram.

2 is a timing diagram of a conventional internal clock signal generation circuit.

3 is an internal clock signal generation circuit diagram according to the present invention.

4 is a timing diagram of an internal clock signal generation circuit according to the present invention.

4 (a) is when CLOCK-IN is within the locking range by the delay stage.

4 (b) is when CLOCK-IN is not within the locking range by the delay stage.

* Explanation of symbols for main parts of the drawings

100: delay circuit

3 is an internal clock signal generation circuit diagram according to the present invention, and FIG. 4 is a timing diagram of an internal clock signal generation circuit according to the present invention.

The internal clock signal generation circuit according to the present invention includes a delay circuit 100 that receives an external clock signal CLOCK_IN and first to seventh delay stages (Delay Stage 1 to delay Stage 7) connected in series with the delay circuit 100. ) And the external clock signal CLOCK_IN as the clock signal CLK, each of the first to the second input signals receiving the outputs of the first to seventh delay stages (Delay Stage 1 to Delay Stage 7) as the clock data CLOCK_Di. The outputs Q2n-1 of the sixth flip-flops FF1 to FF6 and the odd-numbered flip-flops FF2n-1 of the first to sixth flip-flops FF1 to FF6 are each of the first to fifth inverters ( Among the INV1 to INV5, the odd-numbered inverter (INV2n-1) is input and the output of the even-numbered flip-flop (FF2) Q2n is input to the even-numbered inverter (INV2n) and the odd-numbered delay stage (Delay Stage 2n-1) Is output to each of the first to third tri-state inverters TSI1 to TSI3, and an even-numbered delay stage 2n is applied to each of the first to fourth tri-state buffers TSB1 to TSB4. The first to fifth inverters INV1 to INV5. ) And the outputs of the second to sixth flip-flops FF2 to FF6 are respectively input to the first to fifth NOR gates NOR1 to NOR5, and the first to fifth NOR gates NOR1 to NOR5. The output of is applied to the first to fifth / selection switches / G1 to G5 and the second to sixth selection switches G2 to G6, and the first selection switch G1 is grounded.

The first to seventh / selection switches / G1 to / G7 and the first to seventh selection switches G1 to G7 are paired, respectively, to the first to fourth tri-state buffers TSB1 to TSB4 and the first to seventh. The operation signal is alternately applied to the third tri-state inverters TSI1 to TSI3, and the outputs of the first to fourth tri-state buffers TSB1 to TSB4 and the first to fourth tri-state inverters TSI1 to TSI3 are jointly internal. Output the clock signal CLOCK_OUT.

Each of the delay stages includes one inverter.

The operation of the internal clock signal generation circuit of the present invention will be described in two ways.

First, FIG. 4 (a) is a timing diagram for a case where CLOCK_IN is within a locking range by a delay stage.

As shown in FIG. 4 (a), when the period of the external clock signal CLOCK_IN is smaller than the delay period of the entire delay stage, the external clock signal CLOCK_IN is delayed in advance in the delay circuit 100. To output the delayed clock signal CLOCK_IND between the times T1 to T2.

Q1 and Q2, which are the outputs of the first flip-flop FF1 and the second flip-flop FF2, are "LOW" at time T2, and Q3 and Q4, which are the outputs of the third flip-flop FF3 and the fourth flip-flop FF4. Is "HIGH", Q5 which is the output of the fifth flip-flop FF5 is "LOW".

At time T2, the fourth clock data CLOCK_D4 sequentially rotates the first through fourth tri-state buffers TSB1 through TSB4 and the first through third tri-state inverters TSI1 through the delay time of the clock data CLOCK_Di. TSI3) are alternately operated and output as the internal clock signal CLOCK_OUT.

That is, the external clock signal CLOCK_IN is not locked at time T1 but is locked at time T2 to output the fourth clock data CLOCK_D4 as the internal clock signal CLOCK_OUT.

4 (b) is a timing diagram when CLOCK_IN is not within the locking range by the delay stage.

As shown in FIG. 4 (b), when the period of the external clock signal CLOCK_IN is greater than the delay period of the entire delay stage, the external clock signal CLOCK_IN is fixed through the delay circuit 100. Even when the delay clock signal CLOCK_IND having a delay period is output, the internal clock signal CLOCK_OUT is locked at time T1 to output the fourth clock data CLOCK_D4.

Therefore, the present invention can make the external clock signal CLOCK_IN delay clock signal CLOCK_IND having a constant delay, thereby making it possible to widen the locking range without adding a delay stage. The clock access time and current consumption until the output can be reduced.

Claims (2)

An internal clock signal generation circuit for effectively modeling an external clock signal CLOCK_IN input to an external device and outputting an internal clock signal CLOCK_OUT, comprising: a delay circuit for receiving the external clock signal CLOCK_IN and the external clock signal ( A first tri-state buffer receiving CLOCK_IN, a first to seventh delay stage (Delay Stage 1 to Delay Stage 7) connected in series with the delay circuit, and the external clock signal CLOCK_IN to a clock stage CLK. The first to sixth flip-flops FF1 to FF6 and the first to seventh delay stages (Delay Stage 1 to Delay Stage 7) and the outputs of the first to seventh stages, respectively, to the data stages D; The odd-numbered inverters of the first to fifth inverters INV1 to INV5 respectively receiving the inverted outputs / Q2n-1 of the odd-numbered flip-flop FF2n-1 among the sixth flip-flops FF1 to FF6. INV2n-1 and among the first to fifth inverters INV1 to INV5 respectively receiving the outputs Q2n of even flip-flops FF2n among the first to sixth flip-flops FF1 to FF6. First to fifth knock gates to which even-numbered inverters INV2n, outputs of the first to fifth inverters INV1 to INV5, and outputs of the second to sixth flip-flops FF2 to FF6 are input. NOR1 to NOR5 and first to third tri-state inverters receiving the outputs of the odd-numbered delay stages (Delay Stage 2n-1) of the first to seventh delay stages (Delay Stage 1 to Delay Stage 7). TSI1 to TSI3 and second to fourth tri-state buffers TSB2 to receiving outputs of even-numbered delay stages (Delay Stage 2n) of the first to seventh delay stages (Delay Stage 1 to Delay Stage 7), respectively. TSB4), second to sixth selection switches G2 to G6 connected to output terminals of the first to fifth NOR gates NOR1 to NOR5, and a first selection switch G1 connected to ground, and the first The first to fourth tri-state buffers TSB1 to TSB4 and the first to third tri-state inverters TSI1 to TSI3 are alternately connected in series with each of the sixth selection switches G2 to G6. ) First to sixth / selection switch (/ G2 ~) configured to apply an operation signal alternately to / G6), and the outputs of the first to fourth Samsung-type buffers TSB1 to TSB4 and the first to third tri-state inverters TSI1 to TSI3 jointly internal clock signals CLOCK_OUT. Internal clock signal generation circuit characterized in that the output. The internal clock signal generation circuit of claim 1, wherein the delay stage comprises one inverter.

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