KR19990012641A - Internal Clock Signal Generation Circuit - Google Patents
Internal Clock Signal Generation Circuit Download PDFInfo
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- KR19990012641A KR19990012641A KR1019970036114A KR19970036114A KR19990012641A KR 19990012641 A KR19990012641 A KR 19990012641A KR 1019970036114 A KR1019970036114 A KR 1019970036114A KR 19970036114 A KR19970036114 A KR 19970036114A KR 19990012641 A KR19990012641 A KR 19990012641A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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Abstract
외부에서 입력되는 넓은 범위의 클럭신호를 효과적으로 모델링하여 내부 클럭신호를 출력시킬 수 있는 내부 클럭신호 발생회로는 입력되는 외부 클럭신호(CLOCK_IN)의 주기가 변하여 로킹(LOCKING)범위가 넓어져도 추가의 지연단이 필요없도록 하기 위하여 외부 클럭신호(CLOCK_IN)를 일정한 지연을 가지는 지연 클럭신호(CLOCK_IND)를 출력하는 지연회로부를 추가하여 지연단(Delay Stage)을 추가하지 않고 로킹(LOCKING)범위를 넓게 만들 수 있으므로 레이아웃 면적과 메모리 칩의 데이터를 출력하기까지의 클럭 억세스 타입(clock access time) 및 전류소비를 줄일 수 있다.The internal clock signal generation circuit that can effectively model a wide range of clock signals input from the outside and output the internal clock signal has an additional delay even when the locking range is widened due to the change in the period of the external clock signal CLOCK_IN. In order to eliminate the need for a stage, a delay circuit unit for outputting a delay clock signal CLOCK_IND with a constant delay to the external clock signal CLOCK_IN can be added to increase the locking range without adding a delay stage. Therefore, the clock access time and current consumption until outputting the layout area and data of the memory chip can be reduced.
Description
본 발명은 내부 클럭신호 발생회로에 관한 것으로서, 특히 외부에서 입력되는 넓은 범위의 클럭신호를 효과적으로 모델링하여 내부 클럭신호를 출력시킬 수 있는 내부 클럭신호 발생회로에 관한 것이다.The present invention relates to an internal clock signal generation circuit, and more particularly, to an internal clock signal generation circuit capable of outputting an internal clock signal by effectively modeling a wide range of clock signals input from the outside.
메모리 소자의 기술이 점차 발전함에 따라 메모리 칩의 동작속도가 점점 고속화 되어가고 있다.As the technology of the memory device is gradually developed, the operating speed of the memory chip is getting faster.
그러나 외부의 클럭신호를 입력받아 메모리 칩을 동작시키기에 적당한 내부 클럭신호를 발생시키기까지는 일정한 지연시간을 가지므로 외부의 클럭신호로부터 메모리 칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time)을 줄이는데는 한계가 있다.However, since it has a certain delay time to receive an external clock signal and generate an internal clock signal suitable for operating the memory chip, the clock access time from the external clock signal to outputting the data of the memory chip. There is a limit to the reduction.
이러한 한계를 개선하기 위하여 PLL(Phase Locked Loop) 또는 DLL(Delay Locked Loop)를 이용하여 외부 클럭신호와 내부 클럭신호의 지연시간을 줄이거나 내부 클럭신호를 외부 클럭신호보다 좀더 빠르게하여 매우 빠른 클럭 억세스 타임(clock access time)을 얻을 수 있다.To overcome this limitation, PLL (Phase Locked Loop) or DLL (Delay Locked Loop) can be used to reduce the delay time of external clock signal and internal clock signal or to make the internal clock signal faster than external clock signal for very fast clock access. You can get the clock access time.
도 1은 종래의 내부 클럭신호 발생회로도이고, 도 2는 도 1의 내부 클럭신호 발생회로의 타이밍도이다.1 is a conventional internal clock signal generation circuit diagram, and FIG. 2 is a timing diagram of the internal clock signal generation circuit of FIG. 1.
입력되는 외부 클럭신호(CLOCK_IN)는 직렬로 연결된 제1∼제n지연단(Delay Stage 1∼Delay Stage n)중 제1지연단(Delay Stage 1)의 입력과 각각의 플립플롭(FF1∼FFn)의 클럭신호(CLK) 그리고 제1 N형 트랜스미션 스위치(TG1)의 입력에 인가되고 제1 N형 트렌스미션 스위치(TG1)와 제1 P형 트렌스미션 스위치(/TG1)는 게이트가 어스되고 출력단이 공동으로 내부 클럭신호(CLOCK_OUT)를 출력한다.The input external clock signal CLOCK_IN is input from the first delay stage (Delay Stage 1) and the respective flip-flops (FF1 to FFn) of the first to nth delay stages (Delay Stage 1 to Delay Stage n) connected in series. Is applied to the clock signal CLK and the input of the first N-type transmission switch TG1, and the first N-type transmission switch TG1 and the first P-type transmission switch / TG1 are gated and the output terminal Output the internal clock signal CLOCK_OUT jointly.
각각의 제1∼제n지연단(Delay Stage 1∼Delay Stage n)사이 사이의 출력인 클럭_데이타(CLOCK_Di)은 각각 제1∼제n 플립폴롭(FF1∼FFn)의 데이터(D)와 제2∼제n+1 N형 트렌스미션 스위치(TG 2∼TG n+1)의 입력에 인가된다. 상기 제1∼제n 플립폴롭(FF1∼FFn)은 출력(Q1∼Qn)은 각각 제1∼제n인버터(INV 1∼INV n)을 거쳐 반전되어 각각의 제1∼제2n 노어게이트(NOR1∼NORn)에 입력되고 제2∼제n+1 플롭(FF2∼FFn+1)의 출력(Q2∼Qn+1)은 바로 각각의 제1∼제n 어게이트(NOR1∼NORn)에 입력된다. 상기 제1∼제n 노어게이트(NOR1∼NORn)의 출력은 제2∼제n+1 N형 트렌스미션 스위치(TG 2∼TG n+1)와 제2∼제n+1 P형 트렌스미션 스위치(/TG 2∼/TG n+1)의 게이트 신호로 각각 입력된다. 상기 제2∼제n+1 P형 트렌스미션 스위치(TG 2∼TG n+1)와 제2∼제n+1 P형 트렌스미션 스위치(/TG 2∼/TG n+1)의 출력은 제1∼제n P형 트렌스미션 스위치의 입력으로 인가된다.The clock data CLOCK_Di, which is an output between the first to nth delay stages (Delay Stage 1 to Delay Stage n), is the data D and the first to nth flip-flop FF1 to FFn, respectively. It is applied to the input of the 2nd -n + 1th N type transmission switches TG2-TGn + 1. The first to nth flip-flops FF1 to FFn are inverted through the first to nth inverters INV 1 to INV n, respectively, and the outputs Q1 to Qn are each of the first to second n-th gate NOR1. The inputs Q2 to Qn + 1 of the second to n + 1 flops FF2 to FFn + 1 are directly input to the respective first to nth gates NOR1 to NORn. The outputs of the first to nth NOR gates NOR1 to NORn include second to n + 1N type transmission switches TG 2 to TG n + 1 and second to n + 1 P type transmission switches. It is input to the gate signals of (/ TG 2 to / TG n + 1), respectively. The outputs of the second to n + 1 P-type transmission switches (TG 2 to TG n + 1) and the second to n + 1 P-type transmission switches (/ TG 2 to / TG n + 1) It is applied to the input of the 1st to nth P-type transmission switches.
도 2의 타이밍도에 나타낸 클럭_데이타(CLOCK_Di)는 입력되는 외부 클럭신호(CLOCK_IN)를 제1∼제n지연단(Delay Stage 1∼Delay Stage n)에서 지연시킨 신호이다.The clock_data CLOCK_Di shown in the timing diagram of FIG. 2 is a signal obtained by delaying the input external clock signal CLOCK_IN at the first to nth delay stages (Delay Stage 1 to Delay Stage n).
시간 T0∼T1에서 제1플립프롭(FF1)과 제2플립프롭(FF2)의 출력인 Q1과 Q2는 LOW, 제3플립프롭(FF3)과 제4플립프롭(FF4)의 출력인 Q3과 Q4는 HIGH, 제5플립프롭(FF5)과 제6플립프롭(FF6) 및 제7플립프롭(FF7)의 출력인 Q5와 Q6 및 Q7은 LOW가 된다.Q1 and Q2, which are the outputs of the first flip-flop FF1 and the second flip-flop FF2, are LOW, and Q3 and Q4, which are the outputs of the third flip-flop FF3 and the fourth flip-flop FF4, at times T0 to T1. Is HIGH, Q5, Q6, and Q7, which are outputs of the fifth flip-flop FF5, the sixth flip-flop FF6, and the seventh flip-flop FF7, become LOW.
상기 T1∼T2에서 클럭_데이타4(CLOCK_D4)가 제5 N형 트렌스미션 스위치(TG5)가 온되어 제5 P형 트렌스미션 스위치(/TG 5)에 인가된후 제5 P형 트렌스미션 스위치(/TG 5)에서 제1 P형 트렌스미션 스위치(TG 1)가 클럭_데이타(CLOCK_Di)의 지연시간에 의하여 순차적으로 온되어 내부 클럭신호(CLOCK_OUT)로 출력한다.In the T1 to T2, the clock_data4 (CLOCK_D4) is turned on and is applied to the fifth P-type transmission switch / TG 5 after the fifth N-type transmission switch TG5 is turned on. In / TG 5), the first P-type transmission switch TG 1 is sequentially turned on by the delay time of the clock_data CLOCK_Di and outputs the internal clock signal CLOCK_OUT.
즉 외부 클럭신호(CLOCK_IN)가 상승할 때 클럭_데이타(CLOCK_Di)가 LOW가 되면 Qi신호가 LOW가 Qi-1은 HIGH가 된다. 따라서 제n-1인버터(INV n-1)를 자나 반전된 /Qi-1 LOW와 Qi신호 LOW는 제n-1노어게이트(NOR n-1)에 입력되어 HIGN신호를 출력하여 제n N형 트렌스미션 스위치(TG n)를 온시키면 외부 클럭신호(CLOCK_IN)보다 임의의 지연시간을 가진 클럭_데이타(CLOCK_Di)를 외부 클럭신호(CLOCK_IN)보다 빠른 내부 클럭신호(CLOCK_OUT)로 출력할 수 있다. 상기에서 n=I이다.That is, when the clock_data (CLOCK_Di) becomes LOW when the external clock signal CLOCK_IN rises, the Qi signal becomes LOW and Qi-1 becomes HIGH. Therefore, the / Qi-1 LOW and the inverted / Qi-1 LOW and the Qi signal LOW, which are formed by the n-1 inverter INV n-1, are input to the n-1 north gate NOR n-1 to output a HIGN signal to output the nth N type. When the transmission switch TG n is turned on, the clock_data CLOCK_Di having a random delay time than the external clock signal CLOCK_IN may be output as the internal clock signal CLOCK_OUT faster than the external clock signal CLOCK_IN. N = I in the above.
상기 종래의 회로가 로킹(LOCKING)할 수 있는 범위는 7개의 지연단에 의하여 결정되므로 좀더 넓은 로킹(LOCKING)범위를 가지려면 지연단(Delay Stage)과 이에 따르는 플롭플롭(FF)과 인버터(INV)와 트렌스미션 스위치(TG,/TG)와 노어게이트(NOR)를 늘려야 한다.Since the range in which the conventional circuit can be locked is determined by seven delay stages, a delay stage, a flop flop (FF), and an inverter (INV) are required to have a wider locking range. ), Transmission switches (TG, / TG) and NOR gates (NOR) should be increased.
그러나 이러한 방법은 외부 클럭신호(CLOCK-IN)와 내부 클럭신호(CLOCK-OUT)를 로킹(LOCKING)시키기까지 많은 수의 클럭 사이클이 필요하므로 외부의 클럭신호로부터 메모리 칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time)이 길고 잠시 외부 클럭신호(CLOCK-IN)가 없는 대기상태에서도 회로를 온시켜야 하기 때문에 전류소비가 많은 문제점을 가진다.However, this method requires a large number of clock cycles to lock the external clock signal (CLOCK-IN) and internal clock signal (CLOCK-OUT). Current consumption is problematic because the clock access time is long and the circuit must be turned on even in a standby state without an external clock signal CLOCK-IN for a while.
따라서 본 발명의 목적은 외부 클럭신호가 로킹 범위가 넓어도 효과적으로 모델링하여 외부의 클럭신호로부터 메모리 칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time)이 길어지지 않아 잠시 부 클럭신호(CLOCK-IN)가 없는 대기상태에서도 회로를 오프시켜 전류소비를 줄일 수 있는 내부 클럭신호 발생회로를 제공하는데 있다.Accordingly, an object of the present invention is to effectively model the external clock signal even if the locking range is wide so that the clock access time from outputting the data of the memory chip to the external clock signal is not long. The present invention provides an internal clock signal generation circuit that can reduce current consumption by turning off a circuit even in a standby state without -IN).
상기 목적을 달성하기 위한 본 발명에 따른 내부 클럭신호 발생회로는 지연단(Delay Stage)과 프립플롭과 노어게이트와 삼상태 버퍼와 삼상태 인버터 및 외부 클럭신호(CLOCK-IN)의 주기가 변하여 로킹(LOCKING)범위가 넓어도 추가의 지연단을 설치할 필요가 없는 지연회로부를 포함한다.The internal clock signal generation circuit according to the present invention for achieving the above object is locked by changing the period of the delay stage, the flip-flop, the knock gate, the tri-state buffer, the tri-state inverter and the external clock signal (CLOCK-IN) It includes a delay circuit section that does not need to install an additional delay stage even if the (LOCKING) range is wide.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1는 종래의 내부 클럭신호 발생회로도1 is a conventional internal clock signal generation circuit diagram
도 2는 종래의 내부 클럭신호 발생회로의 타이밍도2 is a timing diagram of a conventional internal clock signal generation circuit.
도 3은 본 발명에 따른 내부 클럭신호 발생회로도3 is an internal clock signal generation circuit diagram according to the present invention;
도 4는 본 발명에 따른 내부 클럭신호 발생회로의 타이밍도4 is a timing diagram of an internal clock signal generation circuit according to the present invention.
(a) CLOCK-IN이 지연단에 의한 로킹(locking)범위에 있을때(a) When CLOCK-IN is in the locking range by delay stage
(b) CLOCK-IN이 지연단에 의한 로킹(locking)범위에 없을 때(b) When CLOCK-IN is not in the locking range by delay stage
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100:지연회로부100: delay circuit
도 3은 본 발명에 따른 내부 클럭신호 발생회로도이고 도 4는 본 발명에 따른 내부 클럭신호 발생회로의 타이밍도이다.3 is an internal clock signal generation circuit diagram according to the present invention, and FIG. 4 is a timing diagram of an internal clock signal generation circuit according to the present invention.
본 발명에 따른 내부 클럭신호 발생회로는 외부 클럭신호(CLOCK_IN)를 입력받는 지연회로(100) 및 제1삼상태버퍼와 상기 지연회로(100)에 직렬로 연결된 제1∼제7지연단(Delay Stage 1∼Delay Stage 7)과 외부 클럭신호(CLOCK_IN)를 클럭신호(CLK)로 제1∼제7지연단(Delay Stage 1∼Delay Stage 7)의 출력을 클럭_데이타(CLOCK_Di)는 입력받는 각각의 제1∼제6플립플롭((FF1∼FF6)과, 상기 제1∼제6플립플롭(FF1∼FF6)중 홀수번째 플립플롭(FF2n-1)의 반전된 출력(/Q2n-1)은 각각의 제1∼제5인버터(INV1∼5)중 홀수번째 인버터(INV 2n-1)에 입력되고 짝수번째 플립플롭(FF2n)의 출력(Q2n)은 짝수번째 인버터(INV 2n)에 입력되며, 홀수번째 지연단(Delay Stage 2n-1)의 출력은 각각의 제1∼제3삼상태인버터(TSI 1∼TSI 3)에 입력되고 짝수번째 지연단(Delay Stage 2n)의 출력은 각각의 제1∼제4삼상태버퍼(TSB 1∼TSB 4)에 인가되며, 상기 제1∼제5인버터(INV 1∼INV 5)의 출력과 제2∼제6의 플립플롭(FF2∼FF6)의 출력(/Q2n-1, Q2n)은 각각 제1∼제5 노어 게이트(NOR 1∼NOR 5)에 입력되고, 상기 제1∼제5 노어게이트(NOR 1∼NOR 5)의 출력은 제1∼제5/선택스위치(/G1∼/G5) 및 제2∼제6선택스위치(G2∼G6)에 인가되고 제1선택스위치(G1)는 접지된다.The internal clock signal generation circuit according to the present invention includes a delay circuit 100 that receives an external clock signal CLOCK_IN, and first through seventh delay stages connected in series to the first tri-state buffer and the delay circuit 100. The outputs of the first to seventh delay stages (Delay Stage 1 to Delay Stage 7) are input to the stage 1 to Delay Stage 7) and the external clock signal CLOCK_IN as the clock signal CLK, respectively. The inverted outputs / Q2n-1 of the first to sixth flip-flops (FF1 to FF6) and the odd-numbered flip-flops FF2n-1 of the first to sixth flip-flops FF1 to FF6 are Each of the first to fifth inverters INV1 to 5 is input to the odd-numbered inverter INV 2n-1, and the output Q2n of the even-numbered flip-flop FF2n is input to the even-numbered inverter INV 2n. The output of the odd delay stage 2n-1 is input to each of the first to third tri-state inverters TSI 1 to TSI 3, and the output of the even delay stage 2n-1 is each first To the fourth tri-buffer (TSB 1 to TSB 4) The outputs of the first to fifth inverters INV 1 to INV 5 and the outputs / Q2n-1 and Q2n of the second to sixth flip-flops FF2 to FF6 are respectively the first to fifth norms. The first to fifth NOR gates NOR 1 to NOR 5 are input to the gates NOR 1 to NOR 5, and the outputs of the first to fifth NOR gates NOR 1 to NOR 5 are first to fifth / selection switches / G1 to / G5 and second to fifth agents. It is applied to six selection switches G2 to G6 and the first selection switch G1 is grounded.
제1∼제7/선택스위치(/G1∼/G7)와 제1∼제7선택스위치(G1∼G7)는 각각 쌍을 이루어 각각 제1∼제4삼상태버퍼(TSB1∼TSB4)와 제1∼제3삼상태인버퍼(TSI1∼TSI4)에 번갈아 동작신호를 인가되고 제1∼제4삼상태버퍼(TSB1∼TSB4)와 제1∼제3삼상태인버터(TSI1∼TSI4)의 출력이 제1삼상태버퍼(TSB1)의 출력단과 공동으로 내부 클럭신호(CLOCK_OUT)를 출력한다.The first to seventh / selection switches / G1 to / G7 and the first to seventh selection switches G1 to G7 are paired, respectively, and the first to fourth tri-state buffers TSB1 to TSB4 and the first to seventh, respectively. The operation signals are alternately applied to the third tri-state buffers TSI1 to TSI4, and the outputs of the first to fourth tri-state buffers TSB1 to TSB4 and the first to third tri-state inverters TSI1 to TSI4 are output to the first. The internal clock signal CLOCK_OUT is output in common with the output terminal of the tri-state buffer TSB1.
상기 각각의 지연단(Delay Stage)은 하나의 인버터로 구성된다.Each delay stage is composed of one inverter.
본 발명의 내부 클럭신호 발생회로의 동작을 두가지로 나누어 설명한다.The operation of the internal clock signal generation circuit of the present invention will be described in two ways.
(a) CLOCK_IN이 지연단에 의한 로킹(locking)범위에 있을 때.(a) When CLOCK_IN is in the locking range by delay stage.
주기 T0∼T1에서 외부 클럭신호(CLOCK_IN)의 주기가 지연단(Delay Stage)전체의 지연주기보다 작은 경우에는 외부 클럭신호(CLOCK_IN)가 지연회로(100)에서 미리 일정한 지연주기를 가져 시간 T1∼T2에 지연 클럭신호(CLOCK_IND)를 출력한다.If the period of the external clock signal CLOCK_IN in the periods T0 to T1 is smaller than the delay period of the entire delay stage, the external clock signal CLOCK_IN has a predetermined delay period in the delay circuit 100 in advance and the time T1 to The delay clock signal CLOCK_IND is output to T2.
시간 T1∼T2에서 지연 클럭신호(CLOCK_IND)가 제1플립프롭(FF1)과 제2플립프롭(FF2)의 출력인 /Q1과 Q2는 LOW, 제3플립프롭(FF3)과 제4플립프롭(FF4)의 출력인 /Q3과 Q4는 HIGH, 제5플립프롭(FF5)의 출력인 /Q5는 LOW가 된다.At times T1 to T2, the delay clock signal CLOCK_IND is the outputs of the first flip prop FF1 and the second flip prop FF2, / Q1 and Q2 are LOW, and the third flip prop FF3 and the fourth flip prop ( / Q3 and Q4, which are the outputs of FF4), are HIGH, and / Q5, which is the output of the fifth flip-flop FF5, is LOW.
시간 T2∼T3 클럭_데이타4(CLOCK_D4)가 클럭_데이타(CLOCK_Di)의 지연시간에 의하여 순차적으로 제1∼제4삼상태버퍼(TSB1∼TSB4)와 제1∼제3삼상태인버터(TSI 1∼TSI 4)를 번갈아 동작시켜 내부 클럭신호(CLOCK_OUT)로 출력한다.The time T2 to T3 clock_data 4 (CLOCK_D4) is sequentially converted into the first to fourth tri-state buffers TSB1 to TSB4 and the first to third tri-state inverters TSI 1 by the delay time of the clock_data CLOCK_Di. TSI 4) are alternately operated and output as the internal clock signal CLOCK_OUT.
즉 외부 클럭신호(CLOCK_IN)가 시간 T1에서 로킹(LOCKING)되지 않고 시간 T2에서 로킹(LOCKING)되어 내부 클럭신호(CLOCK_OUT)를 출력한다That is, the external clock signal CLOCK_IN is not locked at time T1 and is locked at time T2 to output the internal clock signal CLOCK_OUT.
(b) CLOCK_IN이 지연단에 의한 로킹(locking)범위에 없을때(b) When CLOCK_IN is not in the locking range by delay
주기 T0∼T1에서 외부 클럭신호(CLOCK_IN)의 주기가 지연단(Delay Stage)전체의 지연주기보다 큰 경우에는 외부 클럭신호(CLOCK_IN)가 지연회로(100)을 통하여 일정한 지연주기를 가지는 지연 클럭신호(CLOCK_IND)를 출력하더러도 시간 T0∼T1범위에 존재한다.If the period of the external clock signal CLOCK_IN in the period T0 to T1 is larger than the delay period of the entire delay stage, the external clock signal CLOCK_IN is a delayed clock signal having a constant delay period through the delay circuit 100. Even if (CLOCK_IND) is output, it is in the range of time T0 to T1.
시간 T0∼T1에서 지연 클럭신호(CLOCK_IND)가 제1플립프롭(FF1)과 제2플립프롭(FF2)의 출력인 /Q1과 Q2는 LOW, 제3플립프롭(FF3)과 제4플립프롭(FF4)의 출력인 /Q3과 Q4는 HIGH, 제5플립프롭(FF5)의 출력인 /Q5는 LOW가 된다.At times T0 to T1, the delay clock signal CLOCK_IND is the output of the first flip-flop FF1 and the second flip-flop FF2, / Q1 and Q2 are LOW, and the third flip-flop FF3 and the fourth flip-prop ( / Q3 and Q4, which are the outputs of FF4), are HIGH, and / Q5, which is the output of the fifth flip-flop FF5, is LOW.
시간 T1∼T2 클럭_데이타4(CLOCK_D4)가 클럭_데이타(CLOCK_Di)의 지연시간에 의하여 순차적으로 제1∼제4삼상태버퍼(TSB1∼TSB4)와 제1∼제3삼상태인버터(TSI 1∼TSI 4)를 번갈아 동작시켜 내부 클럭신호(CLOCK_OUT)로 출력한다.The time T1 to T2 clock_data 4 (CLOCK_D4) sequentially turns the first to fourth tri-state buffers TSB1 to TSB4 and the first to third tri-state inverters TSI 1 according to the delay time of the clock_data CLOCK_Di. TSI 4) are alternately operated and output as the internal clock signal CLOCK_OUT.
즉 외부 클럭신호(CLOCK_IN)가 시간 T1에서 로킹(LOCKING)되어 내부 클럭신호(CLOCK_OUT)를 출력한다.That is, the external clock signal CLOCK_IN is locked at time T1 to output the internal clock signal CLOCK_OUT.
따라서 본 발명은 외부 클럭신호(CLOCK_IN)를 일정한 지연을 가지는 지연 클럭신호(CLOCK_IND)를 만들어 지연단(Delay Stage)을 추가하지 않고 로킹(LOCKING)범위를 넓게 만들 수 있으므로 레이아웃 면적과 메모리 칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time) 및 전류소비를 줄일 수 있다.Accordingly, the present invention can make the external clock signal CLOCK_IN a delayed clock signal CLOCK_IND having a constant delay, thereby making the locking range wider without adding a delay stage. The clock access time and current consumption until the output can be reduced.
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