JPH0396014A - Synchronizing counter - Google Patents

Abstract

PURPOSE:To realize high speed processing by constituting a circuit block of each stage after 3rd and succeeding stages, of a binary counter FF, and a FF receiving an AND of output data from a 2nd stage till a preceding stage and an AND of output data of the FF and inverting an output data in response to a level of the input data. CONSTITUTION:The output of a JK FF 14 is inverted at a trailing edge of a clock pulse CK just after an AND data AND OUT(n-1) and the output data OUT(n-1) go to a high level and the output of a JK FF 16 goes to a high level. So long as the output is confirmed up to a delay of 1.5 clock period, the output of the JK FF 14 is inverted and the circuit is normally acted as a synchronizing signal counter. Since the period of a delay of 1.5 clock is allowed by taking a delay by AND gates 21-23 into account, the operation at a clock frequency thrice a conventional clock frequency is attained. Moreover, no increase in fanout due to the increase in stage number is caused and high speed operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous counter, and particularly to a synchronous counter constructed by combining a flip-flop and a logic gate. [Prior Art] Since all of the outputs of a synchronous counter change in synchronization with clock pulses, compared to an asynchronous counter in which the output changes vary from stage to stage and the delay increases as the stage progresses, it is extremely difficult to construct a digital circuit. It is useful for For example, taking a four-stage synchronous counter as an example, a circuit as shown in FIG. 4 is known as a basic first example circuit.

This circuit consists of JK flip-flops 11, 12, 13 .
14 and 2-person AND gate 21. 3-person AND gate 3
1 of the third and fourth stage JK flip-flops -13.14. The K terminal is connected to the JK flip-flops 11 and 12 in the previous stage operated by the 2-man NAD gate 21 and the 3-man NAD gate 31, respectively.
, 1l to 13, and the first stage J
The J terminal and K terminal of the K flip-flop 11 are connected to the power supply voltage V.
CC is fixed at a high level, and the output of the first-stage JK flip-flop 11 is directly input to the J and K terminals of the second-stage JK flip-flop 12. Also, each JK
A circuit clock pulse CK is commonly applied to the CLK terminals of the flip-flops 11 to 14.

Next, the operation of this circuit will be explained below.

The outputs of the JK flip-flops 11 to 14 are inverted when the levels at the J and K terminals are high, and maintain the previous output state when the levels are low.

In addition, in a counter, a certain stage is inverted when all the stages before it are at high level, so a counter can be constructed by applying the AND of all the previous stages to the J and K terminals. , also JK flip-flop 11~
Since the output of 14 changes in synchronization with the clock pulse CK, the circuit described above operates as a synchronous counter. Generally, the N-th stage circuit includes a JK flip-flop, and J terminals connected to the J and K terminals of the first stage to the (N-1)th stage.
Input the logical product of the outputs of K flip-flops (N-1
>Input AND gate.

In addition, as in the second conventional example shown in FIG.
The part for calculating the logical product of inputs to the terminals can also be configured with two cascaded AND gates 21 and 22, and this circuit also operates on the same principle as the first conventional example.

[Problem to be solved by the invention]

In the first conventional example described above, the Nth stage has the first
Since an (N-1) input AND gate is required to take the logical product from the stage to the (N-1)th stage, as the number of stages increases, the fan-out increases as the stage goes up, and the fan-out of the first stage in particular increases. When the fan-outs of the J terminal, K terminal, and the AND gate are equal (N+1), the waveform of the carry signal to the subsequent stage becomes rounded or delayed. If a master-slave type flip-flop is assumed, this delay is equal to the clock period. If it becomes larger than 172, it will no longer function as a counter that normally transmits the carry signal to the subsequent stage, and therefore,
This limit clock frequency has the disadvantage that it becomes lower as the number of stages of the counter increases.

In addition, in the second conventional example, even if the number of stages increases, the fanout of each stage can be suppressed to a maximum of 3, but in this case, AND
Since the gates are connected in cascade, there is a delay N times the transmission delay time of one two-manual AND gate from when the level of the clock pulse changes at the Nth stage until the level of the carry signal changes. , this delay time is (ts-(N-2)t), where the JK flip-flop setup time is ts and the AND gate transmission delay time is tpd.
pci), and in the case of a master-slave type, there is a drawback that if this becomes larger than 1/2 of the clock period, normal operation will not be possible.

As described above, in the conventional example, when a multi-stage synchronous counter is configured, there is a problem that the operable clock frequency becomes low.

An object of the present invention is to solve the above-mentioned problems and provide a multistage synchronous counter that can operate at higher speeds. [Means for Solving the Problems] The synchronous counter of the present invention includes a first-stage flip-flop that inputs a signal at a predetermined level to its input terminal and performs a binary counting operation according to clock pulses, and A second stage flip-flop receives the input output data of the first stage flip-flop and inverts the level of the output data according to the level of the input data, and performs a binary counting operation in accordance with the clock pulse. a third stage binary counter flip-flop;
A third-stage AND gate performs a logical product of the output data of the binary counter flip-flop and the output data of the second-stage flip-flop, and a third-stage AND gate receives the output data of the AND gate in accordance with the clock pulse. a third-stage flip-flop that inverts the level of output data according to the level of the data; and an n-th stage (n is an integer of 4 or more, the same applies hereinafter) binary counter that performs a binary counting operation according to the clock pulse. the logical AND data of the (n-1)th stage, which is the logical product of the output data of the flip-flops for the second stage to the (n-2)th stage, and the flip-flops of the (n-1)th stage. a first AND gate in the n-th stage that performs a logical product with the output data of the n-th stage and outputs the logical product data as the n-th stage logical product data, and a flip-flop for the binary counter in the n-th stage and a second AND gate in the n-th stage that performs logical product with the output data of the n-th stage;
It has an n-th stage of seven flip-flops which takes in the output data of the AND gate and inverts the level of the output data according to the level of the taken data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment shows a four-stage synchronous counter, in which the power supply voltage VCC is input to the input terminals J and K terminals, and the clock pulse C
The first stage JK flip-flop 11 performs a binary counting operation according to K, and the first stage JK flip-flop 11 inputs to the J terminal and K terminal of the input terminal when the clock pulse CK becomes high level.
a second-stage JK flip-flop 12 that takes in the output data ○UTI of the K flip-flop 11 and inverts the level of the output data OUT2 according to the level of the taken-in data when the clock pulse CK becomes a low level; Input power supply voltage VCC to J terminal and K terminal and clock pulse CK
A JK flip-flop 15 for the third binary counter performs a binary counting operation according to the output data of the JK flip-flop 15 for the binary counter and the JK flip-flop 15 for the second stage.
A third-stage two-man power AND gate 21 that performs logical product with the output data OUT2 of the flip-flop 12, and a two-man power AND gate 21 when the clock pulse CK becomes high level.
The third stage JK flip-flop 13 takes in the output data of the clock pulse CK and inverts the level of the output data OUT3 according to the level of the taken data when the clock pulse CK becomes low level, and the power supply voltage is applied to the J terminal and the K terminal. The nth stage inputs VCC and performs binary counting operation according to the clock pulse CK (n is an integer greater than or equal to 4; however, in this embodiment, n is 4).
Only. The same applies hereafter) and the JK flip-flop 16 for the binary counter, and from the second stage to the (n2)th stage (n=
4, so it is only the second stage).
-1) The first two-man-powered AND gate 22 of the nth stage which performs the logical product of the logical product data of the stage and the output data of the (n-1)th stage flip-flop and outputs it as the logical product data of the nth stage. and a second two-man-powered AND gate 23 in the n-th stage, which takes the logical product of this n-th stage logical product data and the output data of the JK flip-flop 16 for the n-th stage binary counter;
When the clock pulse CK becomes a high level, the output data of the second two-manufactured AND gate 23 is taken in. When the clock pulse CK becomes a low level, the level of the output data OUTn is inverted according to the level of the taken data. The configuration includes n-stage JK flip-flops 14.

In order to configure a synchronous counter with five or more stages, the circuit blocks shown in FIG. 2 may be successively connected to the fourth subsequent stage of the embodiment shown in FIG.

The third stage in FIG. 1 is a special case of the circuit block in FIG. 2, and the fourth stage is substantially the same as the circuit block in FIG. 2, so the circuit block in FIG. 2 will be described. In addition, the JK flip-flop used below is a master-slave type, and input data is read at the rising edge when the clock pulse CK goes high, and the output data level changes at the falling edge when the clock pulse CK goes low. I will explain it as a thing.

This circuit block is a JK flip-flop 14.16
and a two-man AND gate, 22.23. Since the high-level power supply voltage VCC is connected to the J and K terminals of the JK flip-flop 16, the output is inverted at the falling edge of the clock pulse CK and operates as a binary counter, and its output is connected to a two-man AND gate. It is connected to one input end of 23. Also, the output data OUT from the second stage to the (n-2)th stage
The logical product of 2 to OUT (n-2) is the logical product data of the (n-1)th stage AND OUT (n-1).
It is connected to one input terminal of the ND gate 22, and
) stage output data OUT(n-1) is connected to the other input terminal.

Also, the output of this two-man power AND gate 22 is a two-man power AND
It is connected to the other input terminal of the gate 23 and output data OUT2 to OUT from the second stage to the (n-1)th stage.
It is output to the next stage as the logical product of T (n-1), that is, the logical product data AND OUTn of the nth stage. Furthermore, a clock pulse CK is connected to the CLK terminals of the JK flip-flops 14 and 16.

The operation of this circuit block will be explained using the time charts shown in FIGS. 3(a) and 3(b).

Here, FIG. 3(a) shows that when the logical product data AND OUT(n-1) of the (n-1)th stage is input almost simultaneously with the falling edge of the clock pulse CK,
) indicates the case where the clock pulse arrives a little later than one clock cycle from the falling edge of the clock pulse CK. Furthermore, since this logical product data ANDOUT(n-1) is the logical product of the outputs from the second stage to the (n-2)th stage of the synchronous counter, the logical value is constant for at least two clock cycles. ．． In FIG. 3 (a>, the logical product data AND OUT(n
-1) and the output data OUT (n-1) go high, and the output of the JK flip-flop 16 also goes high, at the falling edge of the clock pulse CK, the output (OUTn) of the JK flip-flop 14 goes high. Invert.

Since the JK flip-flop 16 operates in the same way as the JK flip-flop 11 at the front stage of this synchronous counter, the above operation corresponds to a carry occurring at the next clock when all the output data up to the previous stage becomes high level. However, it can be seen that it is operating normally as a synchronous counter.

Furthermore, as shown in FIG. 3(b), even if the logical product data AND OUT (n-1) changes one clock period after the falling edge of the clock pulse CK that should change due to the influence of the previous stage, the JK flip-flop 14 will not change. The rising edge of the clock pulse CK that reads input data, that is, 1
．． JK as long as it is determined by a delay of 5 clock cycles.
The output of the flip-flop 14 can be inverted and can operate normally as a synchronous force counter.

Next, considering the delay caused by the AND gates 21 to 23 of the data in the embodiment shown in FIG.
The maximum transmission delay time of the D gate is (N-2) tpd, which is the same as the second conventional example, but since a delay of 1.5 clock cycles is allowed, the 3 @ clock of the second conventional example frequency.

Further, the number of fan outs in each stage is only two two-man-powered AND gates, so there is no increase in fan out due to an increase in the number of stages as in the first conventional example, and high-speed operation is possible.

Although the embodiments of the present invention have been described above, the flip-flop used in this synchronous counter is not limited to JK flip-flops, and the present invention can be applied as long as the output is inverted by a carry signal from the previous stage. A similar effect can be obtained. Further, if the AND gate is also logically equivalent, it is also possible to take a circuit ellipse using other OR gates, NAND gates, NOR gates, etc.

[Effects of the Invention] As explained above, the present invention provides circuit blocks for each stage after the third stage, including a flip-flop for a binary counter that performs binary counting operation based on clock pulses, and outputs from the second stage to the previous stage. The configuration includes a flip-flop that receives the AND of the data and the output data of the binary counter flip-flop and inverts the output data according to the level of this input data using a clock pulse. There is no increase in the delay time of the carry signal, and since the operating margin for the delay time of the carry signal can be approximately three times that of the conventional method, there is an effect that the clock frequency can be increased and the speed can be increased.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3(a) and (b) are circuit diagrams of the circuit blocks of each stage when the embodiment shown in the figure is further multistaged. 4 and 5 are circuit diagrams showing first and second examples of conventional synchronous counters, respectively. 11-16...JK flip-flop, 21-23.
・2-person AND gate, 31...3-person AND gate 9

Claims (1)

[Claims] A first stage flip-flop inputs a signal of a predetermined level to its input terminal and performs a binary counting operation according to a clock pulse, and the output data of the first stage flip-flop is inputted to its input terminal according to the clock pulse. a second-stage flip-flop that inverts the level of output data according to the level of captured data; a third-stage binary counter flip-flop that performs a binary counting operation according to the clock pulse; and this binary counter. a third-stage AND gate that takes the logical product of the output data of the second-stage flip-flop and the output data of the second-stage flip-flop; and a third-stage AND gate that takes in the output data of the AND gate in accordance with the clock pulse; a third-stage flip-flop that inverts the level of output data according to the clock pulse, and an n-th stage (n is an integer of 4 or more, the same applies hereinafter) binary counter flip-flop that performs a binary counting operation according to the clock pulse. , from the second stage to the (n-th
2) Take the logical product of the logical product data of the (n-1)th stage, which is the logical product of the output data of the flip-flops up to the stage, and the output data of the (n-1)th stage flip-flop, and calculate the logical product of the nth stage. a first AND gate in the nth stage that outputs the logical product data; and an a second AND gate; and an n-th stage flip-flop that takes in the output data of the n-th stage second AND gate in accordance with the clock pulse and inverts the level of the output data according to the level of the taken-in data. A synchronous counter comprising: