JPS6130122A - Parallel-serial converting circuit - Google Patents

Abstract

PURPOSE:To relax conditions of the high-speed operation and to output a serial signal having a high repeat frequency by providing serial registers to which the same serial signal, the same load signal, and odd and even parallel signal are inputted and syntherizing outputs of them. CONSTITUTION:The same shift signal SM and the same load signal SL are inputted to shift registers 2 and 3, and even signals P2-P8 of parallel signals A and B are inputted to the register 2, and odd signals P1-P7 of signals A and B are inputted to the register 3. Outputs taken into registers 2 and 3 in order are applied to one inputs of AND gates 5 and 6 of a selecting ciruit 8, and the signal SM is applied to the other input of the gate 5, and the signal to which the signal SM is inverted by an inverter 4 is applied to the other input of the gate 6. Outputs of gates 5 and 6 are synthesized by an OR gate 7 to output a serial signal SSE, thus relaxing conditions of the high-speed operation to output the serial signal SSE having a high repeat frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a scanning signal generation circuit for a display signal source, and more particularly to a parallel-to-serial conversion circuit suitable for generating a scanning signal at high speed.

[Background of the invention]

FIG. 1 is a diagram showing a conventional parallel-to-serial conversion circuit. The shift register 1 receives parallel signals P,
N? , @ Input shift signal Ss□ and load signal SL. When the load signal SL becomes a no-y level, the shift register 1 takes in the parallel signal to in synchronization with the rising edge of the shift signal SSX. Then load signal S
When L becomes low level, the shift register 1 converts the parallel signal A ""'7'a taken in in synchronization with the rising edge of the shift signal SSX from 8 to the serial signal SSX.
Output as . FIG. 2 is a timing chart of FIG. 1. (α) is the shift signal Ssx*(1) l is the load signal St, (C1 indicates the timing of the serial signal SSX. The load signal SL is shifted) Once every 8 cycles of the Ssx signal, one cycle of the shift signal ( The shift signal SSX is at a high level during the period (from the falling edge to the falling edge of the shift signal SSX) and is at a low level during the other periods. When the load signal SL is at a high level, at the rising edge of the shift signal Ssx, the parallel signals P, . When the I2-code signal SL is at low level, the rising edge of the shift signal six turns 1.
The signals are shifted one by one and the serial signal S1j is output. Since the shift register operates at the rising edge of the shift signal, the level of the serial signal six is one step during one station period (from rising edge to rising edge) of the shift signal.

Therefore, if this conventional circuit is used, the serial signal SSX
The highest repetition frequency of is half of the repetition frequency of shift signal six. In other words, the upper limit of the repetition frequency of the shift signal SSX at which the shift register can operate is the fix.
This method has the disadvantage that a serial signal six having a repetition frequency higher than jxx cannot be obtained.

[Purpose of the invention]

An object of the present invention is to provide a barrel-to-barrel serial conversion circuit in which the highest repetition frequency of an output serial signal is equal to the repetition frequency of a shift signal input to an internal shift register.

[Summary of the invention]

The level of the serial signal output from a parallel-to-serial conversion circuit using a conventional shift register does not fluctuate during one shift signal period.

On the other hand, the shift signal has one high level period and one a-level period within its one cycle period.

Therefore, two shift registers are provided, and the parallel signals are distributed to the two shift registers alternately in the order in which they are desired to be converted into serial signals.The output of each register is selected between the high level period and the Ω-level period of the shift signal, and the serial signal is By outputting as
RIii! The I repetition frequency was made equal to the repetition frequency of the shift signal.

[Embodiments of the invention]

Fig. 5 shows an embodiment of the present invention, and Fig. 4 shows its timing chart. In Figure 6, the same shift signal Six and the same load signal SL are input to the shift register 2.5. The shift register 5 receives a parallel signal P1.
Odd parallel signal P8. ^, Hey, 7)? is input, and the shift register 2 receives a parallel signal P.
□Even parallel signal Pg * P4 * 7'
s*8 is input. Shift register 20 output B
is the input of the ANI gate 5 along with shift No. 41 SSX, and the output A of the shift register 3 is the input of the inverter f
It becomes the input of ANI) gate 6 together with the output of i':r'-)4. Inverter gate 4 has shift signal SS
X is input. AND gate 5゜AND gate 6
Both outputs are input to an OR gate 70, from which a serial signal SSX is taken out. Here, inverter gate 4゜AND goo) 5. A) ID game)
6. A portion constituted by the OR gate 7 is referred to as a selection circuit 8. The raw salt will be explained below with reference to Figures 3 and 4. The same shift signal SSM is input to shift registers 2 and 5. Also, shift registers 2 and 5 #'CG! Iil-
? Input a Meade SL. This load signal SL is set to 1 of the shift signal SSX every 4 cycles of the shift signal 5sir.
This is a signal that is at a high level during the period (from the falling edge to the falling edge) and is at a low level during the rest of the cycle. When the shift No. 6 SSI changes from low level to high level while the load signal SL is at high level, the odd parallel signal 4jP is sent to the shift register 5 in synchronization with its rising edge.
1. p.

A * PI is taken into the shift register 2, and even parallel signals Pt * A s 7'am8 are taken in, respectively. Thereafter, when the load signal SL becomes low level, in synchronization with the rising edge of the shift signal 5111, the shift register 3 faces, 8', ^, and P, and the shift register 2
outputs signals in the order of 8m A - P4 - h. Let the output of shift register 2 be B, and the output of shift register 3 be A.

ta) in FIG.
The output A of the timer is shown. Here, since the shift registers 2 and 3 operate in synchronization with the rising edge of the direction shift signal Ssx, h and P at each output A and B, ,
The signals to P, A-PR, 8, and 8 are outputted with the same timing. The period during which the signals of outputs A and B are held is one cycle from the rising edge of the shift signal SSX to the next rising edge. Then, the selection circuit 8 divides one cycle period in which the signal is held into two, and selects the output B of the shift register 2 in the first half of the two periods, and the output A of the shift register 3 in the second half. [Output as serial signal SSX until the end of the application. Selection circuit 8
is the inverter gate 4. ANI) Gate 5.6. It is composed of an OR gate 7. Output B of shift register 2 is
It is input to the AND gate 5 together with the shift signal SsI, and is output while the shift signal sag is at a high level. Also, the output A t' of the shift register 5! The shift signal Ssx is inputted to the AND gate 6 together with a signal whose phase is shifted by 180 degrees through the inverter gate 4, and the shift signal Ssx is input to the AND gate 6.
is output during the low level period. The outputs of AND gates 5 and 6 are combined by OR gate 7 and serial signal S
Output as SX. The timing of the serial signal 5sir is shown in FIG. 4 tg+rc. As is clear from the above, the level of the serial signal SSX changes using the half period of the shift signal 531 as the minimum unit. In other words, shift signal six
The repetition frequency of the serial signal six is equal to the maximum repetition frequency of the serial signal six.

According to the circuit shown in Figure 3, the serial signal can be outputted up to the maximum repetition frequency fll with respect to the upper limit fsz of the repetition frequency of the shift signal at which the shift register can operate.

#! Figure 5 is an improved timing chart of the timing chart shown in Figure 4 to ensure more reliable timing of each signal amount, and Figure 6 is an example of a circuit for realizing the timing of m5 factors. . The difference in structure between the circuit in Figure 3 and the circuit in Figure 6 is that in Figure 6, the shift signal SIK is not directly input to the shift register 5, but is input via the inverter gate 10. Note that the shift signal 511 is not input to the selection circuit 8, but the shift signal six is input via the delay circuit W&9. do clarification. Shift register 2 receives shift signal 4jSxx, and shift register 3#C receives shift signal SJ through inverter gate 10.
A shift signal SsI, which is an inversion of J, is input to each. The load signal SL is input to the shift register 2.about.3 as a signal that rises at the center of the high level period of the shift signal SSZ and falls at the center of the next high level period every four periods of the shift signal SsI. When the a-do signal SL is at a high level, the shift register 3 takes in the ℃ odd parallel signal amount 7°/k -Pa*Pt in synchronization with the rising edge of the shift signal SSZ, and -77) the register 2 takes in the shift signal SSX. synchronized with the rising edge of P6* P4
m Take in Pg. Thereafter, when the load signal Sh becomes low level, the shift register 3 sequentially outputs the odd parallel signals taken in in synchronization with the rising edge of the shift signal SSX, and the shift register 2 outputs the odd parallel signals taken in in synchronization with the rising edge of the shift signal six. Even-numbered parallel signals are output in the order of input. However, since the shift signal 551 and the shift signal SSX are out of phase by 180 degrees, the shift register 20 output B
and the output A of the shift register 5 also has a phase shift signal SSX.
is shifted by an amount corresponding to the phase of 180°. These timings are shown in Figure 5 (al (Al (di (gl
Ruru goes to (j). Next, if the shift signal SSX or shift signal SSX is used to select and output the output B of the shift register 2 and the output A of the shift register 6, the timing for switching each signal will be scattered, so IN: I don't have much room for J-saku. Therefore, a signal whose phase of the shift signal is delayed by 270 degrees by the delay circuit 9 is inputted to the selection circuit 8 as the selection signal Sc. Selection 4R (The high level of it number Sc is during the period #C when the data of the output B of the shift register 2 is ensured, and the +12- level is the high level of the output A of the shift register 6.
Since the data in the selection signal SQ is in a period where the data is sufficient, the output B of the shift register 2 is selected at the high level of the selection signal SQ, and the output A of the shift register 5 is selected at the CL- level, and the serial signal SIX is selected.
As a result, there is room for movement.

Figure 7 shows a kite in which N shift registers are used by expanding the principle of the present invention.

The input parallel signals of the shift registers 11 (17 to 11 (N) are 4 each in Figure 7, but in general, they may be m in number. The shift registers 11i1) to 11 (N)
outputs parallel signals taken in all at once in synchronization with the rising edge of the shift signal six.

Since the level of these outputs does not vary during one cycle of the shift signal SKH, the highest repetition frequency is equal to the repetition frequency of the shift signal SXX.

Therefore, one shift of these outputs (one station review of the shift signal 551) is switched to N periods by the AND gate 15 (11 to 15 (#)) and the OR gate 7, and the serial signal SI
If it is output as X, the maximum repetition frequency of the serial signal sag will be doubled after the shift signal SSX. Therefore, in order to obtain the necessary high-speed serial signal SSX, the shift register 1
1(1) to 11(N)ci The conditions for high-speed operation required are relaxed. however.

This is because it is not possible to select the output of the shift register using a signal obtained by modifying the shift signal six or shifting the phase as in the circuits shown in Figures 3 and 6.

A new decoder circuit 12 is provided, and a high-speed (equivalent to serial signal SSX) decode signal is used as a selection signal for each AN.
It is necessary to supply to D gates 1 (1) to 15 (N).

〔Effect of the invention〕

According to the present invention, since the maximum repetition frequency of the serial signal is equal to the repetition frequency of the shift signal, if jsx is the upper limit frequency of the shift signal at which the shift register can operate, the maximum repetition frequency of the serial signal is also 181, which is the same. By using a shift register, you can see the effect of being able to output a serial signal with twice the repetition frequency of the conventional one. In addition, the repetition frequency of the shift signal required to obtain a serial signal with a high H4 repetition frequency for reverse I/C purposes is 4, which has the effect of easing the high-speed operation conditions required of the shift register.

[Brief explanation of drawings]

ji! Figure 1 is a clock diagram showing a conventional parallel-to-serial conversion circuit, Figure 2 is a waveform diagram showing a time chart of Figure 1, Figures N and S are times # & Figure 4 of an embodiment of the present invention.
J is the waveform factor showing the timing chart in Figure 3, Figure 5 is the timing chart of the circuit that improved the timing in Figure 4, and Figure 6 is the implementation to realize Figure M5. A circuit diagram illustrating an example, the seventh factor is a circuit diagram illustrating an embodiment of a circuit extending the principles of the present invention. 's2*3s11...Shift register 4.10-...
Inverter 5.6.16...ANI) Gate 7...OR gate 8...Selection circuit 9...Delay circuit 12...Decoder 1 Figure Liu 2 (/I ([ 37th Synro- 4th [i2] 51st (I)su7) i goriy PI Pt PI
Pt P6 Ps /'4 Ps
Pz ftFigure 6

Claims (1)

[Claims] In a parallel-serial conversion circuit that converts a parallel signal into a serial signal using a shift register that inputs a shift signal and a load signal, the shift signal is converted to 1/n.
a shift signal whose frequency is doubled (n is an integer of 2 or more);
A parallel device characterized in that n shift registers each receiving a load signal having the same frequency as the load signal are provided, and the outputs of the respective shift registers are switched at the timing of the input shift signal and output/combined to form a serial signal. -Serial conversion circuit.