JPS58146129A - Parallel-serial conversion circuit - Google Patents

Abstract

PURPOSE:To execute the parallel-series conversion in high speed, by shifting two shift registers alternately and selecting the output of the two shift registers alternately. CONSTITUTION:An even number bit of parallel data (from 0 to 15) is taken as an input in parallel with the 1st shift register 1, an odd number bit is inputted in parallel with the 2nd shift register 2 at the same time, the 1st and 2nd shift registers 1, 2 are shifted alternately with shift clocks (b), (c), outputs (f), (g) of the 1st and 2nd shift registers 1, 2 are selected alternately with a data selector 4 based on the shift clocks (b), (c) of the frequency division circuit 3 to obtain a serial data (h). Thus, the inexpensive parallel-serial conversion circuit with high speed conversion is obtained.

Description

Detailed Description of the Invention The present invention provides a parallel-to-serial conversion circuit, particularly a parallel-to-serial conversion circuit using a 77)-register, in which even-numbered bits and odd-numbered bits of parallel data are connected to respective inputs. a first shift register and a second shift register to
．． Second shift - alternating shifts of the registers and
Part 1. The present invention relates to a parallel-to-serial conversion circuit that can perform parallel-to-serial conversion at high speed by alternately selecting the output of a second shift register.

Conventionally, as a parallel/serial conversion circuit, a circuit as shown in FIG. 1 using a shift register is known. FIG. 1 shows an example of a parallel/serial conversion circuit that converts 16-bit parallel data into serial data. That is, by connecting shift registers 1 and 2 of 8-bit configuration in series, 16-bit parallel data is converted to serial data and output. Generally speaking, the frequency of the shift clock in one shift register is Since there is a limit (for example, the maximum shift clock frequency of TI's 74LS166 is 25 MH), it is not possible to speed up the conversion process any further as shown in FIG. However, in CRT displays, it is necessary to increase the number of Ka dots in order to improve the resolution of displayed images, which requires high-speed processing of parallel/serial conversion of line display image data. Note that if the shift registers 1 and 2 are constructed of high-speed elements, it is possible to obtain a parallel-to-serial conversion circuit capable of high-speed processing, but the high-speed elements generally have a low degree of integration. It has the disadvantage of increasing the number of ICs to be mounted, which makes it expensive.

An object of the present invention is to solve the above problems and provide a parallel-to-serial conversion circuit that is inexpensive and capable of high-speed processing. Therefore, in the parallel-to-serial conversion circuit of the present invention, which converts parallel data to serial data using a shift register, the even-numbered bits of the parallel data are used as parallel inputs. a first shift register; a second shift register that also receives odd-numbered bits as inputs in parallel; a frequency divider circuit that generates a shift clock that alternately shifts the first and second shift registers; and a data selector that alternately selects the output of #E1 and the second shift register based on the shift clock output from the wrinkle division circuit. This will be explained below with reference to the drawings.

Figure aIZ is a block diagram showing one embodiment of the hook configuration of the present invention, and Figure 3 shows the operation of the embodiment shown in Figure 2. Here is a time chart to clarify. Reference numeral 1 in the figure is the first shift register, 2tlJil! 2 shift registers, 3
7 lip @70 for Fi branch, 4 is a data selector, and 4-1 to 4-3 are NAND gates forming the data selector 4.

The operation of the embodiment shown in FIG. 2 will be explained in conjunction with the time chart shown in FIG. Note that the clock pulses b and c given to the clock terminal CK of α#i, 7 lip-flop 3 shown in FIG. The output terminals q and q are applied to the first shift register 10 clock terminal CLK and the second shift register 2 clock terminal CLK (the shift clocks and q are as described below). (also given to data selector 4 to alternately select the outputs of #11 and second shift registers 1 and 2);
d and - are the load signal and the signal 20-, which load parallel data into shift register 1 and second shift register 2 of tHl, f and ! indicates the serial data output from the first shift register 1 and the second shift register 2, and h indicates the serial data output from the data selector 4. A parallel/serial conversion circuit that converts parallel data into serial data. ! *1
Even-numbered bits of the 6-bit parallel data, ie, 0.2. ..., ..., 14 bit data is fF
1 load signal is input to shift register 1 of $111, and also the odd numbered bits, ie 1, 3 .
..., ..., 15 bit data is 1IIF20
The output signal is input to shift register 2 of @2 by the first signal. And the clock terminal CK of flip 70 tube 3
The clock pulse α (shown in FIG. 3) input to the flip 70 tube 3 is frequency-divided, and shift clocks b and C are output from the output terminal Q of the flip 70 tube 3 and from each other. In the first shift register l, the shift clock b causes the above 0.2. . . . , 14-bit parallel data is sequentially shifted and serial data f as shown in FIG. 3 is output from the output terminal QH. Similarly, the second shift register 2 outputs serial data y as shown in FIG. and,
The serial data f and da output from the shift registers 1 and 2 are alternately selected by the data selector 4, and serial data as shown in the third factor is output. In this way, the 16-bit parallel data input to the shift registers 1 and 2 is converted into serial data h synchronized with the clock pulse α. Of course, in the present invention, the frequencies of the shift clocks b and C are changed to the shift clocks b and C used in the present invention.
Therefore, if the frequency of the clock pulse a is set to twice the maximum shift frequency, the fastest parallel
Needless to say, serial conversion can be performed.

That is, the parallel/serial conversion circuit of the present invention can perform conversion processing in half the time compared to the conventional example shown in FIG. As a specific example of the illustrated embodiment in FIG.
, the company's 74S112. for flip-flop 3. Same as data selector 4 (if TI's 74800 is used, for example, set the frequency of the clock pulse α to 35M
H (in this case, serial data of 35MH is obtained), the shift frequency of the 74LS166 used as the shift register and 2 is 17.
5 MHz, which is well within the usable range.Also, looking at the delay time, the above 74LS166.7
If the delay times of 48112 and 74S 00 are maximum 35 F&z, 7rLZ and 5nl according to their respective standards, the total delay time in the embodiment shown in FIG. 2 is full S+35FL#+5tLz+5rLz-28,6
rLt (here, 28.6 I is one clock period in 35 MH2) = 23.4 I, which is also within a usable range.

The embodiment shown in FIG. 2 is an example in which 16-bit parallel data is divided into even and parsimonious bits, shifted alternately, and the results are combined and converted into serial data. However, the present invention is not limited to this,
It goes without saying that other arbitrary multi-bit data can be divided into three or four and converted into parallel/serial in the same way.As explained above, according to the present invention, By configuring nine combinations of low-speed and inexpensive shift registers, high-speed frequency dividing flip-flops, and data selectors,
O that can provide a parallel-to-serial conversion circuit that is inexpensive and capable of high-speed conversion.

[Brief explanation of the drawing]

Fig. 1 is a conventional example of a parallel/serial conversion circuit, Fig. 2 is a block diagram showing the configuration of an embodiment of the present invention, and Fig. M3 is a time chart for explaining the operation of the embodiment shown in Fig. 2. shows. In the figure, 1 represents a first shift register, 2 a second shift register, 3 a 7-lip/70-tub, and 4 a data selector.

Claims (1)

[Claims] In a parallel-to-serial conversion circuit that converts parallel data into serial data using a shift register, a first 77, which uses even-numbered bits of the parallel data as a parallel input;
A shift register of H2 which also receives odd-numbered bits as parallel inputs, a shift register that alternately shifts the above #E1 and the second shift register.
and a data selector that alternately selects the outputs of the first and second shift registers based on the shift clock output from the branch circuit. Parallel/serial conversion circuit.