JPS62202638A - Digital quadruple phase modulator - Google Patents

Abstract

PURPOSE:To easily obtain a desired modulation output frequency by adding data of 2 series being the result of interpolation to a waveform shaping digital filter output by (m-1)-set of data while inverting the polarity at each other interval. CONSTITUTION:Input data I, Q are waveform-shaped to be a form suitable for the transmission for the frequency spectrum of a modulation output of waveform shape filters 2-1, 2-2. The output is interpolated by (m-1)-set of data so as to make the data period to 1/m by interpolation circuits 3-1, 3-2. The interpolated output is thinned out every time slot at the timing different in each I and Q side by data selection circuits 4-1, 4-2 and the polarity is inverted every one data by polarity inverting circuits 5-1, 5-2. The outputs are added by an addition circuit 6 and the result is outputted as a modulation output wave 9 via a DA conversion circuit 7 and a low pass filter 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a four-phase phase modulator, and in particular, the modulation circuit is completely digitalized to achieve high precision and modulation speed.

This invention relates to a digital waveform synthesis type digital four-phase phase modulator that has a large degree of freedom in modulating output frequency.

[Conventional technology]

Conventional 1 One example of a means for digitally shaping a signal equivalent to a signal obtained by ordinary phase modulation means is disclosed in Japanese Patent Laid-Open No. 55-24763.

The above conventional technology uses a table index type filter using ROM as a waveform shaping filter, stores the response characteristics of the filter corresponding to the modulation output frequency, sampling rate, etc. in LOMVC, and outputs the output corresponding to the input signal. ．． Waveforms are synthesized by outputting from the OM and digitally converting it into a modulated waveform.

[Problem that the invention seeks to solve]

The above conventional technology is a method in which the response characteristics of the filter corresponding to the modulation output frequency and sampling rate are stored in the ROM of the table index type digital filter using the ROM used for the waveform shaping filter. When the speed changes or when it is desired to change the modulation output frequency, it is necessary to change the contents of the ROM, and there is a problem that the same circuit cannot be adapted to various transmission speeds.

An object of the present invention is to provide a digital four-phase phase modulator that can easily obtain a desired modulated output frequency.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a sampling period I, Q of an output signal of a waveform shaping digital filter corresponding to two series of input data I, Q of quadrature phase modulation.
In order to make each 17m (m is a positive integer of 2 or more),
A means for interpolating the time interval in the sampling period using m-1 pieces of data is used. Then, the I and Q data after interpolation are thinned out every other I and Q data at different timings.

After this thinning, the polarity of every other data is reversed,
That is, multiply +1 and -1 alternately, and then multiply 1. By adding the Q outputs, the output waveform of the four-phase phase modulation is digitally synthesized. This composite output is L)/A
An analog modulated output is obtained by converting and passing the output through a low-pass filter for harmonic removal.

[Effect]

In the waveform synthesis process described above, the frequency of the modulated output can be selected by arbitrarily setting the value of the interpolation number m. Furthermore, when various values are taken as the period of the waveform shaping digital filter output, the modulated output frequency can be set to a constant value by selecting the value of the interpolation number door corresponding to each period. I can do it.

Furthermore, if the number of samplings of the waveform shaping digital filter for input data I and Q is a constant number yb (n is a positive integer) per cycle of input data, then the clock of the waveform shaping digital filter is adjusted to the cycle of input data I and Q. It is possible to match the corresponding period, and the circuits of the waveform shaping filters can be made the same. And the above interpolation number m
If is selected in accordance with the period of input data, the modulated output frequency can be made constant regardless of the period of input data.

〔Example〕

EMBODIMENT OF THE INVENTION Below, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 shows one embodiment of the present invention, and FIG. 2 shows analog waveforms of the waveforms of various parts of FIG. 1. In FIG. 1, 1-1 and 1-2 are four-phase phase modulation input data I, Q, 2-1 and 2-2 are waveform shaping digital filters, 3-1 and 3-2 are interpolation circuits, and 11
-1 and 71-2 are data selection circuits.

5-1.5-2 is a sign inversion circuit, and 6 is an addition circuit.

7 is an L)/A converter, 8 is a low-pass filter, and 9 is a modulated output signal.

Next, the operation shown in FIG. 1 will be explained. Input data I in Figure 1
, Q are signals with the waveforms shown in FIG. be done. The output of this waveform shaping filter is shown in FIG. 2. FIG. 2 (6) is a diagram in which one cycle of the input data (α) is sampled four times, and is a case where the value of LE is 4. As this waveform shaping filter, it is possible to apply, for example, a table index type digital filter using tOM (as disclosed in Japanese Patent Application Laid-Open No. 53-24763 cited above).

The waveform shaping digital filter output is sent to the interpolation circuit 3-1.
In step 3-2, interpolation is performed using m -1 pieces of data so that the data period is 17 m. The analog waveform of the output of the interpolation circuit is as shown in FIG. 2(c). FIG. 2(C) shows a waveform in the case where the number of complements m=4 as an analog waveform.

The interpolated output is divided into l and Q by data selection circuit 4-1.4-2.
The data on both sides are thinned out every other time slot at different timings, and the sign of the output is inverted every other data in a sign inversion circuit 5-1.5-2. The analog waveform output of the sign inversion circuit is as shown in FIG. 2(d).

The outputs are added together by an adder circuit 6, the output is converted into an analog signal by an L/A converter 7, and harmonic components are removed by a low-pass filter 8.

A modulated output wave 9 is output to the output terminal. The analog waveform of the output of the adder circuit 6 is shown by the solid line in FIG. 2 (gl), and the output waveform of the low-pass filter 8 is the waveform shown by the dotted line in FIG. 2 (g).

FIG. 3 shows an embodiment of the first factor interpolation circuit 3-1.5-2 and the clock generation circuit, in which 11 is an interpolation circuit input signal, 12, 15, 16, 19 are latch circuits, and 14
is a subtraction circuit, 15 is a division circuit, 17 is an addition circuit, 18 is a selector circuit, 20 is an interpolation circuit output signal, 31 is a clock excavator, 55, 32, 34 are frequency division circuits, 35 is synchronized with input data The output of the clock 36 is the output of the clock for the waveform shaping digital filter.

At 2 in FIG. 3, the interpolation circuit input signal 11, that is, the waveform shaping filter output, is temporarily stored in latch circuits 12 and 13. The latch circuit 12 stores data one time slot later than the latch circuit 13.

The subtraction circuit 14 calculates the difference between the data temporarily stored in the latch circuits 12 and 13, that is, the difference between the outputs of digital filters that are temporally adjacent to each other, and divides the result into the division circuit 1.
5 by the number of interpolations m to obtain a difference for each data after interpolation, and this is temporarily stored in the latch circuit 16.

The output of the 9th circuit 16 is sent to the adder circuit 17? and the interpolation circuit output 20 are added together and sent to the selector circuit 18. Immediately after the interpolation circuit input data is stored in the latch circuits 12 and 15, the selector circuit 18 selects and outputs the output of the latch circuit 13. In other words, data from one time slot nine times ago is output. This result is stored in the latch circuit 19 and output as an output signal 20. Next, the selector circuit 18 is switched to the adder 17 side, adds the value stored in the latch circuit 19 and the difference for each interpolation stored in the latch circuit 16, and uses the result to add the value stored in the latch circuit 19 to the latch circuit 19. The stored data is updated and outputted as an output signal 20. Above, this operation is m −1
Repeat times.

At the m-th time, by inputting 77 input data to the latch circuits 12 and i3, it is possible to interpolate the r section of the waveform shaping filter output using data of 771-11 wA.

Note that, although the one or more examples are examples using the simplest linear interpolation, it goes without saying that it is possible to use a more accurate interpolation method.

The clock oscillator 31 in FIG. 3 is an original photo for supplying a lock necessary for each part of the present invention, and is divided into 1A by a divide-by-1 circuit 52 to form a clock having the same period as the data rate after interpolation. It is used as a latch pulse for circuit 19. The output of the frequency dividing circuit 32 is divided into 17 m by the frequency dividing circuit 33,
A clock having the same period as the data before interpolation, that is, the digital filter output, is formed, and the latch circuits 12 and 15
and is used as a pulse for operating the selector circuit 18. Furthermore, the output of the frequency dividing circuit 33 is divided by 1/' in the frequency dividing circuit 34 to form a clock having the same period as the input data 1-1, 1-2 in FIG.
Used in 1.2-2. Input data 1-1.1-2
When the clock is synchronized by an external clock, the clock can be phase-compared with the output 35 of the frequency divider circuit 34 shown in FIG. 3, and the clock excavator 31 can be phase-synchronized using a PLL circuit.

FIG. 4 shows an embodiment of the data selection circuit 4-1.4-2 in FIG. 1, and 41 and 42 are data selection circuit inputs;
4.5, 44 is a flip-flop circuit, a5. a6 is an output circuit. In the above, the quantity expressed in multiple bits is 1
It is representatively represented by a line or one circuit. Also, 47 is an input, N, a clock input synchronized with 42, 48
4 is a frequency dividing circuit with a frequency division ratio of 1/2, and 49 is a phase inverting circuit.

In FIG. 3, input data 41 is input to clock input 47.
is a clock whose frequency is divided to 1A by the frequency divider circuit 48.

The output is temporarily stored in the flip-flop circuit 43.

On the other hand, the input data 42 is temporarily stored in the flip-flop circuit 44 using a clock obtained by inverting the frequency-divided clock by a phase inverting circuit 49. That is, input data 41, 4
2 is once every 2 clocks.

Furthermore, since the inputs 41 and 42 are temporarily stored using clocks that are inverted from each other, it is possible to obtain outputs 45 and 46 that are thinned out by nine time slots at mutually different timings.

FIG. 5 shows another embodiment of the present invention. In FIG. 5, numeral 5 is a sign inversion circuit in which the sign is inverted every two time slots. The rest is the same as in FIG. In the embodiment shown in FIG. 1, after the data is thinned out by the data selection circuit 4-1.4-2, the sign of each data is inverted by the sign inversion circuit 5-1. In the embodiment, data selection circuit 4-1.4-
The difference is that after the two outputs are added, the signs are inverted every two time slots. Everything else is the same as the embodiment shown in FIG. 1, and the characteristics of the waveform-combined modulation circuit output are also exactly the same.

Among four-phase phase modulation, when applying the present invention to offset four-phase phase modulation in which the data switching point is shifted by half a period between input data A and Q, input data E or After shifting Q by half a cycle, the filter may be operated at a sampling rate nine times the input data transmission rate, and I and Q may be output at the same timing. Operations after interpolation can be performed in exactly the same way. However, the value of the above-mentioned l needs to be an even number in order to obtain the waveform shaping filter output at the same timing for I and Q.

〔Effect of the invention〕

According to the present invention, in order to synthesize a four-phase phase modulation waveform after interpolating between one time slot of waveform shaping digital filter output data using a plurality of data, the modulation output frequency and the contents of the waveform shaping digital filter can be changed. You can set the desired frequency by simply changing the number of interpolations.

Further, even if the period of the output of the waveform shaping digital filter varies, the modulated output frequency can be kept constant by selecting an appropriate value for the interpolation number. Furthermore, if the number of samplings of the waveform shaping digital filter for one time slot of input data is kept constant, when the transmission speed of input data changes, if the number of interpolations is also selected to an appropriate value, the output frequency can be kept constant. It is possible to do so.

As an example, the input data transmission rate is 16K each for I and Q.
b-32Kh/z, 48Kb/J'#64K
b/! , 96Kb/z, 128KA Shio-256K
When obtaining b/z four-phase phase modulation, if the number of samplings of the waveform shaping digital filter in one period of input data is 1k16, the number of interpolations is 48, 24, and 16, respectively.
, 12.8 m 6 #3, the modulated output frequency can be set to 5.072 MHz. Furthermore, if each of the above interpolation numbers is doubled, the modulated output frequency can be set to lh 144 MHz.

If one modulator is applied to a wireless line using this function, the number of interpolations must be changed when the condition of one line deteriorates.
It is possible to maintain a certain level of line quality by lowering the transmission speed during tm. In addition, if this modulator is used as a common backup device for the modulators of multiple radio devices with different transmission speeds, when switching to the current device, you can change the interpolation number to match the transmission speed of the current device by pressing the button. It is possible to easily switch between the active machine and the spare machine by matching the transmission speed of the spare machine to that of the active machine, and it is possible to economically prepare the spare machine.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a waveform diagram at main points in the embodiment shown in the figure. FIG. 3 shows an embodiment of the interpolation circuit shown in FIG. 1 and a black-and-white noise generation circuit, and FIG. 4 shows an embodiment of the data selection circuit shown in FIG. 1.
FIG. 5 shows another embodiment of the invention. 2-1.2-2... Waveform shaping digital filter. 3-1.3-2... interpolation circuit, 4-1.4-2-...,
Data selection circuit, 5-1.5-2... code conversion circuit,
6...Adder, 7...Digital-to-analog conversion circuit. 8...Low pass filter.

Claims (1)

[Claims] In a digital four-phase phase modulator having a waveform shaping digital filter corresponding to one and two series of input data I and Q, the sampling period of the waveform shaping digital filter is set to 1/1/1, respectively. m (m is a positive integer of 2 or more), the time interval of the sampling period is interpolated by m-1 pieces of data, and the I and Q data after interpolation by the means are interpolated at different timings from each other. Digital four-phase phase modulation characterized in that a four-phase phase modulated wave of an arbitrary frequency is obtained by providing a means for thinning out every other data and performing digital/analog conversion of the combined output of the thinned out I and Q data. vessel. 2. Claim 1 provides that the output timing of either the I or Q side of the waveform shaping digital filter is delayed by 1/2 of the fundamental period of the input data of the waveform shaping filter. Features: Digital 4-phase phase modulator.