JP3192803B2 - Digital modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator for processing a digital multilevel signal, shaping the waveform, and outputting the resulting signal as an analog modulated signal.

[0002]

2. Description of the Related Art Conventionally, several methods using digital signal processing have been considered in order to obtain a required modulated analog signal. Figure 15 is a conventional digital modulator Baie
FIG. 3 is a configuration diagram illustrating an example of a baseband waveform shaping unit . 1
a, 1b are shift registers, 2 is a clock generation circuit, 3
a and 3b are output signal values, that is, band-limited base bars.
A ROM in which command waveforms are written, 11 is an output selection selector, and 4 is a D / A converter. This circuit is an example used for a π / 4 shift QPSK modulator. Next, this operation will be described. Generally, a π / 4 shift QPSK modulator is
An input data signal is mapped on a phase plane by a signal mapping circuit, and is divided into an in-phase component signal and its quadrature component signal. These component signals are converted into an analog signal, that is, a baseband waveform by the digital modulator of FIG. 15, and the output is taken out as a required modulation output by the quadrature modulation circuit.

In general, when there are many possible combinations of input signal values, such as a π / 4 shift, a large number of memory areas must be used to generate a corresponding baseband waveform signal. No. In the configuration example shown in FIG. 15, in order to greatly reduce this, only one type of digital value is written in the ROM in which the output signal value is written. Then, two shift registers are provided, input signals are separately input, and a value written in the ROM is selected and output. Since the selector alternately switches these ROM outputs and outputs them to the D / A, the storage capacity of the ROM can be reduced.

FIG. 16 is a diagram showing a configuration of another conventional digital modulator. In the conventional example of FIG. 15, digital signal processing up to a baseband signal is performed. In this example, digital signal processing up to an IF (intermediate frequency) signal is realized. That is, it is composed of an interpolation circuit, a selector, and an inversion circuit. In which the I-channel in-phase component signal, Q channels of the quadrature component signal is to utilize the fact that there is orthogonality COS and SIN, reads COS for modulation, the value of SIN amplitude from a common ROM is there.

In the figure, 13 is a selector, 14 is a COS and SIN sample value generation circuit, and 15 is a multiplier as a part related to the patent of the present application. This operation is as follows. The Ich and Qch signals of the input signal pass through a digital filter and are further smoothed by an interpolation circuit. The multiplier 15 multiplies the roll-off output by the Calua sine wave sample. First, the number of sine wave samples is four in one cycle. Sample angles of 0, π / 2, π, 3π
/ 2 degrees, COS and SIN are 1, 0,-
1, 0 and 0, 1, 0, -1. From this, the sample value generation circuit 14 may actually generate 1, -1 and 0. Furthermore, at the above angles, when one of SIN and COS is 1 or -1 and the other is 0, multiplication and simultaneous addition only need to be multiplication. That is, it is only necessary to select COS or SIN. Therefore, here, the sample value generation circuit 14
Need only be generated for +1 and -1. Thus, the selector 13 and the multiplier 15 express digital modulation.

[0006]

The conventional digital modulator is configured as described above, and the COS axis is used even when the carrier sine wave sample value is handled digitally.
Ich baseband signal projected on SIN axis
Π / 4 shift QPSK is applicable only when the modulation scheme in which the Qch baseband signal
However, there is a problem that the method cannot be applied to the case of digital phase modulation in which the waveforms have a correlation as described above .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been developed for Ich (COS) and Qch (SI
It is an object of the present invention to provide a small-scale digital modulator that can realize an IF signal by digital signal processing even if N) is not independent.

[0008] The digital modulator according to the present invention, the thin
Input a signal sequence of vol rate and two consecutive signal values
Sign inversion processing is performed for every other set as one set, and the signal value is set to 2
While distributing to one of the two signal sequences
Signal to which the signal value is distributed for each signal value
By switching the series alternately, 2
Rearranger for generating a distribution of two symbol rate signals
If the digital variable waveform shaping filter each minute arranged signal sequence to process separately waveform shaping respectively, the input signal sequence
An oscillator for generating a predetermined periodic signal for tone processing, pre
Separately for the two output signals of the waveform shaping filter
Multiply the periodic signal, synthesize and add each output signal and modulate
And interleaving means for outputting a signal.

[0009] The digital modulator according to the present invention, the thin
Input a signal sequence of vol rate and output 4 consecutive signal values
Sign inversion is performed for every other set as one set, and the signal value is set to 4
While distributing to one of the three signal sequences.
Zero is inserted into two signal series, and the signal value is separated for each signal value.
The signal sequence to be distributed is switched in order,
Generates a distribution signal sequence with four related symbol rates
And a waveform shaping filter for individually shaping each of the divided signal sequences.
An oscillator for generating a predetermined periodic signal for digital modulation processing, and four output signals of the waveform shaping filter.
Multiply each of the synchronization signals separately and combine each output signal
And Intaripu means for outputting a modulated signal addition to, the
From the output signal of the interleaving means,
An output filter for extracting several components was provided.

[0010]

[Embodiment 1] Conventional digital modulator is Ic
The invention will be described in which h and Qch have been considered for independent signals, but have been extended so that they can be applied to signals that change in relation to Ich and Qch. FIG.
FIG. 2 is a diagram showing a first embodiment of the present invention. In the present embodiment, the digital modulator of the present invention is used for narrow band MSK (GMSK).
Etc.) and π / 2 shift BPSK.
First, the configuration will be described. In the figure, reference numeral 21 denotes an input terminal of an input signal sequence I _n {± 1}, and 22 denotes a rearranger for rearranging input data and outputting the data to a _n , b _n , {± 1, 0} 2ch. It is. Reference _numeral 23 denotes a first waveform shaping filter which inputs an and outputs a baseband signal whose waveform is shaped according to the input sequence. Similarly, 24 inputs b _n and outputs a waveform corresponding to the input sequence. It is a second waveform shaping filter that outputs a shaped baseband signal. Reference numeral 25 denotes a first interpolation circuit for interpolating the output of the waveform shaping filter 23 at a period of 1 / (4N) times the IF frequency (N is an integer), and 26 denotes the output of the waveform shaping filter 4 at 1 / (4N) of the IF frequency. This is a second interpolation circuit that performs interpolation at a double cycle (N is an integer). Reference numeral 27 denotes an interleaver / inverting circuit for selecting and inverting the first and second interpolation circuit outputs in accordance with a control signal of the controller 28 to generate a digital IF modulation signal. Reference numeral 28 denotes an interpolator operation cycle and 1 / (4M of the IF frequency). ) A controller that outputs a control signal of the interleaver / inverting circuit 27 at a double cycle (M is an integer: N ≧ M). 29 is a D / A converter for D / A converting the digital IF modulation signal created by the interleaver / inverting circuit 27; 30 is a low-pass filter for removing harmonic components of the output of the D / A converter 29; Is an output terminal for outputting the output of the low-pass filter 30 to the outside.

First, general characteristics of an input signal will be described. According to the data sequence {I _n }, π / 2 shift BPS
The K-modulated signal waveform can be expressed as follows. If this is expressed in a complex form, it is expressed by equation (1), and in real number form, it is expressed by equation (2).

[0012]

(Equation 1)

Here, g (t) is an impulse response waveform of a transmission baseband signal, Ts is a symbol period, and ω _c is a carrier angular frequency. By transforming equation (2), the following equation (3) is obtained. Now, when the data sequence {I _n } is divided into two sequences {a _n } and {b _n }, the expression is expressed by Expression (4). When this is applied, equation (3) can be rewritten as equation (5).

[0014]

(Equation 2)

Now, the rearranger 22 outputs the data sequence {I
according to _n} (4) wherein the two sub-sequences {a _n},
Rearrange to {b _n }. Next, the two rearranged sub-sequences {a _n } and {b _n } are respectively applied to the waveform shaping filters 2.
Is input to 3,24, (6) a band-limited transmission baseband signal _{a'K} the formula is converted to _{b'K}. Then, the signal waveform represented by the real number is represented by Expression (7).

[0016]

(Equation 3)

In the equation (7), T _f represents an operation cycle of the waveform shaping filter circuit, and k represents an integer. Generally, a value of 2 or more is selected for Ts / _Tf . FIG. 9 shows the structure of the waveform shaping filter 44.
An example is shown. 9, 60 sub-sequence {a _n: ±
An input terminal of the 1,0}, 61 operates at T _s period Schiff
Register 62 is an N-ary operating at Ts / N = _Tf cycle
The counter 63 outputs the output of the shift register 61 and the N-ary power.
The output of the counter 62 is used as an address to store the stored base.
A ROM for outputting a band waveform, 24 is an output terminal
It is. The same applies to other waveform shaping filters 45, 46 and 47.
It can be realized with a simple configuration. Note that this waveform shaping filter
It may be composed of ordinary FIR and IIR. The waveform-shaped signal {a ′ _K } is input to the interpolation circuit 25. The interpolation circuit 25 is a first interpolation circuit that interpolates the output of the waveform shaping filter 23 at a period of 1 / (4M) times the IF frequency (M is an integer). Similarly, reference numeral 26 designates the output of the waveform shaping filter 24 as I
2nd interpolation at 1 / (4M) times cycle of F frequency (M is an integer)
Interpolation circuit. FIG. 2 is an example showing the state of interpolation, in which the output of the waveform shaping filter of oversample 4 is further interpolated to four times the sample. In this case, the IF frequency becomes Ts / 4. Here, the interpolation circuit 28 outputs interpolating _a'K and Ai, likewise, and Bi an output obtained by interpolating the _b'K.

Next, the operation of the controller 28 will be described. From equation (5), it can be seen that the following two carriers are required to represent a π / 2 shifted BPSK signal. Ac (t) = cos (ω c t) Bc (t) = - sin (ω c t) the sample points of the carrier, the angle 0, π / 2, π, 3π / 2
I will take it. FIG. 3 shows a sample value sequence of each carrier. In this case, the sample sequence value of each carrier has a value alternately, and when one carrier is ± 1, the other carrier is always 0. Therefore, the modulation signal can be expressed by the following equations (8) and (9).

[0019] _{sr (kTf) = a'K cos} (ω c kTf) -b' K sin (ω c kTf) (8) sr (iTc) = Aicos (ω c iTc) -Bisin (ω c iTc) (9 Here, Tc is the operation cycle of the interpolation circuit. The following series operating at a period of 1 / (4M) times the carrier frequency is (9)
It is equivalent to the expression

[0020]

(Equation 4)

That is, the digital IF signal can be realized by selecting and outputting Ai and Bi, and inverting it every two sample periods, as represented by equation (10). That is, the controller 28 supplies the interleaver / inverting circuit 27 with (1
A control signal for realizing the operation given by equation (0) is transmitted. More specifically, FIG. 4 shows an example of a control signal given to the interleaver / inverting circuit 27 by the controller 28.

The interleaver / inverting circuit 27 receives the control signal, selects and inverts two interpolating circuit outputs, and outputs the result. FIG. 5 shows an example of the outputs of the interrogation circuits A (t) and B (t) and the output of the interleaver / inverting circuit 27.
Next, the output value of the interleaver / inverting circuit 28 is D / A converted by the D / A converter 29. And the D / A converter 2
The 9 output signals are converted into analog IF modulated signals by removing the higher harmonic components by the low-pass filter 30. At this time, the low-pass filter 30 is set to a band for removing a harmonic component that is four times or more the IF frequency. The above description will be described for each frequency. 6 (a) shows the spectrum of the output of the interleaver / inverting circuit 27, FIG. 6 (b) shows the spectrum of the output of the D / A converter 29, and FIG. 6 (c) shows the spectrum of the output of the low-pass filter 30. Show. In addition, D / A output
Instead of the latter LPF, one of the spectra in FIG.
A selectable BPF may be used.

Embodiment 2 FIG. This embodiment describes an example of a digital modulator applied to a signal side in which both Ich and Qch sequentially change in a specific relationship. As a specific example,
An example in which the present invention is applied to a π / 4 shift QPSK modulator will be described. FIG. 7 is a diagram showing a second embodiment of the present invention. In the figure,
41 is an input terminal of the Ich input sequence I _n {± 1}, 42
The Qch input sequence Q _n input terminals of {∈ ± 1}, 43 are rearranged I, the Q2ch input data, a _n, b _n, c
_n , d _n ｛∈ ± 1, 0｝ 4ch. 44 inputs the a _n, a first waveform shaping filter for outputting the baseband signal waveform shaping in accordance with the input sequence, as well as 45, 46 and 47 respectively b _n, c
_n, enter the d _n, a second output a baseband signal whose waveform is shaped in accordance with the input sequence, third, and fourth waveform shaping filter. 48 is a first interpolation circuit for interpolating the output of the waveform shaping filter 44 at a period of 1 / (8N) times the IF frequency (N is an integer). Similarly, 49, 50, and 51 are waveform shaping filters 45, 46, respectively. The second, third, and fourth interpolation circuits interpolate the output of 47 at a period of 1 / (8N) times (N is an integer) times the IF frequency. An interleaver / inverter 52 selects and inverts the first, second, third, and fourth interpolator outputs in accordance with a control signal of a controller 53 to generate a digital IF modulation signal. (8M) A controller that outputs a control signal of the interleaver / inverting circuit 52 at a multiple cycle (M is an integer: N ≧ M). 54 is a D / A converter for D / A converting the digital IF modulation signal created by the interleaver / inverting circuit 52.
Reference numeral 55 denotes a low-pass filter for removing harmonic components from the output of the D / A converter 54, and reference numeral 56 denotes an output terminal for outputting the output of the low-pass filter 55 to the outside.

By the way, the signal waveform subjected to π / 4 shift QPSK modulation by the data sequence {I _n , Q _n } can be expressed as follows. If this is expressed in complex terms, (11)
Equation (12) in real number expression.

[0025]

(Equation 5)

[0026] Here, g (t) is the impulse response waveform of the transmission baseband signal, Ts is the symbol period, the omega _c is the carrier angular frequency. By transforming equation (2), the following equation (1) is obtained.
3) Equation is obtained. If the data sequence {I _n , Q _n } is _expressed by four sub-sequences {a _n }, {b _n }, {c _n }, {d _n }, the expression (14) is obtained. At this time, Expression (13) can be expressed by Expression (15).

[0027]

(Equation 6)

Now, the rearranger 43 outputs the data sequence {I
_n , Q _n } according to equation (14).
_{n}, {b n},} {c n}, rearranged to {d _n}. FIG. 8 shows an example of rearrangement . Next, rearranged four sub-sequence _{{a n}, {b n} }, {c n}, {d n} are respectively input to the waveform shaping filter 44, 45, 46, 47, (16) band-limited transmission baseband signal representation _{{a'k}, {b'k} }, {c'k}, {d'k}
Is converted to Therefore, the signal waveform is represented by equation (17).

[0029]

(Equation 7)

Here, _Tf represents the operation cycle of the waveform shaping filter circuit, and k represents an integer. Generally, a value of 2 or more is selected for Ts / _Tf . Next, the waveform-shaped signal {a ′ _k }
Is input to the interpolation circuit 48. The interpolation circuit 48 is a first interpolation circuit that interpolates the output of the waveform shaping filter 44 at a period of 1 / (8M) times the IF frequency (M is an integer). Similarly, 49, 50, and 51 are waveform shaping filters 4 respectively.
5, 46, and 47 outputs are output at 1 / (8M) times cycle (M
Is an integer), and is a second, third, and fourth interpolation circuit. FIG. 4 is an example showing the state of interpolation, in which the output of the waveform shaping filter of oversample 4 is further interpolated to 8 times the sample. In this case, the IF frequency becomes Ts / 4. Here, the output of the interpolation circuit 8 which interpolated a ′ _k is Ai,
Similarly, _{b'k, c'k,} the outputs obtained by interpolating the _d'k Bi, Ci, and Di.

Next, the operation of the controller 53 will be described. From equation (15), it can be seen that four carrier waves of equation (18) below are required to represent a π / 4 shifted QPSK signal. Ac (t) = cos (ω c t) Bc (t) = - sin (ω c t) Cc (t) = cos (ω c t + π / 4) Dc (t) = - sin (ω c t + π / 4) (18) FIG. 11 shows a sample value sequence of each carrier. In this case, as in the first embodiment, first, sampling is performed at four points of one cycle of the carrier wave. For example, FIG. 11A shows a sample value sequence of Ac (t). The portion of FIG. 11A is a case where four samples are repeated in one period (1, 0, -1, 0 repetition).
The portion of the figure shows the case where 0 is inserted between each sample.
As a result, the sample value sequence of Ac (t) has 8 samples per period (0, 0, 0, 0, -1, 0, 0,
0 repetition). Similarly, FIG.
As shown in (c) and (d), Bc (t), Cc
(T) and Dc (t) can also be represented by a sample value sequence of 8 samples in one cycle with 0 inserted.

Here, referring to FIGS. 11 (a) to 11 (d),
The sample value sequence of each carrier has a value alternately, and when one carrier is ± 1, the other three carriers are always 0. Therefore, the modulated signal is expressed by the following equation (19):
0). sr (kTf) = a ′ _k cos (ω _c kTf) −b ′ _k sin (ω _c kTf) + c ′ _k cos (ω _c kTf + π / 4) −d ′ _k sin (ω _c kTf + π / 4) (19) sr (iTc) = Aicos (ω c iTc) -Bisin (ω c iTc) + Cicos (ω c iTc + π / 4) -Disin (ω c iTc + π / 4) (20) where Tc is the operation period of the interpolation circuit. The following series operating at a period of 1 / (8M) times the carrier frequency is (20)
It is equivalent to the expression

[0033]

(Equation 8)

That is, the digital IF signal is represented by (21)
Di, Bi, Ci, Ai are selected and output as in the equation,
This can be realized by inverting every four samples. That is,
The controller 53 supplies the interleaver / inverting circuit 52 with (2
A control signal for realizing the operation given by the expression (1) is transmitted. FIG. 12 shows an example of a control signal provided by the controller 13 to the interleaver / inverting circuit 52. The interleaver / inverting circuit 52 receives the control signal, selects and inverts the outputs of the four interpolating circuits, and outputs them. FIG. 13 shows an example of the outputs A (t), B (t), C (t), D (t) of the interpolator and the outputs of the interleaver / inverter 52.
Next, the output value of the interleaver / inverting circuit 52 is D / A converted by the D / A converter 54. Then, the D / A converter 54
The output signal is filtered by the low-pass filter 55 to remove harmonic components, and becomes an analog IF modulation signal. At this time, the low-pass filter 55 is set to a band for removing harmonic components that are four times or more the IF frequency. FIG. 14 illustrates the above relationship for the frequency band. That is, FIG.
14 shows the spectrum of the output of the interleaver / inverting circuit 52, FIG. 14B shows the spectrum of the output of the D / A converter 54, and FIG. 14C shows the spectrum of the output of the low-pass filter 55. Note that, instead of the LPF after D / A output, FIG.
(B) BPF that can select one of the spectra in
May be used.

[0035]

According to the above manner the present invention, according to the present invention, in the digital modulator, re that generates first and second output signal columns of memory Toko for storing a predetermined signal string corresponding to the input signal train Since an arrayer, each waveform shaping filter, a digital modulation oscillator, and interleaver means for multiplying and adding them are provided, a digital modulator in which input signals mainly in the differential system are not independent of Ich and Qch is reduced. There are effects that can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital modulator according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating interpolation of the modulator according to the first embodiment.

FIG. 3 is a diagram illustrating a sampling timing of a carrier in the first embodiment.

FIG. 4 is a diagram illustrating control signals of a controller according to the first embodiment.

FIG. 5 is a diagram illustrating each output signal of the configuration of the first embodiment.

FIG. 6 is a diagram illustrating a frequency spectrum of each output in the configuration of the first embodiment.

FIG. 7 is a configuration diagram of a digital modulator according to another embodiment of the present invention.

FIG. 8 is a diagram illustrating an operation of the rearranger according to the second embodiment and illustrating output signals.

FIG. 9 is a configuration diagram of a waveform shaping filter according to a second embodiment.

FIG. 10 is a diagram illustrating interpolation of the digital modulator according to the second embodiment.

FIG. 11 is a diagram illustrating a sampling timing of a carrier wave according to the second embodiment.

FIG. 12 is a diagram illustrating a control operation of a controller according to the second embodiment.

FIG. 13 is a diagram illustrating each output signal of the configuration of the second embodiment.

FIG. 14 is a diagram illustrating a frequency spectrum of each output in the configuration of the second embodiment.

FIG. 15 is a configuration diagram illustrating an example of a conventional digital modulator.

FIG. 16 is a configuration diagram showing an example of another conventional digital modulator.

[Explanation of symbols]

 22, 43 rearranger 23, 24 waveform shaping filter 25, 26 interpolator 27, 52 interleaver / inverter 28, 53 controller 29, 54 D / A converter 30, 55 low-pass filter 44, 45, 46, 47 Waveform shaping filter 48, 49, 50, 51 Interpolator

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (2)

(57) [Claims] 1. A signal sequence having a symbol rate is inputted, and
Sign inversion processing for every other set of two signal values
And when the signal value is distributed to one of two signal sequences,
And zeros are inserted into the other signal series, and the signal value is
Alternately switch the signal sequence to be distributed
A distribution signal sequence of two symbol rates having a phase relationship is
A rearranger for generating, a waveform shaping filter for separately performing waveform shaping processing on each of the arranged signal sequences, and a predetermined circuit for digital modulation processing of the input signal sequence.
Oscillator for generating the initial signal, and two output signals of the waveform shaping filter, respectively.
Is multiplied by the periodic signal, and the output signals are combined and added to change.
Interleaving means for outputting a tuning signal.
Digital modulator according to symptoms. 2. A signal sequence having a symbol rate is inputted, and
Sign inversion processing every other set as a set of four signal values
And, when distributing the signal value to one of four signal sequences
At the same time, zeros are inserted into the other three signal sequences, and each signal value is
The signal sequence to which the signal value is distributed is switched in order for each
Distribution of four symbol rates with a predetermined phase relationship
A rearranger for generating a signal sequence; a waveform shaping filter for separately performing a waveform shaping process on each of the divided signal sequences; and a predetermined circuit for digital modulation processing of the input signal sequence.
Oscillator for generating a period signal, and four output signals of the waveform shaping filter, respectively.
Is multiplied by the synchronizing signal, and the output signals are combined and added to change.
And Intaripu means for outputting a tone signal, the desired modulation signal from the output signal of the Intaripu means
Features an output filter that extracts frequency components
Digital modulator to.