JPS63261912A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to make the interpolation highly accurate by using a time changing coefficient noncyclic filter and using a phase locked loop so as to convert the sampling frequency. CONSTITUTION:The input sampling signal having a frequency fS1 is inputted to a phase comparator 1, where it is subject to phase comparison with an output being the result of 1/M frequency division of the oscillating frequency of a VCO 2 by a frequency divider 4 and the output is inputted to the VCO 2. Thus, the center frequency fC of the VCO 2 is locked to the least common multiple of the frequency fS1 and the output sampling frequency fS2. The output of the VCO 2 is subject to 1/N frequency division by a frequency divider 3 and the frequency becomes the frequency fS2 to apply phase locking of the input/output sampling frequencies. Then the count of the frequency divider 4 is latched and the frequency fS2 is used as the latching clock to read out a time changing coefficient. On the other hand, the input data f<(n>T<)> is inputted to memories 9-12 via delay elements 6-8 to write the product of the time changing coefficient. The result is summed by adders 13-15 and the result is outputted. Thus, high- order interpolation is applied while using digital signals and highly accurate processing is attained and the circuit constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interpolation device, and particularly to an interpolation device suitable for sampling frequency conversion of a digital image signal.

[Conventional technology]

The image signal has a wide spectrum ranging from direct current to several MHz, and the sampling frequency when digitized is about 10-odd MHz. When exchanging signals between devices with different sampling frequencies, it is necessary to convert the sampling frequency, but conventional methods include converting it to an analog signal, holding the data, and reading it out at a different sampling frequency. It was used. Further, as a method of performing digital linear interpolation, a digital interpolation method described in Japanese Patent Laid-Open No. 166333/1984 is known.

[Problem that the invention seeks to solve]

When applied to an image signal, the above-mentioned conventional technique has a drawback that the sampling frequency is high and the five-circuit operating frequency becomes high and complicated, but the approximation accuracy of interpolation is low and errors are large. Also A/D.

Even with the method of converting the sampling frequency by converting it to analog using a D/A, there were many problems in that although the number of parts increased, noise was likely to be mixed in.

An object of the present invention is to provide an interpolation device that performs high-order interpolation in digital form to avoid noise from analog circuits, suppresses the low precision caused by low-order interpolation, and has a simple circuit configuration. It is in. Another object of the present invention is to convert the sampling frequency using a phase-locked loop, thereby simplifying the circuit configuration for providing the interpolation time of the interpolator.

Still another object of the present invention is to perform high-order interpolation digitally in a device that doubles the sampling frequency, thereby suppressing the low precision caused by low-order interpolation, and simplifying the circuit configuration of the sampling frequency. The purpose of the present invention is to provide a conversion device.

[Means for solving problems]

The above object is achieved by using an interpolation method using a time-varying coefficient acyclic filter and by combining this with a phase-locked loop. Interpolation using a time-varying coefficient acyclic filter is detailed in Japanese Patent Application No. 15633/1982, but will be briefly explained.

Sample value f(iT) of signal f(t), where i=0
~n, T: The formula for approximating the value at any time t using the sampling period is g(t) = ao(t)・f(OT)+a t(t)
・ f CT)+...=+an-z(t)f((
n-1)T)+arl(t)f(nT)・・・・・・(
1) is given by. Equation (1) is in the form of a difference equation representing the operation of an acyclic filter with f (i T) as an input and ai(t) as a coefficient. However, the coefficient is a function of the time t of the output data, so it can be seen that the interpolation according to equation (1) can be performed by an acyclic filter with time-varying coefficients. FIG. 2 shows the configuration of a time-varying coefficient acyclic filter. The input signal f (n T) is the delay element 20
1, 202, -2 On causes a delay of 1 sampling period of the human input signal.

n+1 data f (0), f (T), ・=
f (n T) and the coefficient multipliers 211, 212 .・
...21n will be powered by humans.

Coefficient a i determined by the time t of the output data using the coefficient multiplier
(t) is multiplied by the input data f (i T), and the adders 221, 222 . . . . is input to 22n, integrated, and output as g (t) in equation (1). Coefficient a i
(t) is a function only of time t of output data.

This is achieved by storing it in a ROM or the like and reading it out using t as an address. Figure 3 shows the concept of interpolation. The interpolated value g (t) is calculated using n+1 input data f (OT), f
(T), ・= f (n T), the function g(
t) is calculated as the value at time t. Although t is a value unrelated to the period T of the input data, it is necessary to clearly relate the output time and the input time of the input data. In devices that convert sampling frequencies, it is common to associate the input sampling frequency with the output sampling frequency by some means.6 This is usually done using a phase-locked loop (PLL). The present invention provides a method for obtaining the above interpolated time t using a PLL.

[Effect]

When the input/output sampling frequency becomes a ratio of rational numbers such as WMm, a PLL using a frequency divider is used to synchronize the two frequencies.1 If the frequency ratio is not a simple rational ratio, then another method is used. An oscillator is used. The above relationship is shown in FIG. (In the figure, 1 is a phase comparator, 2 is a voltage controlled oscillator (VCO), and 3.4 is a frequency divider with frequency division ratios N and M, respectively.

In 4a), the oscillation frequency fc of the VCO is fsx fsx since there is a relationship between the input frequency fSsr fSz and fc =Nfsx, =Mfs1. In figure 4'(b), 41 is a low pass filter (LPF), 42 is a mixer, and 4
3 is a fixed frequency oscillator with frequency fo. 4rb), even if the wave number ratio is not a simple value, f
fsx can be synthesized from sx.

Now, the present invention provides a PL that synchronizes the input and output sampling frequencies in the interpolation time setting of the interpolation device used for sampling frequency conversion.
The configuration is simplified by using a frequency divider included in L.

〔Example〕

Embodiments of the present invention will be described below with reference to FIG.

In FIG. 1, 1 is a phase comparator, 2 is a voltage controlled oscillator (VCO), 3 and 4 are frequency dividers with frequency division ratios of N and M, respectively, 5 is a latch, 6 to 8 are delay elements, and 9 -12 are memories, and 13-15 are adders. FIG. 1 shows an example in which the interpolation method is applied to a device that converts the sampling frequency from fsx to fsz by using a fourth-order approximation formula. Input type conversion signal ([
The wave number fst) is input to the phase comparator 1, the phase is compared with the output of the frequency divider 4, and the output is input to the VCO 2. The center oscillation frequency of vCO is fc, which is the least common multiple of fsl and output sampling frequency fsz. That is, fc=N
f sz=M f sz (M, N are mutually prime integers), the VCO output is frequency-divided by M in the frequency divider 4 to become fsl, which is phase-compared with the input in the phase comparator 1, and frequency synchronization is performed. The output of the VCO 2 is also input to the frequency divider 3 and divided by N to become fsz. In this way, the input and output sampling frequencies are synchronized. Here, since the frequency divider 4 is a counter that counts fc by M, the count value takes a value from 0 to M-1 in the period T of fsl.

It can be seen that when the count value is latched by the latch 5, it becomes a value τ obtained by measuring the time of the latch clock with the period T of fsr. Therefore, it can be seen that if fsz is used as the latching clock, that is, the value of interpolation time τ can be obtained for each fsz. Therefore, interpolation can be performed by reading out the time-varying coefficient ai(τ) using the value of the latch 5 as the interpolation time τ and multiplying it by the input data fi. Input data f(nT) is input to delay element 6
Input data 1o=fs is input to a delay device consisting of ~8
get. The input data fo=fs is input to the memories 9 to 12, respectively, together with the interpolation time τ. The product ai(τ)fi of data fi and coefficient ai(τ) is written in memories 9-12. That is, multiplication is performed in memory. The product results are added by adders 13 to 15, and interpolated data g(τ
) is output as As mentioned above, in this example,
Since the input and output sampling frequencies are synchronized, there is no fluctuation in interpolation time and highly accurate interpolation can be performed. Furthermore, since memory is used in the coefficient multiplier, high-order interpolation can be achieved even with high-speed data such as image signals.

FIG. 6 is a diagram showing the configuration of another embodiment of the present invention. In the figure, 6 to 8 are delay elements having a delay time equal to the input sampling period T, 9 to 12 are interpolation coefficient multipliers, and 13 to 15
is an adder, and 51 is a switch. In Figure 5, the interpolated value g(t) is obtained using the fourth-order interpolation formula, and the sampling frequency is set to 1/T.
FIG. 6 shows an operational waveform diagram of an embodiment of a sampling frequency conversion device that doubles the frequency from 2/T to 2/T. Input data f(n
T) is input to the delay elements 6 to 8 every period T, resulting in a data series 1o=f3. The coefficients are multiplied by coefficients by coefficient multipliers 9 to 12, respectively, and added by adders 13 to 15 to obtain an interpolated output g(t). g(t)=αofo+αsfx
+αzf2+αsfa. Here, since αi is not time-varying, g(t) always outputs only the value at the intermediate time point of the input data sample points. However, the output value at the sample point of the input data can be outputted from the input data series as it is, so the output is the interpolated value g(t) and the input data value f (n T
) can be output alternately, and there is no need to time-varying the coefficients of the interpolation acyclic filter. Therefore, the switch 51 in FIG.
By doing the above, you can obtain the same effect as using a time-varying coefficient. This makes it possible to omit a circuit for calculating a time-varying coefficient, a counter for setting an output time, and the like.

The interpolation coefficient αi in FIG. 5 is, for example, the interpolation function 5i
If nx/x (where x=π(t nT)/T)
, ao=as=-0,2122, ao=az=0.
The value will be 6366. However, interpolation α1=α
x = 9/16. In the case of such simple coefficients, the coefficient multiplier can be implemented by data bit shifting and addition/subtraction. Figure 7 shows the value shifted to the -LSB side (However, the MSB can be obtained by shifting it to the retention side. In Figure 7, 71 and 72 are functional elements that shift the MSB by 1 bit and 4 bits, respectively) and retain the MSB. , 73
is an adder. When a coefficient is expressed as a sum or difference of powers of 2, the coefficient multiplier can be constructed of only a bit shifter and an adder/subtractor, and a multiplier with a complicated structure can be omitted.

In FIG. 8 showing another embodiment of the present invention, the delay units 6 to 8 and the switch 51 are the same as those in FIG. FIG. 8 shows an embodiment in which the coefficient multiplier as described above is constituted by a bit shifter and an adder/subtracter, and further, the interpolation function is time symmetric.

This is possible when doubling the sampling frequency because the interpolation time is halfway between the input sample points.

That is, g(t)=aofo+a1f1+azfx+α
At 8fδ, α0=α8. Since α1=α2, gc
t)=aoCfo+f3)+axCf1+fx), and the coefficient multiplication can be halved. In FIG. 8, the adder 81 calculates fo +fs, and the adder 82
calculates fx +fz. Each coefficient is multiplied by the method described in FIG.
．． 87 and adders 83 and 84 execute multiplication of αz=9/16. The operation of the switch 51 is similar to that shown in FIG.

As can be seen from the above description, according to this embodiment, the number of coefficient multipliers is halved and the bit shifters are constructed with adders, so that the configuration of the sampling frequency conversion device can be greatly simplified.

〔Effect of the invention〕

According to the present invention, in a device that converts input and output sampling frequencies, the interpolation time τ is set using a PLL that synchronizes the input and output frequencies, so the hardware is simplified and fluctuations in τ are reduced. Since the number of errors is small, an interpolation device with a small interpolation time error can be realized. In addition, since it uses an interpolation method using a time-varying coefficient acyclic filter, high-order interpolation is possible with simple hardware, and there is less interpolation error compared to analog methods or other digital interpolation methods. A memory such as a ROM can be used for the interpolation of high-speed data such as a single image signal.

Further, in the embodiment in which the sampling frequency is doubled, a time-varying coefficient can be realized by using a switch, so that the configuration can be greatly simplified. Furthermore, by selecting an interpolation function whose coefficients are time symmetric, the number of coefficient multipliers can be halved. Further, by configuring a coefficient multiplier using a bit shifter and an adder, the configuration of the sampling frequency conversion device can be further simplified.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a configuration diagram of a time-varying coefficient acyclic filter used in the present invention, Fig. 3 is an explanatory diagram of an interpolation method for time interpolation, and Fig. 4 is a phase diagram. A diagram showing the configuration of a synchronous loop, FIG. 5 is a configuration diagram showing an embodiment of the present invention,
FIG. 6 is a waveform diagram for explaining the operation of FIG. 5, FIG. 7 is a diagram for explaining bit shift and multiplication by addition and subtraction, and FIG. 8 is a diagram showing another embodiment of the present invention. 1... Phase comparator, 2... Voltage controlled oscillator, 3, 4
... Frequency divider, 5... Latch, 6-8, 201-20
n...Delay element, 9-12...Memory, 13-15
゜221~22n, 81~84... Adder, 211~
21n, 71-73... Coefficient multiplier, 41... Reduced pass filter, 42... Mixer, 43... Fixed frequency oscillator. % 1 Figure 2 Mouth Figure 3 Figure 4 (1, α) Figure S 6 Figure 7 Figure 8 Figure 33

Claims (1)

[Claims] 1. The system of the n-th order acyclic filter whose input data is the sampled values of n consecutive points sampled in the first sampling period is determined for each second sampling period. An output obtained by interpolating the value at the interpolation time of the sample value at the n point using a time-varying coefficient acyclic filter given as a function of the interpolation time within the time at the n point, and sampling at the second sampling period. In an interpolation device that obtains a data string, the reciprocal of the first sampling period fs_1
and a voltage controlled oscillator having a frequency fc that is the least common multiple of the reciprocal fs_2 of the second sampling period within a variable oscillation frequency range, and a first frequency divider and a phase comparator having a frequency division ratio of fc/fs_1. A phase-locked loop configured by fc/
The first sampling frequency fs_1 and the second sampling frequency fs_2 are synchronized by a second frequency divider having a frequency division ratio of fs_2, and the first frequency divider has a frequency division ratio of fs_2. A sample characterized in that a latch is provided to store and hold the frequency, the latch operation of the latch is executed by a clock synchronized with the output of the second frequency divider, and the latch output is used as the interpolation time. frequency conversion device. 2. A time-varying coefficient non-recursive filter that gives the coefficients of an n-th order non-recursive filter whose input data are sampled values of n consecutive points as a function of the interpolation time within the time of the n points, which is determined for each output sampling period. In a sampling frequency conversion device that interpolates the value of the input data at the interpolation time and obtains an output data string sampled at the output sampling period, the output sampling period is set to 1 of the input sampling period. /2, and an output data switch is provided, and when the data output time coincides with the data input time, the input data is output as is, and when the output time is in the middle of the input time, interpolation is performed by the time-varying coefficient acyclic filter. A sampling frequency conversion device characterized by doubling the sampling frequency of data by outputting a value. 3. The sampling frequency conversion device according to claim 2, wherein the coefficient multiplication of the time-varying coefficient acyclic filter is realized by a combination of data bit shifting and addition/subtraction. Device. 4. In the sampling frequency conversion device according to claim 2, the interpolation order and the output time are selected so that the interpolation coefficients are time symmetric, and the input data of the time-varying coefficient acyclic filter is A sampling frequency conversion device characterized in that the number of times of multiplication is reduced by almost half by adding delay element outputs having the same value of interpolation coefficient in a delay element array and then performing interpolation coefficient multiplication.