JPH01144818A - Numerical value control type oscillation circuit - Google Patents

Abstract

PURPOSE:To raise output frequency by converting the sample rate of a sawtooth wave state outputted from an integration means to Mfs (M is a positive integral number) with the aid of linear interpolation and level-converting it to a value being a relation that N/M (N is a positive integral number showing the level number of a saw-tooth-wave state) is made to be a modulus with the aid of congruent arithmetic operation. CONSTITUTION:When the sawtooth wave outputted from the accumulator is multiplied by 2, it is sequentially latched by latch circuits 41 and 42 which are serially connected. The output of the circuits 41 and 42 is added to an addition circuit 43. The amplitude level of the addition output from the circuit 43 is mad to be 1/2 by the gain converting circuit 44 of 1/2 gain. The output of the circuit 44 is made to be that data in the central position of a sampling point being adjacent to the sawtooth wave outputted from a latch circuit 13 is obtained by the linear interpolation. Thus, by adding the output of the circuit 44 and the circuit 42, the sawtooth wave of which sample rate is double of that of the sawtooth wave outputted from the latch circuit 13 can be obtained.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is used in variable frequency oscillation circuits such as phase-locked loop circuits (hereinafter referred to as PLL circuits) composed of digital circuits. Numerically controlled oscillator circuit (hereinafter referred to as
(referred to as NGO).

(Prior Art) As a variable frequency oscillation circuit of a so-called digital PLL circuit configured with a digital circuit, an NGO (or referred to as a digitally controlled oscillation circuit DCO) is generally used.

The conventional structure of this NGO is shown in FIG. The illustrated NGO is configured as an accumulator including an adder circuit 12 and a latch circuit 13.

The operation will be explained with reference to FIG. The control data D supplied to the input terminal 11 is added to the latch data of the latch circuit 13 in the adder circuit 12 . This addition output is
Each time the operating clock CK is input to the input terminal 14, it is latched by the latch circuit 13. This latch data is supplied to the output terminal 15 and also to the adder circuit 12.

Through the above operation, an integral output of the input control data D is obtained at the output terminal 15. In this case, since no overflow prevention circuit or the like is added to the accumulator, the accumulator is in the same state as if it were reset at the time of overflow. As a result, as shown in FIG. 6, a sawtooth wave is obtained from the accumulator, which oscillates at an oscillation frequency according to the value of the input control data D as shown in the following equation (1).

However, fosc: oscillation frequency of accumulator [1/5lfs
: Frequency of operating clock CK [1/slN: Number of levels of output data of accumulator The above-mentioned NGO has the following advantages, and in particular, it can be used as a narrowband PLL circuit that can only be realized with a digital PLL circuit. It is indispensable as an oscillation circuit.

(1) Since the frequency sensitivity, which is the ratio of the control data D to the oscillation frequency fO5c, depends only on the operating clock frequency fs and the number N of accumulator levels, ideal linearity can be obtained.

(2) By increasing the number of levels N of the output data of the accumulator, the resolution can be improved without any upper limit.

(3) The envelope when the sawtooth wave, which is the oscillation output, is converted from digital to analog is constant.

(4) Phase continuity of oscillation output is maintained.

FIG. 7 shows an NGO configured to obtain an oscillation output as an analog waveform. In addition, in Figure 7, the previous fifth
The same parts as those in the figures are given the same reference numerals, and detailed explanations will be omitted.

In FIG. 5, the sawtooth wave output from the latch circuit 13 is converted into sine wave data by a lookup table 16 in which sine wave data is written. This sine wave data is converted to a digital/analog conversion circuit (
After being converted into an analog value by a D/A conversion circuit (hereinafter referred to as a D/A conversion circuit) 17, it is smoothed by a low-pass filter (hereinafter referred to as an LPF) 18. As a result, a sine waveform free of distortion and spurious components is obtained and supplied to the output terminal 19.

In this way, all of the above-mentioned advantages can be obtained even when converting digital oscillation output to analog oscillation output, so the NGO shown in Figure 5 is effective for a mixed digital and analog PLL circuit. It is possible to obtain extremely stable and highly pure oscillation output. Moreover, in the NGO shown in FIG. 5, the frequency variable range can be made much wider than that of voltage-controlled crystal oscillator circuits and the like.

Upper limit of NGO oscillation frequency fosc (wax)
can be obtained by setting DN/2 in the above equation (1). This is determined only by the operating clock frequency fs, as shown in the following equation (2).

fo sc (wax) = f s / 2
-(2) However, when obtaining an analog sine wave, it is necessary to remove the spectrum due to folding as shown in Figure 8, so the practical range of the oscillation frequency fosc is f
It becomes smaller than s/2. That is, the oscillation frequency f
As Osc increases, fS fosc decreases, making it difficult for the LPF 19 to separate them.

In this way, the oscillation frequency fO8c of the NGO in FIG. 5 is limited by the operating clock frequency fs, and the oscillation frequency t
In order to increase osc, it is necessary to increase the operating clock frequency fs.

However, in general, an accumulator has an adder circuit that processes a large number of bits in order to increase its resolution. Therefore, in order to increase the operating clock frequency fs, it is necessary to take measures such as operating the adder circuit in a pipeline manner, which results in a very large circuit scale.

Conventionally, an NGO as shown in FIG. 9 or 10 has been used as an NGO that can obtain a high frequency output without increasing the circuit scale. In addition,
In Figure TJ9 and Figure 10, the same parts as in Figure 7 are given the same reference numerals and detailed explanations will be omitted.

First, the NGO shown in Fig. 9 can obtain an output frequency M times that of the NGO shown in Fig. 7 by inputting the output of the LPF 18 to a PLL circuit that can output an oscillation output multiplied by M of the input signal. This is how it was done.

That is, the frequency fo s output from the LPF 18
The signal of c (< fs /2) is sent to the phase detection circuit 20
is supplied to the reference input terminal of The comparison input terminal of this phase detection circuit 20 is supplied with the frequency-divided output of the frequency divider circuit 23 . The detection output of the phase detection circuit 20 is smoothed by the LPF 21 and then sent to a voltage controlled oscillator circuit (hereinafter referred to as VCO).
is supplied as a control voltage. The oscillation output of this VCO 22 is frequency-divided by M in a frequency dividing circuit 23, and the frequency is divided by M into the phase detection circuit 22.
0 as a comparison input, and the output terminal 24
is supplied to As a result, the output terminal 24 has an LPF
An analog sine wave which is synchronized with the output of 18 and whose frequency is multiplied by M is obtained.

Next, the NGO shown in FIG. 10 uses a quadrature modulation type frequency conversion circuit to obtain an NGO output with a frequency higher than the oscillation frequency fO5c of the accumulator.

That is, in the NGO shown in FIG. 10, the oscillation output of the accumulator is converted into a sine wave by the same configuration as the NGO shown in FIG. Conversion circuit 26, LPF2
It is converted into a cosine wave by a circuit consisting of 7. The sine wave output is supplied to a multiplication circuit 28 and multiplied by a signal obtained by passing the oscillation output of the local oscillation circuit 29 through a 90'' phase shift circuit 30.

On the other hand, the cosine wave output is supplied to the multiplication circuit 31 and multiplied by the oscillation output of the local oscillation circuit 29. The multiplication outputs are added by an adder circuit 32, band-limited by a bandpass filter 33, and then supplied to an output terminal 34.

Here, with reference to FIG. 11, the principle of converting the frequency of the oscillation output of the accumulator by a quadrature modulation circuit using a sine wave output and a cosine wave output will be explained.

In FIG. 11, a vector OA is the oscillation output of the local oscillation circuit 29. Now, to simplify the explanation,
It is assumed that this vector OA does not rotate. Next, the vector OB, which is orthogonal to the vector OA, is the phase shifted output of the 90'' phase shift circuit 30.These two vectors OA.

Sine wave sinωosc t and cosine wave co in OB respectively
Multiplying by sωosc t and adding the vectors results in the output of the vector OC. However, ωOSC is 2πfO5c
It is. The vector OC rotates counterclockwise with respect to the vector ωosc. This means that the frequency of the local oscillation circuit 29 is increased by ωosc. As a result, the NGO shown in FIG. 10 can obtain an operation equivalent to vCO whose center frequency matches the oscillation output of the local oscillation circuit 29.

According to the configuration of FIG. 9 or FIG. 10 described above, the output frequency of the NGO can be increased without increasing the operating clock frequency fs.
Unlike O, even if the output frequency of NGO is increased, the circuit size does not increase.

However, in the NGO shown in FIG. 9, unless the response speed of the M multiplier PLL circuit is made sufficiently fast, the response of the digital PLL circuit itself using the NGO will be affected. Therefore, a new problem arises in that the loop gain of the M multiplier PLL circuit must be made sufficiently large. Also, N.C.O.
Since an LC type oscillation circuit is used as the VCO 22 in order to accommodate a wide variable frequency range, a problem arises in that the purity of the oscillation spectrum deteriorates.

On the other hand, the NGO shown in FIG. 10 has a problem in that spurious signals are likely to occur due to imperfections in the orthogonal modulation circuit (orthogonal deviation, carrier leak, etc.). FIG. 12 shows an example of spurious generation due to imperfections in the orthogonal modulation circuit. FIG. 12 shows the case where there is a carrier leak called vector oO' and a perpendicular shift, and the composite vector OC is
At the same time that the phase change is no longer constant, the envelope is also no longer constant. An example of the output vector in this case is
Shown in Figure 3. Figure 13 shows the desired spectrum fo+f
osc (fO is the reference station oscillation frequency), fOS
This shows how a spectrum of fOfO9sfo±2fos is generated. This is because, as shown by the dotted line in FIG. 12, the locus of the tip of the composite vector OC is not on the circumference.

(Problems to be Solved by the Invention) As mentioned above, in NGOs, conventionally, in order to increase the output frequency, the operating frequency fs of the accumulator is increased, or the oscillation output of the accumulator is controlled by PLL.
A configuration using a frequency conversion circuit and a configuration using a quadrature modulation type frequency conversion circuit have been considered.

However, the configuration in which the operating frequency fs of the accumulator is increased has a problem in that the circuit scale increases. Further, in a configuration using a multiplier PLL circuit, since the response speed of the PLL circuit must be increased, there are problems in that the loop gain must be increased and that the purity of the oscillation spectrum deteriorates. Finally, a configuration using a quadrature modulation circuit has a problem in that spurious signals are likely to occur due to imperfections in the quadrature modulation circuit.

Therefore, an object of the present invention is to provide an NGO that can increase the output frequency without causing these problems.

[Configuration of the Invention (Means for Solving Problems) In order to achieve the above object, this invention has fs[1/s
A sawtooth wave is obtained by integrating the human control data at a frequency of . The sample rate of this sawtooth wave is converted to Mfs (M is an integer) by linear interpolation. This converted output is level-converted to a value modulo N7M (the number of amplitude levels of the oscillation output of the integrating means) by a congruence calculation.

(Function) According to the above configuration, the number of samples of the sawtooth wave output from the integrating means is multiplied by M by linear interpolation. This fS
If the amplitude full scale (N level) of the sawtooth wave whose sample rate is converted from to Mfs corresponds to 2π [rad], it has a minimum number of samples of 2M per 2π. By converting the level of such harmonics by a joint operation modulo N7M, the amplitude that corresponds to 2π at the N level can be changed to correspond to 2π at the N/M level. As a result, the period of the sawtooth wave is
It is possible to obtain a sawtooth wave which is shortened to 1/M and has a frequency M times that of the sawtooth wave output from the integrating means.

Note that if the value of the input control data is substantially constant, the sawtooth wave output from the integrating means will be a substantially perfect sawtooth wave whose period is substantially constant and increases linearly. Therefore, the number of samples can be sufficiently increased by M times by linear interpolation.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. Note that in FIG. 1, the same parts as in FIG. 7 are given the same reference numerals and detailed explanations will be omitted.

The NGO shown in FIG. 1 shows an example of doubling the sawtooth wave output from the accumulator.

In FIG. 1, the sawtooth wave output from the accumulator is sequentially latched by latch circuits 41 and 42 connected in series. The accumulator operating clock CK is used as a latch pulse for each of the latch circuits 41 and 42.

The outputs of the latch circuits 41 and 42 are added by an adder circuit 43. The added output of this adder circuit 43 has an amplitude level reduced to 1/2 by a gain conversion circuit 44 with a gain of 1/2.

The output of the gain conversion circuit 44 is obtained by linear interpolation of data at the center of adjacent sample points of the sawtooth wave output from the latch circuit 13. Therefore, by combining the output of this gain conversion circuit 44 and the output of the latch circuit 42, a sawtooth wave whose sample rate is twice the sample rate of the sawtooth wave output from the latch circuit 13 can be obtained. .

The output of the gain conversion circuit 44 is supplied to a data processing circuit 45, where the level is converted into a value having a relationship modulo N/2 by a joint operation. This data processing circuit 45 simply
This is an extremely simple circuit that ignores the most significant bit (MSB) of input data. Similarly, the output of the latch circuit 42 is also supplied to the data processing circuit 46, and the level is converted to a value having a relationship modulo N/2 by a joint operation.

The output of each data processing circuit 45 , 46 is supplied to a multiplex circuit 47 . This multiplex circuit 47 alternately selects the outputs of the data processing circuits 45 and 46 in accordance with the gate pulse GP of frequency fs supplied to the input terminal 48 and time-division multiplexes them. As a result, the multiplex circuit 47 can obtain a sawtooth wave having a sample rate twice that of the sawtooth wave output from the latch circuit 13.

Note that the circuits after the multiplex circuit 47 are the same as the circuit shown in FIG. 7 above, except that the operating frequency of the D/A circuit 17 is 2 fs.

The operation of the above configuration will be explained with reference to FIGS. 2 and 3.

FIG. 2 shows the interpolation operation and the modulo N/2 data processing operation.

In FIG. 2, the points indicated by O (a, b, c.

d, e, f) are samples of the output data of the accumulator, and the points (g, h, i.

j, k) are these interpolated data. As shown,
In this embodiment, linear interpolation is used for interpolation. This is because if the input data of the accumulator is substantially constant and the oscillation frequency of the sawtooth wave is substantially constant, linear interpolation data can provide an estimated value with extremely few errors.

When actually applying NGO to a narrowband digital PLL circuit, in the steady state of the PLL circuit, NG
Since the output frequency of O hardly changes, linear interpolation is extremely effective in practice.

In Figure 2, the point indicated by (1+ mr nr
o+ p+ q) is a sample obtained by level-converting the output data of the accumulator and the linear interpolation output data to a value having a relationship modulo N/2 by a congruence operation. Assuming that the range of the output data of the accumulator and the linear interpolation output data is (0 to N) as shown in FIG. 2, this is set to the range of (0 to N/2).

For example, in FIG. 2, point h becomes a sample of 1 by subtracting N/2 from its original value. The same applies to other samples. Specifically, this processing can be realized simply by using lower-order data excluding the MSB.

A sample of the output data processed as above is
(a, g, b, 1. m, n, d, j, O.

p), resulting in a sawtooth wave indicated by a solid line in the figure.

According to this, the obtained sawtooth wave has a period that is half the period of the sawtooth wave output from the accumulator, and has a frequency that is twice the frequency of the sawtooth wave.

FIG. 3 is a timing chart showing the operation of the multiplex circuit 47 shown in FIG. As shown in the figure, when the gate pulse is low level, the multiplexer circuit 47 selects the output of the accumulator processed by the data processing circuit 46, and when the gate pulse is high level, the multiplexer circuit 47 selects the data obtained by linear interpolation. Select the one that passed 45.

Note that FIG. 3 shows an example corresponding to each sample in FIG. 2, and each sample is (a + g + b * l
+mrn+d+J+0+p).

As detailed above, in this embodiment, the sample rate of the sawtooth wave output from the accumulator is doubled by linear interpolation, and this converted output is converted to N/2 by a joint operation.
By converting the level to a value modulo ,
A sawtooth wave having twice the frequency of the sawtooth wave output from the accumulator is obtained.

According to such a configuration, the output frequency of the NGO, which was conventionally limited by the operating clock frequency fs of the accumulator, can be digitally multiplied. The output frequency can be increased without increasing phase jitter or generating spurious signals other than the desired oscillation spectrum, which would otherwise occur when increasing the output frequency.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the invention.

In the previous embodiment, a case was explained in which the output frequency of the accumulator was doubled, but this embodiment shows a configuration in which this is converted into a film and multiplied by 2 (K is a positive integer greater than or equal to 2). It is something. In this case, the circuit portions 49 surrounded by broken lines in FIG. 1 may be cascaded in K stages as shown in FIG. 4. However, each circuit section 491...4
The frequencies of the latch pulses of the latch circuits 41 and 42 and the gate pulse GP of the multiplex circuit 47 are determined by each circuit section 49.9. ...It is doubled every 49 times. In FIG. 4, 501...50x are terminals to which latch pulses are supplied, and 511...51x are the corresponding terminals 50,...
...An inverter that inverts the latch pulse supplied to 50x and generates the gate pulse CP.

In addition, in the previous embodiment, the case where the output frequency of an integrating means such as an accumulator is multiplied by 2 was explained, but it is also possible to perform multiplication other than multiplication by 2, such as 3 times, 5 times, etc. Of course.

Further, in the previous embodiment, a case has been described in which level conversion is performed before time division multiplexing is performed by the multiplex circuit 47, but level conversion may be performed after time division multiplexing.

It goes without saying that various other modifications can be made without departing from the gist of the invention.

[Effects of the Invention] As described above, according to the present invention, the output frequency can be increased without increasing the circuit scale and without causing phase noise or spurious in the output vector.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and FIG.
The figure is a signal waveform diagram to explain the operation in Figure 1, and Figure 3 is a timing chart to explain the operation in Figure 1.
FIG. 4 is a circuit diagram showing the configuration of another embodiment of the present invention, FIG. 5 is a circuit diagram showing the configuration of the first example of the conventional NGO, and FIG. 6 is for explaining the operation of FIG. 5. Signal waveform diagram, No. 7
The figure is a circuit diagram showing the configuration of a second example of a conventional NGO.
The figures are a spectrum diagram and a circuit diagram to explain the operation in Figure 7, Figure 11 is a vector diagram to explain the operation in Figure 10, and Figure 12 is a diagram to explain the problem in Figure 10. The vector diagram and FIG. 13 are spectrum diagrams for explaining the problem in FIG. 11.14.48...Input terminal, 12.43...Addition circuit, 1B, 41.42...Latch circuit, 16...
・Lookup table, 17...D/A conversion circuit,
18... LPF, 19... Output terminal, 44... Gain conversion circuit, 45.46... Data processing circuit, 47...
・Multiplex circuit, 49,491...49K
...Circuit section, 50, ...50K...Input terminal, 5
11...51K...Inverter. Applicant's Representative Patent Attorney Takehiko Suzue Figure 5 Figure 6 Figure 4 (2"fs) (2'ts) Figure 7 Figure 8 Figure 11 Figure 12 Figure 13

Claims (2)

[Claims] (1) Integrating means for integrating input control data to obtain a sawtooth wave according to a predetermined operating clock, and linear interpolation of the sample rate of the sawtooth wave output from this integrating means Mf_s (M is a positive integer) rate conversion means for converting into N/M by joint calculation of the conversion output of this rate conversion means.
(N is a positive integer indicating the number of levels of the sawtooth wave) Level converting means for converting the level to a value having a modulus of the number of levels of the sawtooth wave. (2) The above M is set to 2, and the portion consisting of the above rate converting means and the level converting means is added to the above integrating means in K stages (K
is a positive integer) are connected in cascade, and the driving frequency of each stage is sequentially set to 2.
2. The numerically controlled oscillation circuit according to claim 1, wherein the numerically controlled oscillation circuit is configured such that the height increases by a factor of two times.