JPH07142929A - Direct digital synthesizer - Google Patents

Abstract

PURPOSE:To set the band of an output frequency from a direct digital synthesizer to be wide and to set the synthesizer to be highly precise and small in size. CONSTITUTION:A counter 2 which frequency-divides the output reference clock fCLK of a reference oscillation circuit 1 into 1/2, 1/4 and 1/8 so as to output them is provided. Phase step information DELTAtheta is increased by eight times and it is inputted to a numeric control oscillator(NCO) consisting of an adder 5 and a register 6. It is increased by four times and is inputted to NCO consisting of an adder 9 and a register 10. Then, they are integrated by the clock of 1/8 and are added in parallel by two four-phase parallel arithmetic circuits 11 and 12. The output value SIGMADELTAtheta of a switch circuit 13 is taken out from a register 14 at the timing of a reference clock so as to obtain phase information theta.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a direct digital synthesizer used in communication equipment.

[0002]

2. Description of the Related Art A phase locked loop (PLL) structure is a basic structure that is widely applied to a frequency synthesizer for obtaining a highly accurate output frequency. P
The LL configuration has a great advantage in terms of circuit scale and frequency accuracy that an output frequency phase-locked with a high-accuracy reference oscillation source using a crystal oscillator can be obtained with a relatively small-scale circuit. However, since the PLL configuration is a negative feedback control loop, there is a reciprocal relationship between the signal-to-noise ratio (C / N) of the frequency synthesizer output and the response speed of the loop. Therefore, when it is necessary to perform high-speed frequency switching for each short burst section, such as TDM (Time Division Multiplex) communication and frequency hopping communication, if the response speed of the frequency switching operation is increased, the system bandwidth Becomes wider and the C / N of the output decreases, which is a problem. One way to solve this problem is to use the Direct Digital Synthesize
There is a DDS type high speed synthesizer using r; DDS). Since the DDS type high speed synthesizer does not have a feedback loop having a PLL configuration unlike the conventional frequency synthesizer, the frequency switching time can be shortened.

FIG. 7 is a block diagram of a conventionally used DDS circuit. In the figure, 101 is a reference oscillating circuit that outputs a reference clock signal f _CLK , 102 is an adder that performs addition operation with the phase step information Δθ set from the outside as one input and the integrated value ΣΔθ of Δθ as the other input,
Reference numeral 103 denotes a register which outputs the integrated value ΣΔθ as phase information θ according to the timing of the reference clock signal f _CLK , and 104 and 105 each have an output value θ of the register 103 as an address, and one cycle of a previously stored cosine waveform and sine waveform. A ROM (Read Only Memor) that can sequentially read the amplitude data (0 ° to 360 °)
y), 106 and 107 are ROM 104 and R, respectively.
D that converts the output value of OM105 into an analog voltage signal
/ A converter (Digital to Analog Converter), 108
Numerals 109 denote a low pass filter (LP) that removes harmonic components contained in the outputs of the D / A converter 106 and the D / A converter 107 and outputs a desired signal.
F). Here, the configuration of the adder 102 and the register 103 shown in FIG. 7 is generally a numerically controlled oscillator (Numerica).
l Controlled Oscillator (NCO).

In the above structure, the oscillation frequency f _DDS by the DDS circuit is represented by a mathematical expression. First, the output frequency f _DDS
And the period T _DDS thereof have the following relationship.

[Equation 1] Further, the cycle T _NCO of the output value θ of the register 103 can be expressed by the following equation.

[Equation 2]

Here, the ROM 104 and the ROM 105
Is the period T of the phase information θ output from the register 103.
_{Since the NCO} outputs the amplitude data for one cycle of the output frequency f _DDS, the following equation holds.

## _EQU3 ## T _NCO = T _DDS (3) From the equations (1), (2), and (3), the output frequency f _DDS and the reference clock signal f _CLK are as follows.

[Equation 4] From the equation (4), in order to increase the frequency frequency f _DDS of the DDS circuit and widen the band, the reference clock signal f
It turns out that it is sufficient to speed up _CLK .

[0006]

[SUMMARY OF THE INVENTION However, the adder 102 and the register 103 is negative feedback configuration, and, since the processing by the reference clock signal f _CLK, a limit to the speed of the reference clock signal f _CLK Occurs. Further, if the value of N in the equation (4) is increased, the minimum step frequency can be set to a smaller value and a highly accurate signal can be obtained, but the circuit scale of the adder 102 and the register 103 increases, and the reference clock signal f _As in the case of increasing the speed of _CLK , the calculation processing time is limited. Therefore, in the conventional configuration, it is difficult to broaden the output frequency band and improve the accuracy.

The present invention provides a direct digital synthesizer suitable for miniaturization and IC implementation, which eliminates the problem of the operation processing speed of the integrating operation due to the widening of the output frequency and the high accuracy in the conventional configuration. The purpose is to

[0008]

A direct digital synthesizer according to the present invention comprises a reference oscillation circuit for outputting a reference clock signal f _CLK , and the reference clock signal f _CLK.
The clock signal f _CLK / 2, f _CLK / 4, f
A counter for outputting _CLK / 8, a {× (-1)} circuit for multiplying the externally set phase step information Δθ by (−1) to output −Δθ, and the phase step information Δθ of 8
A {× 8} circuit that multiplies and outputs 8 · Δθ, and {× 8}
The output value of the circuit 8 · Δθ is used as one input, and the integrated value Σ8 · Δθ of 8 · Δθ is used as the other input. The integrated value Σ8 · Δθ according to the timing of the signal f _CLK / 8
And a {× 2} circuit that doubles the phase step information Δθ and outputs 2 · Δθ,
The {× 4} circuit for multiplying the phase step information Δθ by 4 to output 4 · Δθ and the output value 4 · Δθ of the {× 4} circuit as one input, and the output value Σ8 of the first register・ Δ
a second adder that performs subtraction processing with θ as the other input;
The output value of the second adder is set to the clock signal f _CLK /
According to the timing of 8, the second register outputs as Σ8 · Δθ−4 · Δθ, the output value −Δθ of the {× (−1)} circuit, and the output value Σ8 · Δ of the first register.
θ, the phase step information Δθ, and the output value 2 · Δθ of the {× 2} circuit are input, and the addition operation is performed in parallel to obtain the phase information Σ8 · Δθ−Δθ, Σ8 · Δθ, Σ8 · Δ.
Output value of the first four-phase parallel arithmetic circuit that outputs θ + Δθ, Σ8 · Δθ + 2 · Δθ, and the {× (−1)} circuit −Δ
θ and the output value of the second register Σ8ΔΔ-4−Δ
θ, the phase step information Δθ, and the output value 2 · Δθ of the {× 2} circuit are input, and the addition operation is performed in parallel to obtain the phase information Σ8 · Δθ-5 · Δθ, Σ8 · Δθ-4 ·.
Phase information Σ8 · Δθ−Δθ output from the second four-phase parallel arithmetic circuit that outputs Δθ, Σ8 · Δθ−3 · Δθ, Σ8 · Δθ−2 · Δθ. ，
Σ8 · Δθ, Σ8 · Δθ + Δθ, Σ8 · Δθ + 2 · Δθ
And the phase information Σ8 · Δθ-5 · Δθ, Σ8 · Δθ-4 · Δθ, Σ8 output from the second four-phase parallel arithmetic circuit.
· Δθ-3 · Δθ, and Σ8 · Δθ-2 · Δθ, the clock signal f _CLK / 2 is outputted from the counter, f _CLK
/ 4, f _CLK / 8, a first switching circuit for sequentially switching and outputting according to the timing, and an output value of the first switching circuit,
A third register that outputs phase information θ in accordance with the timing of the reference clock signal f _CLK , and an output value θ of the third register as an address, for one cycle (0 ° to 360 °) of a cosine waveform stored in advance. A first ROM capable of sequentially reading the amplitude data and an amplitude value of one cycle (0 ° to 360 °) of a sine waveform stored in advance are sequentially read by using the output value θ of the third register as an address. A second ROM that can be used and the first RO
First D that converts the output from M into an analog voltage signal
/ A converter, a second D / A converter that converts the output from the second ROM into an analog voltage signal, and the first D / A converter
First low-pass filter for removing the harmonic component of the output of the D / A converter, and second low-pass filter for removing the harmonic component of the output of the second D / A converter It is characterized by having a container.

Further, in the above direct digital system synthesizer, the first ROM and the second R
Complement switching for outputting OM according to the most significant bit of the output value θ of the third register, a value excluding the most significant bit of the output value θ, or its complementary value as θ ′ (0 ≦ θ ′ ≦ π) A circuit and a third adder for performing a subtraction process with the output value θ ′ of the complement switching circuit as one input and π / 2 (radian) as the other input, and outputting θ′−π / 2, A third ROM capable of sequentially reading amplitude data of a half cycle (0 ° to 180 °) of a cosine waveform stored in advance using the output value θ ′ of the complement switching circuit as an address, and the third adder. With the output value θ'-π / 2 as the address,
It is characterized in that it is replaced with a fourth ROM capable of storing the same data as the third ROM and sequentially reading the same data.

Further, in the above direct digital system synthesizer, the third ROM and the fourth R are provided.
A second switching circuit that outputs the OM by inputting the output value θ ′ of the complement switching circuit and the output value θ′−π / 2 of the adder and alternately switching the outputs according to the polarity of the reference clock signal f _CLK. And an output value of the second switching circuit as an address, a half cycle (0 ° to 180 °) of a cosine waveform stored in advance.
Fifth R that can sequentially read the amplitude data of
The OM and the output of the fifth ROM are replaced with a third switching circuit that switches the output destination at the same timing as the second switching circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a structural example diagram showing a first embodiment of the present invention. In the figure, reference numeral 1 is a reference oscillating circuit, which outputs a reference clock signal f _CLK . Reference numeral 2 denotes a counter, which divides the reference clock signal f _CLK to generate a clock signal f _CLK.
Outputs _CLK / 2, f _CLK / 4, f _CLK / 8. Reference numeral 3 is a {× (−1)} circuit, which multiplies the phase step information Δθ set from the outside by (−1) and outputs −Δθ.
The circuit can be easily configured with an inverting circuit and an adder. Four
Is a {× 8} circuit, and the phase step information Δθ is 8
Multiply and output 8 · Δθ. The circuit can be easily constructed by a shift wiring to the upper side of 3 bits. An adder 5 receives the output value 8 · Δθ of the {× 8} circuit 4 as one input and the integrated value Σ8 · Δθ of 8 · Δθ as the other input, performs an addition operation, and outputs the result. Reference numeral 6 denotes a register, which temporarily stores the output value of the adder 5 and outputs the output f of the counter 2.
_At the timing of _CLK / 8, Σ8 · Δθ is supplied to the outside and fed back as the other input of the adder 5. here,
The adder 5 and the register 6 form an NCO.

Reference numeral 7 denotes a {× 2} circuit which doubles the phase step information Δθ and outputs 2 · Δθ. The circuit is
It can be easily constructed by shift wiring to the upper side of 1 bit. 8
Is a {× 4} circuit, and the phase step information Δθ is 4
Multiply and output 4 · Δθ. The circuit can be easily constructed by shift wiring to the upper side of 2 bits. 9 is an adder,
One of the output values Σ8 and Δθ of the register 6 (addition value)
Then, the addition value 4 · Δθ of the {× 4} circuit 8 is used as the other input (subtraction value) to perform addition operation and output. Reference numeral 10 is a register for temporarily storing the output value of the adder 9,
Σ8 according to the timing of the output f _CLK / 8 of the counter 2
・ Output Δθ-4 ・ Δθ.

Reference numeral 11 denotes a four-phase parallel arithmetic circuit, which is {× (-
1)} output value of circuit 3 −Δθ and output value Σ of register 6
And 8 · [Delta] [theta], and the phase step information [Delta] [theta], {× 2} performs addition operation in parallel as inputs the output value 2 · [Delta] [theta] of the circuit 7, the phase information Shiguma8 · according to the timing of the output f _CLK / 8 of the counter 2 Δθ-Δθ, Σ8 · Δθ, Σ8 · Δθ
+ Δθ, Σ8 · Δθ + 2 · Δθ are output. The circuit is
It can be easily configured with an adder and a register. Reference numeral 12 is a four-phase parallel arithmetic circuit, and the output value of the {× (−1)} circuit 3 −Δθ
, The output value Σ8 · Δθ−4 · Δθ of the register 6, the phase step information Δθ, and the output value 2 · of the {× 2} circuit 7.
The addition operation is performed in parallel with Δθ as an input, and the counter 2
Phase information Σ8 according to the timing of the output f _CLK / 8
Δθ-5 · Δθ, Σ8 · Δθ-4 · Δθ, Σ8 · Δθ-
3 · Δθ, Σ8 · Δθ-2 · Δθ are output. The circuit can be easily configured with an adder and a register.

Reference numeral 13 denotes a switching circuit, which is phase information Σ8 · Δθ−Δθ, Σ8 · supplied from the four-phase parallel arithmetic circuit 11.
Δθ, Σ8 · Δθ + Δθ, Σ8 · Δθ + 2 · Δθ, and the phase information Σ8 · Δ supplied from the 4-phase parallel arithmetic circuit 12.
θ-5 / Δθ, Σ8 / Δθ-4 / Δθ, Σ8 / Δθ-3
.DELTA..theta., .SIGMA.8 .DELTA..theta.-2 .DELTA..theta.
_In accordance with the timing of _CLK / 2, f _CLK / 4, f _CLK / 8, ΣΔθ is sequentially switched and output. Reference numeral 14 is a register, which outputs the output value ΣΔθ of the switching circuit 13 as the phase information θ according to the timing of the reference clock signal f _CLK .

Reference numerals 15 and 16 are ROMs, and the register 14
Of the cosine waveform and the sine waveform stored in advance as one address (0 ° to 360 °) are sequentially read. Reference numerals 17 and 18 denote D / A converters, which convert the output values of the ROM 15 and ROM 16 into analog voltage signals and output them. 19 and 20 are LP
F, D / A converter 17 and D / A converter 1 respectively
The harmonic components included in the output of 8 are removed, and the cosine wave from the LPF 19; I = cos (Δθ · f _CLK · t), LPF 20
To sine wave; Q = sin (Δθ · f _CLK · t).

FIG. 4 is a block diagram showing the details of the four-phase parallel arithmetic circuit 11 shown in FIG. In the figure, 111, 112, 1
Reference numeral 13 denotes an adder, which outputs the output value Σ8 of the register 6, respectively.
・ Δθ is one input and the other input is {×
(-1)} output value of circuit 3-[Delta] [theta], phase step information [Delta] [theta], and output value 2 * [Delta] [theta] of {* 2} circuit 7 are added and calculated to obtain phase information [Sigma] 8 * [Delta] [theta]-[Delta] 8, [Sigma] 8 * [Delta] [theta], respectively.
+ Δθ, Σ8 · Δθ + 2 · Δθ are output. Reference numeral 114 denotes a register, which is the output value Σ8 · Δθ−Δ of the adder 111.
θ, output value Σ8 · Δθ of register 6, output value Σ8 · Δθ + Δθ of adder 113, output value Σ8 · Δ of adder 113
θ + 2 · Δθ is temporarily stored and the counter 2 output f _CLK /
Output according to the timing of 8. The four-phase parallel operation circuit 12 in FIG. 1 can also be configured as in the configuration example diagram shown in FIG.

Next, FIG. 2 is a structural example view showing a second embodiment of the present invention. 1 to 14, 1 of the components of FIG.
7 to 20 are the same as those in FIG. Reference numeral 21 denotes a complement switching circuit, which inputs the most significant bit of the output value θ of the register 14 as the polarity bit C, and controls the output by the polarity bit C. It has a function of switching the data excluding the most significant bit of θ when C = “0” and the 1's complement value of the data when C = “1” and outputting it as θ ′. The same function can be easily configured by using an exclusive OR circuit. 22
Is an adder, the output value θ ′ of the complement switching circuit 21 is used as one input (addition value), and π / 2 (radian) is used as the other input (subtraction value) to perform addition operation, θ′−π / 2 is output. Reference numeral 15 'is a ROM, which sequentially reads amplitude data of a half cycle (0 ° to 180 °) of a cosine waveform stored in advance, using the output value θ'of the complement switching circuit as an address.
16 'is a ROM, and the output value of the adder 22 is θ'-π /
Using the address 2 as an address, the same data as the ROM 15 'stored in advance is sequentially read.

Next, FIG. 3 is a structural example view showing a third embodiment of the present invention. 1 to 14 and 1 of the components of FIG.
7 to 22 and 15 'are the same as in FIG. Reference numeral 23 denotes a switching circuit, which outputs the output value θ ′ of the complement switching circuit 21 and the adder 2
The output value of 2 is θ′−π / 2, and θ′− when f _CLK = “1” and θ′− when f _CLK = “0” according to the polarity of the reference clock signal f _CLK. Outputs by alternately switching π / 2. At this time, the ROM 15 ′ alternately outputs the waveform data for θ ′ and θ′−π / 2. Two
Reference numeral 4 denotes a switching circuit, which distributes the output value of the ROM 15 'into cosine waveform data and sine waveform data at the same switching timing as the switching circuit 23 and outputs the data.

[0019]

The operation of the configuration example shown in FIGS. 1 and 4 will be described with reference to FIG. FIG. 5 shows an output value Σ8 · Δθ (broken line) of the register 6 and an output value Σ · Δ of the switching circuit 13 in FIG.
FIG. 6 is a waveform diagram showing an example of a time change of θ (solid line). Now, at time T ₀ , the output value of the register 6 is set to Σ8 · Δθ = 0. Since the adder 5 and the register 6 form an NCO, one cycle of the output f _CLK / 8 of the counter 2 (8 / f
The integration of 8 · Δθ is continued for each _CLK ), and the output value of the register 6 rises in steps of 8 · Δθ as shown by the broken line in FIG. Next, when the time T ₁ is reached and the value of Σ8 · Δθ reaches 2 ^M or more, the value of Σ8 · Δθ is modulo 2 ^M.
By the integrating operation of 2), the value decreases to a value obtained by subtracting 2 ^M , increases again in the step of 8 · Δθ, and the same operation as after time T ₀ is repeated. From the above operation, the output value Σ of the register 6
It can be seen that 8 · Δθ exhibits a sawtooth waveform value. Where the phase step value is Δφ (Δφ = 8 / Δθ),

[Outer 1]

[0020]

[Equation 5]

In FIG. 1, the register 10 is an adder 9
Output value Σ8 · Δθ−4 · Δθ according to the timing of f _CLK / 8. Since the output value Σ8 · Δθ of the register 6 has a sawtooth waveform, the output value Σ8 ·· of the register 10
It can be seen that Δθ-4 · Δθ also exhibits a sawtooth waveform. Four
The phase parallel operation circuit 11 has -Δθ, Σ8 · Δ, Δθ, 2 · Δ
With θ as an input value, the four-phase parallel operation circuit 12 has −Δθ, Σ8
・ Δθ-4 ・ Δθ, Δθ, 2 ・ Δθ are input values, and Σ8
・ Δθ−Δθ, Σ8 ・ Δθ, Σ8 ・ Δθ + Δθ, Σ8 ・
Δθ + 2 · Δθ, Σ8 · Δθ−5 · Δθ, Σ8 · Δ
θ-4 · Δθ, Σ8 · Δθ-3 · Δθ, Σ8 · Δθ-2
・ Output Δθ respectively. The output value is input to the switching circuit 13, and clock signals f _CLK / 2, f _CLK / 4, f
Σ8 ・ Δθ-5 ・ Δ according to the timing of _CLK / 8
θ, Σ8 · Δθ-4 · Δθ, ..., Σ8 · Δθ + Δθ, Σ
The output is switched as ΣΔθ in the order of 8 · Δθ + 2 · Δθ. As a result, the output θ of the register 14 has a saw-tooth waveform that rises stepwise in steps of Δθ in accordance with the timing of the reference clock signal f _CLK , as shown by the solid line in FIG. Here, when N = M is set in the equations (2) and (5), the following equation is established.

[0022]

[Equation 6] From this, it can be seen that the output value θ of the register 14 is equivalent to the output waveform of the conventional register 103 shown in FIG. 7. Further, the equation (5) can be expressed as the following equation.

[Equation 7]

From the above, the direct digital synthesizer according to the present invention is designed so that Δφ (= Σ
Since the phase step information of (8Δθ) is integrated, the integrated clock signal can be speeded up to ⅛ of that of the conventional method. That is, it can be said that this is equivalent to accelerating the integration operation by a factor of eight. Output value Σ of switching circuit 13
Δθ depends on the timing of the reference clock signal f _CLK ,
The register 14 outputs θ, and using the phase information θ as an address, the ROM 15 and the ROM 16 in which the cosine waveform data and the sine waveform data are stored in advance are accessed to output the digital values of the cosine waveform and the sine waveform, respectively. The outputs of ROM15 and ROM16 are D
The signals are converted into analog signals by the A / A converter 17 and the D / A converter 18, and harmonics are removed by the LPF 19 and the LPF 20, respectively, and output as perfect cosine and sine waveforms. Equations (7) and (8) show the respective waveforms.

[Equation 8] Cosine wave; I = cos (Δθ · f _CLK · t) …… (7) Sine wave; Q = sin (Δθ · f _CLK · t) …… (8)

Next, the second embodiment shown in FIG. 2 will be described with reference to FIG. To simplify the explanation,
Consider a case where M = 5, that is, the maximum value of the phase information θ output from the register 14 is 2 ^M −1 = 31. Figure 6
6A shows the output waveform of the complement switching circuit 21, FIG. 6B shows the output waveform of the adder 22, and FIG. 6C shows the ROM 15 ', RO.
The address-to-data relationship of M16 'is shown. Time 0 now
In, the phase information θ output from the register 14 is set to 0. As the time advances in the order of 0 → 1 → 2 → 3 → ..., the register 14 becomes 2 ^M −1 as shown by the broken line in FIG.
= 31, when the value of θ reaches 2 ^M or more, it decreases to θ = 0 and rises again stepwise. Here, focusing on the most significant bit (MSB) of θ, 0 ≦ θ
In the section of ≤2 ^M-1 -1, MSB = 0, and 2
It is clear that MSB = 1 in interval ^{M-1 ≦ θ ≦ 2 M} -1. Therefore, the complement switching circuit 21
When SB = 0, the output value of register 14 is output and MS
When B = 1, since the 1's complement value of θ is output, the output value θ ′ of the complement switching circuit 21 rises stepwise from time 0 to time 15 as shown by the solid line in FIG. 6 (A). And time 1
From 6 to time 31, a triangular staircase waveform descending stepwise is formed. From time 32, the same operation as from time 0 to time 31 is repeated.

Next, the output waveform of the adder 22 will be described. Now, since it can be expressed as π / 2 = 2 ^M−2 −1, the adder 22
The output value of is θ′−π / 2 = θ′−2 ^M−2 −1. Therefore, in contrast to the output waveform of the complement switching circuit 21 shown by the broken line in FIG. 6B, the output of the adder 22 becomes the triangular staircase waveform shown by the solid line in FIG. 6B. ROM 1 is shown in FIG.
5 is a diagram showing an address-to-data relationship of 5'and ROM 16 ', where M =
When the output value of the complement switching circuit 21 is 5, the maximum value is 15
The data corresponding to the amplitude of the cosine waveform is stored using the addresses up to. Therefore, the triangular staircase waveform value of the complement switching circuit 21 shown by the broken line in FIG.
When you access by entering the address, the address is 0 → 1 → 2 →
The data changes in the order of 14 → 15 → 15 → 14 → ... → 1 → 0 → 0 → 1 →, and the data forming the cosine waveform stored in advance in the ROM 15 ′ is read and output.

The adder 2 shown by the solid line in FIG.
When the triangular staircase waveform value of 2 is input to the ROM 16 ′ and accessed, the address is 7 → 6 → ... → 1 → 0 → 0 → 1 →
… → 14 → 15 → 15 → 14 → ... and the ROM1
The data forming the cosine waveform stored in advance in 6'is read and output. Here, the waveform output from the ROM 16 ′ is π / of the waveform output from the ROM 15 ′.
2 is a waveform with a phase delay of 2. Therefore, it is clear that the output waveform of the ROM 16 'is a sine waveform. As shown in the above operation, the triangular staircase waveform is generated, the waveform data is input as the addresses of the ROM 15 ′ and the ROM 16 ′, and in the method of accessing, the ROM 15 ′ and the RO 15 ′ are used.
The data of M16 'is the half cycle (0 °
It can be seen that amplitude data of ~ 180 °) is sufficient. ROM
The outputs of 15 'and ROM 16' are converted into analog signals by a D / A converter 17 and a D / A converter 18, respectively.
The harmonics are removed by the LPF 19 and the LPF 20, respectively, and output as a complete cosine waveform and a sine waveform. The waveform is the waveform shown in the equations (7) and (8) obtained in the first embodiment.

Next, the operation of the configuration diagram of the third embodiment of the present invention shown in FIG. 3 will be described. Complement switching circuit 21
Output value θ ′ of the adder 22 and the output value θ′−π / 2 of the adder 22 are input to the switching circuit 23, and according to the polarity of the reference clock signal f _CLK , θ ′ is obtained when f _CLK = “1”, f _CLK =
When it is “0”, θ′−π / 2 is output alternately. ROM1
5'is alternately accessed using θ'and θ'-π / 2 as an address, and alternately outputs the amplitude data corresponding to θ'and θ'-π / 2. The output value of the ROM 15 ′ is switched by the switching circuit 24 that performs switching operation at the same timing as the switching circuit 23.
Is input to the amplitude data corresponding to θ ′ when f _CLK = “1”, and is output to the amplitude data corresponding to θ′−π / 2 when f _CLK = “0”. As shown in the above operation, it can be seen that the ROM can be shared by arranging the switching circuit that performs the switching operation at the same timing in the front stage and the rear stage of the ROM. The amplitude data corresponding to θ ′ is converted into a cosine waveform of an analog value via the D / A converter 17 and the LPF 19, and the amplitude data corresponding to θ′−π / 2 is converted to the D / A converter 18 and the LPF 20. Is converted into an sine waveform having an analog value via, and the waveforms shown in the equations (7) and (8) are obtained as in the first embodiment.

[0028]

As described in detail above, in the configuration of the direct digital synthesizer of the present invention, the integrating operation is performed by the clock signal having a speed of 1/8 of that of the conventional method, so that the output frequency is increased. That is, it is possible to widen the band and improve the accuracy of the set frequency. Also, RO
By devising the access method of M, the ROM capacity can be reduced, which can contribute to miniaturization. Furthermore, since most of the circuits are logical operations, they can be integrated into an IC,
It has the advantages that it is easy to reduce the size, power consumption, and cost.

[Brief description of drawings]

FIG. 1 is a configuration example diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration example diagram showing a second embodiment of the present invention.

FIG. 3 is a structural example diagram showing a third embodiment of the present invention.

FIG. 4 is a configuration example diagram of a four-phase parallel arithmetic circuit of FIG.

5 is a time chart of the integrating operation and the output value of the register 14 in FIG.

6 is a time chart of output values of the complement switching circuit 21 and the adder 22 of FIG. 2 and an explanatory diagram of address pair data of the ROM 15 ′ and ROM 16 ′.

FIG. 7 is a diagram showing a configuration example of a conventional direct digital synthesizer.

[Explanation of symbols]

 1 Reference Oscillation Circuit 2 Counter 3 {x (-1)} Circuit 4 {x8} Circuit 5 Adder 6 Register 7 {x2} Circuit 8 {x4} Circuit 9 Adder 10 Register 11, 12 4 Phase Parallel Operation Circuit 13 Switching circuit 14 Register 15, 15 ', 16, 16' ROM 17, 18 D / A converter 19, 20 LPF 21 Complement switching circuit 22 Adder 23, 24 Switching circuit 111, 112, 113 Adder 114 Register 101 Reference oscillator circuit 102 Adder 103 Register 104, 105 ROM 106, 107 D / A converter 108, 109 LPF

Claims (3)

[Claims] 1. A and a reference oscillation circuit for outputting a reference clock signal f _CLK, divides the reference clock signal f _CLK, the clock signal f
A counter that outputs _CLK / 2, _fCLK / 4, _fCLK / 8, and a {x (-1)} circuit that multiplies the phase step information Δθ set from the outside by (-1) and outputs -Δθ. , A {× 8} circuit for multiplying the phase step information Δθ by 8 to output 8 · Δθ, and an output value 8 · Δθ of the {× 8} circuit as one input,
A first adder for performing an addition operation using the integrated value Σ8ΔΔθ of Δθ and an output value of the first adder as the clock signal f _CLK /
In accordance with the timing of 8, a first register for outputting the integrated value Σ8 · Δθ, a {× 2} circuit for doubling the phase step information Δθ and outputting 2 · Δθ, and a quadrupling of the phase step information Δθ And the output value 4 · Δθ of the {× 4} circuit is used as one input, and the output value Σ8 · Δθ of the first register is subtracted as the other input. A second adder that performs processing, and an output value of the second adder are used as the clock signal f _CLK /
A second register for outputting Σ8 · Δθ−4 · Δθ in accordance with the timing 8; an output value −Δθ of the {× (−1)} circuit; and an output value Σ8 · Δθ of the first register, The phase step information Δθ and the output value 2 · Δθ of the {× 2} circuit are input to perform an addition operation in parallel to obtain the phase information Σ8 · Δθ−Δ.
θ, Σ8 · Δθ, Σ8 · Δθ + Δθ, Σ8 · Δθ + 2 ·
A first four-phase parallel operation circuit that outputs Δθ, an output value −Δθ of the {× (−1)} circuit, an output value Σ8 · Δθ−4 · Δθ of the second register, and the phase step Information Δθ and the output value 2 · Δθ of the {× 2} circuit
Phase and Σ8
Δθ-5 · Δθ, Σ8 · Δθ-4 · Δθ, Σ8 · Δθ-
A second 4-phase parallel arithmetic circuit that outputs 3 · Δθ, Σ8 · Δθ−2 · Δθ, and phase information Σ output from the first 4-phase parallel arithmetic circuit.
8 · Δθ−Δθ, Σ8 · Δθ, Σ8 · Δθ + Δθ, Σ8
.DELTA..theta. + 2.multidot..DELTA..theta. And the phase information .SIGMA.8.delta..theta.-5.delta..theta., .SIGMA.8.delta..theta.
-4 · Δθ, Σ8 · Δθ-3 · Δθ, Σ8 · Δθ-2 ·
Δθ is the clock signal f output from the counter
_A first switching circuit for sequentially switching and outputting according to the timing of _CLK / 2, f _CLK / 4, f _CLK / 8, and an output value of the first switching circuit, the reference clock signal f
_A third register that outputs phase information θ according to the timing of _CLK , and the amplitude value of one cycle (0 ° to 360 °) of the cosine waveform stored in advance is sequentially read using the output value θ of the third register as an address. And a second ROM capable of sequentially reading amplitude data of one cycle (0 ° to 360 °) of a sine waveform stored in advance by using the output value θ of the third register as an address. A first D / A converter for converting the output from the first ROM into an analog voltage signal; and a second D / A converter for converting the output from the second ROM into an analog voltage signal. A converter, a first low-pass filter that removes a harmonic component of the output of the first D / A converter, and a harmonic component of an output of the second D / A converter With a second low-pass filter Direct digital-N synthesizer according to claim. 2. The direct digital synthesizer according to claim 1, wherein the first ROM and the second ROM are arranged according to a most significant bit of an output value θ of the third register,
A value excluding the most significant bit of the output value θ or a complement value thereof is output as θ ′ (0 ≦ θ ′ ≦ π); and an output value θ ′ of the complement switching circuit is one input, π / 2
Performs subtraction processing using (radian) as the other input, and θ '
A third adder which outputs −π / 2, and an amplitude value of a half cycle (0 ° to 180 °) of the cosine waveform stored in advance are sequentially read by using the output value θ ′ of the complement switching circuit as an address. Replaced with a third ROM that can be used and a fourth ROM that can store the same data as the third ROM and sequentially read it, using the output value θ′−π / 2 of the third adder as an address. The direct digital synthesizer according to claim 1, characterized in that. 3. The direct digital synthesizer according to claim 2, wherein the third ROM and the fourth ROM are provided with an output value θ ′ of the complement switching circuit and an output value θ′−π / of the adder. 2 as an input, and the reference clock signal f _CLK
A second switching circuit which alternately switches and outputs according to the polarity of, and the amplitude value of a half cycle (0 ° to 180 °) of the cosine waveform stored in advance is sequentially read by using the output value of the second switching circuit as an address. And a third switching circuit for switching an output destination at the same timing as that of the second switching circuit, and a fifth ROM capable of controlling the output of the fifth ROM. Direct digital synthesizer described.