SU1515364A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the spectral purity of the output oscillations. The device contains a controlled oscillator 1, a divider 2 frequencies with a variable division factor, a pulse-phase detector 3, a low-pass filter 4, a reference oscillator 5, accumulators 6, 7, a delay element 8, a code adder 9, a pulse-voltage converter 10 , DAC 11, differentiation element 12. A block 13 specifying initial codes has been entered into the device. When switching on or switching the frequency, the block 13, in accordance with the value of the fractional part code arriving at its first input, forms the division factor M generates the code of the initial states of accumulators 6, 7 and during one period of the clock frequency outputs the generated codes to the outputs. The criterion for choosing the value of the initial states is to achieve the minimum of the variances, the deviation of the instantaneous values of the phase from the linearly varying average, since the linear law of change of the phases causes no interference in the output signal. 2 Il.

Description

38 V.P.Maksimov

i.8)

one

(21) i 35CI95 / 2 j-09

(22) 12/28/87

(() 15.10.89. Bullet. To (72) V.L. Znakovsky, and V.Ya.Levantovsky (53) 621.373. (Qi

(36) USSR author's certificate

S 12938 41, class And 03 L 7/18, 09.10.8i.

For Va UK t 2026268, cl. H 3 A, 01.30.80.

(ZM DIGITAL FREQUENCY SYNTHESIZER

(37) The invention relates to radio engineering. The purpose of the invention is to increase the spectral purity of the output oscillations. The device contains a controlled oscillator 1, a divider 2 frequencies with a variable coefficient. division, pulse-phase detector 3, low-pass filter k, reference oscillator 3, accumulators 6.7 delay element 8, adder E codes, pulse-to-voltage converter 10, DAC 11, differentiation element 12. In the device entered block 13 setting initial codes. When switching on or switching the frequency, the block 13 in accordance with the value of the fractional part code of the coefficient that arrives at its first input. dividing M forms the code of the initial states of drives 6, 7 and during one period of the clock frequency gives the generated codes to the outputs. The criterion for selecting the value of the initial states is to achieve a minimum of the variances of the deviation of the instantaneous phase values from the linearly varying average, since the linear law of phase variation causes no interference in the output signal. 2 Il.

with

(L

l M

Iffffx.

ate

ate

with

SG)

four

Sriga

The invention relates to radio engineering and can be used in radio engineering devices for various purposes, including as a heterodyne of receiving devices.

The aim of the invention is to increase the spectral purity of the output oscillations.

Figure 1 shows the electrical structural diagram of a digital frequency synthesizer; 2 shows an example of the execution of the initial code assignment block.

Digital frequency synthesizer contains

there is a controlled oscillator 1, a divider g overflow of the second accumulator 7 2 frequencies with a variable division factor (DPKD), a pulse-phase detector (IFD) 3, a low-pass filter k, a reference oscillator, the first drive 6, the second drive 7, element 20 8 delays, an adder 9 codes, a pulse width to voltage converter 10, a digital-to-analog converter (D / A converter) 11, a differentiation element 12 and a block 13 for setting initial 25 codes.

The initial codes assignment block (Fig. 2) contains the first memory block 1 and the adder is fed to the first input and reduces its content by one. As a result of the interleaving coefficients divided in time, the PDKD2 is divided. on average, the coefficient is divided by N, M, and the output frequency of the driven oscillator CB (,, Y (N, M), where IQ is the clock frequency of the reference generator 5.

The DAC 11, the converter 10 and the differentiation element 12 form the noise compensation circuit of the fractionality of DCDD 2 coefficients occurring in the jump from the integral coefficients of the DCPD 2. The content code is the second drive 7, which contains information about the phase difference integral, arrives at the first input of the DAC and converts in the negative tension, which is then differentiated by the differentiation element 12 and is fed to the input of the filter k. Folding with the output voltage of the IFD 3, the computational signal reduces the jumps of the output oscillation phase of the controlled reactor 1. The unevenness of the fragmentation noise compaction in the frequency range is reduced by shaping the reference voltage of the DAC 1 from the output sequence of the PDKD 2 by conversion 10; In the operating frequency range of the generator 2, the duty ratio and pulses of the DPDD 2 vary, the reference voltage generated by the transducer changes accordingly, and therefore the compensation effect changes; Valuable C

ti, second memory block 15, memory register 1, match element 17, and D 30 trigger 18.

Digital frequency synthesizer works as follows.

The controlled oscillator 1, the DPDD 2, the IFD 3 and the filter 35 form a ring and the phase-locked loop of the controlled oscillator 1, the first and second drives 6 and 7, the delay element 8 and the adder 9 form a fractional bit unit, which 40 together with PDKD 2 performs the functions of a frequency divider with a fractional variable division factor. The fractional variable division factor is realized by alternating four, 5 integer division coefficients of DPKD 2 in time: N-1; N; N + 1; N + 2. This is done as follows. The code of the integer part of the division factor N is fed to the code input of the adder 9. The code of the fractional part of the division factor M is fed to the input of the first drive 6, the content code of which is fed to the input of the second drive 7. The first and second drives 6 and 7 have the same.

50

forging capacity A (where M, the maximum possible value of M). The contents of the first drive 6 under the action of clock pulses from the output

55

which is the inputs of the adder 9

the reference generator 5 is increased by the value of M. The content of the second accumulator 7 under the action of a clock pulse increases by the magnitude of the contents of the neptjoro accumulator 6. When the first and second accumulators 6 and 7 overflow, an overflow signal appears at their overflow outputs,

on the appropriate and increases it

content per unit. Simultaneously delayed element 8 delay for one period of the reference frequency signal

overflow of second drive 7

arrives at the first input of the adder 9 and reduces its contents by one. As a result of the alternation in time of the integer division factors of the PDKD2. on average, the division factor is N, M, and the output frequency of the controlled oscillator CB (,, Y (N, M), where IQ is the clock frequency of the reference oscillator 5.

The DAC 11, the converter 10 and the differentiation element 12 form a fractional noise compensation circuit that occurs when the DDCS integer division factors change abruptly 2. The content code of the second drive 7, which contains information about the phase error integral, is fed to the first input of the DAC 11 and is converted to negative a voltage which is then differentiated by the differentiation element 12 and is fed to the input of the filter k. Adding to the output voltage of the IFD 3, the compensating signal reduces the phase jumps of the output oscillation of the controlled oscillator 1. The nonuniformity of noise compensation of fractionality in the operating frequency range is reduced due to the formation of the reference voltage of the DAC 1 1 from the output sequence of DPKD 2 pulses using the converter 10, In the operating frequency range of the controlled generator 1, the duty cycle of the DPCD 2 varies, the reference voltage generated by the converter 10 accordingly changes, and The compensating effect produced by the DAC 11 varies.

The first and second drives 6 and 7 have inputs of the initial installation. When switching on or switching the frequency, the block 13 of the task in accordance with the value of the fractional part code of the coefficient 10 arriving at its first input

20

25

Neither M forms the code of the initial states of the first and second drives 6 and 7 and during one period of the clock frequency gives the generated codes to the outputs. In this case, until the next frequency switching of the digital frequency synthesizer, the operation of the task block 13 is completed, and in the first and second accumulators 6 and 7, the process of changing their contents begins, causing the alternation of four integer division factors of the PDKD 2.

The initial states of the first and second drives 6 and 71 once 5 set with the help of block 13 tasks when changing M, for each value M are chosen such that in the process of changing the contents of the first and second drives 6 and 7, the order of time and the magnitude of the discontinuous changes in the DPDD 2 integer division ratio is optimal from the point of view of obtaining a minimum of fractional noise in the output oscillation of the controlled oscillator 1.

Task block 13 contains the first and second memory blocks 1 and 15, the address inputs of which receive the fractional part code of the division factor M. This same code goes to the register 1b and the first input of the match element 17. In register 1b, the current code value of the fractional part M is remembered. When M is changed, the newly set value M | does not coincide with the value Mj filled in register 16. With Mi + i, at the output of the coincidence element, a signal of the logical unit and the next clock pulse appear, the input-expander, which sequentially connects to the C input of the D flip-flop 18, the setting delay element and the adder digits D trigger 18 in a single state. The signal that appeared on the second inputs of the first and second blocks 14 and 15 serves as a command to issue the codes of the initial states of the first and second drives 6 and 7 stored in the first and second blocks 1 and 15 of memory at address M. The same signal from the output of the D-flip-flop 18 serves as a JQ signal of the input code M, -. in register 1b. After the occurrence through the delay time in the register 1b at its outputs of the code

thirty

35

first and second blocks 14 and 15 of the memory and transfers the register 1b to the mode of storing the recorded information, i.e. at each change in the value of M for one period of the clock frequency, implification of the code for the initial states of the first and second drives 6 and 7 is issued. In this case, the codes of the initial states recorded in the first and second blocks 1 4 and 15 of memory for each value of M are optimal in terms of obtaining a minimum of noise fractionality. The criterion for choosing the value of the initial states is to achieve a minimum of the variance of the deviation of the instantaneous phase values from the linearly varying average, since the linear law of the phase change causes no interference in the output signal.

Claims (1)

Invention Formula A digital frequency synthesizer containing a ringed controlled oscillator, a variable divider frequency divider, a pulse-phase detector and a low-pass filter connected in series to the first drive, second drive, D / A converter, and a differentiation element that is connected to the input low pass filter, pulse-to-voltage converter, the input and output of which are connected respectively to the output of a frequency divider with a variable division factor and BT The opbiM input of the digital-analogue transducer, the output of which is connected to a variable division frequency divider input with a variable division factor, the code input of the code adder is an input of the code of the integer part of the division factor of the digital frequency synthesizer 1 overflow of the first accumulator connected to the second input of the code adder, the third input of which is combined with the input of the delay element and connected to the overflow output of the second accumulator, the clock input of the delay element, the clock input of the first accumulator, the clock input of the second storage ring and a second input of the phase detector pulse-coupled and connected to the output of the reference oscillator, and the input of the first accumulator is input The m. At the output of the coincidence element 17 forms a logical zero signal and the next clock pulse returns the D-flip-flop 18 to the zero state. This leads to the termination of the issuance of the code of the initial states from the outputs of the transducer. the generator, the series-connected delay element and the adder are first and second memory blocks 14 and 15 and transfers the register 1b to the storage mode of the recorded information, i.e. at each change in the value of M for one period of the clock frequency, the initial states of the first and second drives 6 and 7 are issued. In this case, the codes of the initial states for each value of M written in the first and second blocks 1 4 and 15 of the memory are optimal from the point of view of obtaining a minimum of noise fractionality. The criterion for selecting the value of the initial states is to achieve a minimum of the variances of the deviation of the instantaneous phase values from the linearly varying average, since the linear law of the phase change causes no interference in the output signal. Invention Formula A digital frequency synthesizer containing ringed controlled oscillator, frequency divider with variable division factor, pulse phase detector and low pass filter connected in series to the first drive, second drive, digital to analog amplifier, and a differentiation element that is connected to the input of the lower filter frequency converter, pulse-to-voltage converter, the input and output of which are connected respectively to the output of a frequency divider with a variable division factor and BT opbiM digital-to-analog converter input, series-connected delay element and coder If the output is connected to a variable division frequency divider installation input, the code input of the code adder is the code input of the integral part of the division ratio of the digital frequency synthesizer, the overflow output of the first drive is connected to the second input of the code adder, the third input is combined with the input the delay element and connected to the overflow output of the second accumulator, the clock input of the delay element, the clock input of the first accumulator, the clock input of the second accumulator and the second input of the pulse- the phase detector is combined and connected to the output of the reference oscillator, and the input of the first accumulator is the input the fractional part code of the digital frequency synthesizer division factor, characterized in that, in order to increase the spectral frequency of the output signal, a block for specifying the initial codes is entered, the first and second outputs of which are connected to the corresponding 151536 8 To the input of the first accumulator and the installation input of the second accumulator, the clock input of the initial code assignment block is connected to the output of the reference generator, and the code input of the initial code assignment block is connected to the input of the first accumulator.