SU1478327A1 - Frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to provide a phase shift mode. The frequency synthesizer contains a controlled Mr. 1, a block dividing unit 2, accumulating adders 3 and 4, RS - trigger 5, DAC 6, low pass filter 7, adder 8 codes and a frequency divider 9. The goal is achieved by introducing an adder 8, which plays the role of a phase manipulator, and a divider 9, from which the modulation index depends on the division ratio. 1 il.

Description

114

The invention relates to radio engineering and can be used to obtain a grid of stable frequencies in receiving and transmitting and measuring equipment.

The aim of the invention is to provide a phase shift mode.

The drawing shows an electrical structural diagram of a frequency synthesizer.

The frequency synthesizer contains a controlled oscillator 1, block dividing unit 2, first accumulating adder (NS) 3, second NS 4, RS flip-flop 5, digital analog converter (DAC) 6, low pass filter 7, adder 8 codes, frequency divider 9.

The frequency synthesizer works as follows.

The division unit 2, as well as the first and second CS 3 and 4 are clocked with the reference frequency pulses f0. Block 2 division

produces the partial x0 and the remainder bx from dividing the number aq and k the number b, where a and b are the numbers that determine the output frequency ft of the frequency synthesizer, and q is the capacity of the first NS 3. The code inputs of dividing unit 2 receive the corresponding values of divisible aq and divisor b . The divider b is also used to control the capacity of the second HC4. When the second HC4 is filled, the signal from its overflow output enters the overflow input of the first HC3. The first and second HC3 and 4 serve as a single accumulating adder that integrates the number x aq / b xa + kx / b. The integration result x0 (t) is summed with a fixed number ($ in adder 8 and a variable number x (t) is fed to the input of the lower bits of the D / A converter 6, the most significant bit of which is controlled by the RS flip-flop 5). the detector, and, based on the equality of frequencies at its inputs in the steady state, the frequency at the output of the controlled oscillator 1 is equal to fu fc-an / b, where n is the division factor of the divider 9

Fragmentation interference that occurs in a phase locked loop system is often

You are compensated for by the non-multiplicity of the numbers x0 and q by converting the current value of the number x (t) at the output of the adder 8 using the DAC 6, the output of which is through the filter 7

0

0

five

0

five

d

is fed to the input of the controlled generator 1.

Adder 8 performs the role of a phase handler. The time shift of the process x (t) and the overflow pulse of the adder 8 relative to the initial process x0 (t) and the overflow of the first HC 3 is proportional to the number y. Consequently, the phase shift & t of the output signal of the frequency synthesizer is proportional to the change in Df of the number f and is equal to DC) 2lm./Up/q.

The boundaries of possible changes to the modulating number (J are related to the range of possible values of the number x0. The number Lp cannot be less than the number x0, otherwise situations are possible when the adder 8 does not overflow on every filling cycle of the first HC 3, which is equivalent to RS-flip-flop 5 fails and synchronization in the auto-tuning loop is violated.On the other hand, the cp number cannot be greater than q-xfl, because in this case the adder 8 is constantly overflowed and there are no control pulses on the corresponding RS-flip-flop 5. In this way , Parts Required to satisfy the condition

(q-xm),

where xm is the maximum value of xfl in the range of its changes. In this case, the range of phase change of the output signal is

(1-2xM / q).

At the same time, xm cannot exceed q / 2.

To overlap the full range of phase changes introduced frequency divider 9. For 2TT, it is necessary that xm (n-1) q / 2n, or, taking into account that xfl aq / b, am (n-1) b / 2n, where am is the maximum value of the number a in the range of its changes. If n-1 (divisor 9 is absent), i.e. modulation index 2 it is not provided with finite values of atm numbers. When the divider 9 is switched on with the division factor, the required modulation index is reached with variations of x and in the range of 0 ameb / 4. When the limits expand to, respectively, q / n

five

O

five

and QЈamЈb / 3.

A further increase in n is ineffective and, in the limit, makes it possible to vary the numbers xm and am, respectively, in the ranges and. Corresponding range of yft change

The number is determined from the expression.

At. When or the minimum value of tp, the maximum value (fm 3q / 4.

Claims (1)

Invention Formula A frequency synthesizer containing serially connected RS flip-flops, a digital-to-analog converter, a low-pass filter and a controlled oscillator, serially-connected code division and the first accumulating adder, as well as the second accumulating adder, the first code input and the overflow output of which are connected respectively to the output of the residual signal the code divider and the transfer input of the first accumulating adder, the first code input of the code divider is the input of the signal of the dividend frequency synthesizer, the second to dovy input divider codes obe- five 0 The second code input of the second accumulating adder is dinene and is the input of the frequency synthesizer divider signal, the clock inputs of the code division block, the first and second accumulating adders are combined and are the input signal of the frequency synthesizer reference frequency, so that phase shift keying, code adder and frequency divider are entered, the input and output of which are respectively connected to the output of the controlled oscillator and to the first input of the RS flip-flop, code output and overflow output ora codes are respectively connected to the input of low bits of the DAC and the second input of RS-trigger, the output of the first accumulator is connected to the first input of the adder codes, the second input of which is input to the code modulation signal of the frequency synthesizer. Editor NLazarenko Compiled by Y. Kovalev Tehred M. Khodanich Proofreader M. Vasilyeva Order 2372/54 Circulation 885 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 ....-..-- - - - ----- - - - - .-,., - - -.-.-.-. -----.-.-- - - . - --- - - -----.-- - -. - - - .-. Production and publishing complex Patent. Uzhgorod, st. Gagarin, 101 Subscription