SU799100A1 - Digital frequency synthesizer - Google Patents

Description

(54) DIGITAL FREQUENCY SYNTHESIZER

one

The invention relates to radio engineering and can be used in radio communication systems and measuring equipment.

A known frequency divider with a fractional division ratio, consisting of a serially connected control unit, a programming unit, a pulse elimination unit and a counter, the output of the control unit is connected to the control input of the counter and the splitter input is connected to the signal input of the pulse excluding unit and to the signal input of the programming unit The control input of which is associated with the output of divider 1.. The closest in technical essence to the present invention is a digital frequency synthesizer comprising a synchronized oscillator connected to a ring, a frequency divider with a fractional division factor, a pulse-phase detector, an adder and a low-pass filter, to the input of a pulse-phase detector a reference frequency source is connected and a digital-to-analog converter 2 output is connected to the input of the adder} However, the well-known digital frequency synthesizer does not provide high suppression in the output signal of interferences frequency grid steps.

The purpose of the invention is to improve the interference in the input signal of interference that is a multiple of the frequency grid step.

The goal is achieved by the fact that the digital frequency synthesizer. medu by random informational outputs of fractional fractional schemes

10 remnants of the programming block and the corresponding one-by-one inputs of a digital-to-analog converter; additionally introduced a memory block, the control input of which is connected to

15, exit divider.

FIG. Figure 1 shows the electrical structure of a digital frequency synthesizer; FIG. 220 represents the electrical circuit of the programming unit for one fractional bit of a frequency divider with a fractional division factor.

25

The digital frequency synthesizer contains a synchronized oscillator 1 in a ring, a frequency divider 2 with a fractional division factor, consisting of a connected control unit 3, a programming unit 4,

pulse exclusion unit 5 and counter 6, a pulse-phase detector 7, an adder 8 and a low-pass filter. The outputs of control unit 3 are connected respectively to the control input of counter 6 and the control input of programming unit 4. The input of the splitter 2 frequency with fractional division factor is connected to signal input of the programming unit 4 and with the signal input of the pulse elimination unit 5.

Another control input of the programming unit 4 is connected with the output of the splitter 2 frequency with a fractional division factor. The output of the reference frequency source 10 is connected to the input of the pulse-phase detector 7, and the output of the digital-to-analog converter 11 is connected to the input of the adder 8. A memory unit 12 is additionally inserted between the bit information outputs of the fractional residual circuits of the programming unit 4 and the corresponding digital inputs of the digital-analog converter 11. The memory input 12 of the memory unit 12 is connected to the output of a frequency divider with a fractional division factor of 2.

The programming unit 4 for one fractional bit (Fig. 2) contains a ring 13 connected, a controllable decade 14 and a trigger 15. The signal input of the controllable decade, 14 is connected to the signal input of 16 fractional residual scaling circuit decades. The output of the scaling circuit DB is the control output of the programming unit 4 Other outputs of the scaling circuit 16 are informational. They are connected to the outputs of the triggers of the scaling circuit 16, which form a decade. The other input of the valve 13 is the signal input of the programming unit 4. The other input of the controlled decade 14 is the control input of the programming block 4 and provides for the setting of the division factor. The second input of the trigger 15 is another control input of the programming unit 4.

 The digital frequency synthesizer works as follows.

/ Frequency at the output of the frequency synthesizer F Fbn e EGR, is the frequency of the source 10 of the reference frequency, K. is the division factor of the divider 2 frequencies with a fractional division factor. For example, we put K - 250/4. The setup of the desired division factor provides the block of the coefficient of 250, and the controllable decade 14 of the programming unit 4 is set to obtain the division factor of 2.

Suppose the phase locked loop system is

In synchronization and in scaling circuit 16 of programming unit 4, the number 0 is written. In this case, pulses from the output of synchronized generator 1 will be fed through block 5 of pulse elimination to the signal input of counter 6 and simultaneously to the input of scaling circuit 16 of programming block 4. After receiving 4 the pulses to the input of the programming unit 4, the signal from the output of the controlled decade 14 switches the trigger 15, the programming unit 4 closes and the number 4 will be written in its recalculation circuit 16. After 250 pulses are received at the input tchika used at the output of frequency divider 2 with a fractional dividing ratio for Vits pulse which goes to pulse-phase detector 7, a programming unit 4 and in the memory unit 12.

Due to the fact that the division factor of 250.4 is required, the first division cycle is produced with a coefficient of 250, then a voltage jump is generated at the output of the pulse-phase detector 7 proportional to the fractional remainder, i.e., number 4. This voltage jump is superimposed to the output voltage of the pulse phase detector 7 and exists during the entire second division cycle.

The arrival of the output pulse of the splitter 2 frequency with a fractional division factor to the control inputs of the memory block 12 ensures that the number 4 is written into the memory block 12.

The memory unit 12 is intended to be stored for the next dividing cycle of the number fixed in the scaling diagrams of the programming unit for the previous dividing cycle. For each decimal fractional bit, the memory consists of 4 cells by the number of triggers in the decimal fractional decade of the fractional remainder of the corresponding bit. At the end of each division cycle, each cell of the division is connected to the information outputs of the corresponding fractional residual recalculation circuit using valves controlled by the output pulse of the splitter 2 frequency with a fractional division factor. As a result, each two-stable memory cell assumes the position of its trigger, O or 1, respectively, and stores this state until the next pulse: and from the output of divider 2, frequencies with a fractional division factor. The 12pam directly controls the operation of the digital-to-analog converter 11. The output of the digital-to-analog converter 11 forms a voltage, which in analogue format corresponds to the number stored in memory 12. This voltage is inputted to the adder 8 to compensate for the jumps

voltage arising at the output of the pulse-FD detector 7 due to the fractional division in the ring of the phase-locked loop.

Thus, the output of the digital-to-analog converter 11 during the entire second division cycle will be a voltage proportional to the fractional remainder, i.e., number 4.

The arrival of the output pulse of the splitter 2 frequency with a fractional division factor in the programming LOCK 4 will ensure the switching of the trigger 15 and the opening of the valve 13. As a result, 2 more pulses will go to the programming unit 4 and the number 8 will be recorded in the scoring circuit 16, etc.

Since the second division cycle is also made with a factor of 250, the phase mismatch between the reference pulse 10 and the pulse from the output of the splitter 2 frequency with a fractional division factor due to the fractionality will increase, resulting in the formation of a voltage jump at the output of the phase detector 7 8 etc

In the third division cycle, 4 more pulses will arrive at the input of the programming unit 4. As a result, an overflow pulse is created in the recalculation circuit 16, which acts on the pulse elimination unit 5, ensuring that this division cycle is performed with a factor of 251. At the same time, the fractional remainder, i.e., the number 2, will be written in the scaling circuit 16. If the phase correction is completed, then at the output of the pulse-phase detector 7 after the third dividing cycle, the voltage jump will also be proportional to the fractional remainder, i.e. the number 2, etc.

The proposed digital frequency synthesizer provides a step voltage at the output of a digital-to-analog converter, the law of which change is strictly inverse to the law of changing the step voltage of interference arising at the output of a pulse-phase detector because of fractional division, which provides more complete compensation for the above-mentioned voltage jumps in a ring phase-locked loop and thereby improves the suppression of the output signal interference, multiples of the grid frequency.

Claims (2)

1. USSR author's certificate  506130, class H 03, K 23/00, 01/17/74. 0 2. USSR author's certificate  4,70901, cl. H 03 B 21/02, 01/12/73 (prototype).