JP3506287B2 - Frequency synthesizer and frequency synthesizer method - Google Patents

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial applications Conventional technology (Fig. 5) Problems to be Solved by the Invention (FIG. 5) Means for Solving the Problems (FIG. 1) Action (Fig. 1) Example (FIGS. 1 to 4) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer and a frequency synthesizing method, and can be applied to those which generate a high frequency signal whose frequency is stabilized by a PLL (phase locked loop) circuit.

[0003]

2. Description of the Related Art Conventionally, there is a frequency synthesizer of this type that outputs at a frequency that is an integral multiple of the frequency output by a reference oscillator or a frequency with a narrow interval other than the integral multiple. As shown in FIG. 5, the fractional-N synthesizer 1 has a reference frequency signal S output from a reference oscillator 2.
1 is supplied to the phase comparator 3. The phase comparator 3 detects the phase difference between the frequency-divided signal S2 output by the frequency divider 4 having the logic circuit configuration and the reference frequency signal S1, and gives the error signal S3 based on the detected phase difference to the adder 5. .

The adder 5 adds the interpolation signal S4 output from the automatic phase interpolation circuit 6 to the error signal S3, and gives the added error signal S5 to the low-pass filter 7. Low-pass filter 7
Of the error signal S5 blocks the harmonic component of the error signal S5 and supplies the low-frequency component signal S6 to the sample hold circuit 8. The sample-and-hold circuit 8 samples the low-frequency component signal S6 and supplies the voltage-controlled oscillator 9 with a DC signal S7 whose waveform fluctuation is suppressed.
The voltage-controlled oscillator 9 gives an oscillation signal S8 to an output terminal (not shown) and also gives it to the frequency divider 4 and the frequency division control circuit 10 having a logic circuit configuration.

The frequency divider 4 is controlled by the control signal S9 of the frequency division control circuit 10 so that the two frequency division ratios at the time of dividing the oscillation signal S8 of the voltage controlled oscillator 9 alternate in a predetermined cycle. The frequency-divided signal S2 that is switched according to each frequency-division ratio
Is output. These two frequency division ratios are 1 / where N is an integer.
N and 1 / (N + 1). By cyclically switching between these two frequency division ratios, it is possible to perform frequency division by a so-called decimal point frequency division method in which frequency division is apparently performed by dividing the integer N by adding a decimal point. The frequency division control circuit 10 gives the control signal S10 to the automatic phase interpolation circuit 5 at every predetermined cycle to interpolate the interpolation signal S4.
Is output.

As a result, the fractional-N type synthesizer 1 corrects the phase error detected by the phase comparator 3 with the interpolation signal S4 so as to oscillate at a frequency of, for example, (N + 0.5) times the reference frequency. The signal S8 can be output.

[0007]

In the fractional-N synthesizer 1, the interpolation signal S4 generated by the automatic phase interpolation circuit 6 is generated by the oscillation signal S of the voltage controlled oscillator 8.
It is generated based on only 8. Therefore, the oscillation signal S
A sample and hold circuit 8 is connected after the low-pass filter 7 so that the frequency of 8 is not directly influenced by the fluctuation of the interpolation signal S4 and an unnecessary wave, so-called spurious is not generated.

However, the above-described structure has a problem that the actual structure is complicated, such as the sample-hold circuit 8 is composed of high-precision parts and the complete integration circuit is connected. In addition, there is a drawback that the timing control of the sample hold is difficult. Furthermore, the above-mentioned fractional N
In the system synthesizer 1, the automatic phase interpolation circuit 6 is configured as a digital analog converter that converts the control signal S10 into an analog level. Therefore, there is a problem that the configuration becomes complicated.

Here, consider a case where the sample and hold circuit 8 is not used and the high frequency signals of a plurality of channels are switched at high speed from the fractional-N synthesizer and taken out. In this case, in order to lock the high frequency signal with the PLL at high speed, it is necessary to increase the cutoff frequency of the low frequency filter to increase the speed. In this case, the reference frequency signal may escape to the voltage controlled oscillator and the oscillation signal of the voltage controlled oscillator may be modulated at the reference frequency. Therefore, there is a problem in that it is difficult to switch high frequency signals of a plurality of channels at high speed and to extract them.

The present invention has been made in consideration of the above points, and when switching and outputting oscillation outputs of a plurality of frequencies at high speed, generation of unnecessary waves is suppressed by a simple structure, and each frequency is made high speed. The present invention is intended to propose a frequency synthesizer and a frequency synthesizer method capable of PLL locking.

[0011]

In order to solve the above problems, the present invention relates to a frequency synthesizer for generating a plurality of channels of signals of an arbitrary frequency in a voltage controlled oscillator and a frequency division ratio with N being an arbitrary integer. 1 / N or 1 /
By (N + 1), frequency dividing means for dividing the oscillation output of the voltage controlled oscillator, reference signal generating means for generating a reference frequency signal, and phase difference between the frequency signal and the divided output of the frequency dividing means. Of the phase difference detection means, a correction output generation means for generating a correction output for correcting the detection output in a phase opposite to the detection output of the phase difference detection means, and the frequency division ratio of the frequency division means are cyclically set to 1 / N or 1 / (N + 1) control means, an addition means for adding the detection output and the correction output, a filter means for converting the addition output of the addition means into a DC voltage and giving it to the voltage controlled oscillator, and a correction output. And a second control means for controlling the correction period according to (4) according to the frequency signal.

Further, according to the present invention, in a frequency synthesizer for generating a signal of an arbitrary frequency for a plurality of channels, the frequency division ratios 1 / N and 1 / (N where N is an arbitrary integer).
+1) is periodically controlled to detect the phase difference between the frequency dividing step for dividing the oscillation output of the voltage controlled oscillator and the phase difference between the reference frequency signal and the divided output obtained by the frequency division processing. The correction output generation step that generates a correction output that corrects the detection output obtained in the phase difference detection step and the detection output that is obtained in the phase difference detection step, the addition step that adds the detection output and the correction output, and the addition step A DC conversion step for generating a DC component for controlling the frequency of the oscillation output of the voltage controlled oscillator is provided according to the obtained addition output, and the correction period by the correction output is controlled according to the frequency signal.

[0013]

The second control means accurately controls the correction period by the correction output according to the frequency signal of the reference signal generation means, and corrects the detection output of the phase difference detection means within this correction period. As a result, when the oscillation outputs of a plurality of frequencies are switched and output at high speed, it is possible to suppress the generation of unnecessary waves with a simple configuration and to lock the PLL frequencies at high speed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 5 are designated by the same reference numerals, reference numeral 11 denotes a fractional-N type synthesizer for generating a plurality of high-frequency signals which are used as the carrier frequency of the communication device as a whole. Fractional
When generating a high-frequency signal of a plurality of channels, the N-system synthesizer 11 is a frequency signal output from a reference signal generation unit, for example, a reference oscillator 2, for example, a frequency that is an integral multiple of the reference frequency signal S1 or a frequency with a narrow interval other than the integral multiple. , And each frequency is locked by the PLL.

Fractional N-system synthesizer 11
The sample hold circuit 8 is omitted from the configuration of the conventional fractional-N synthesizer 1. In addition, the fractional-N system synthesizer 11 is provided with a correction output generation means, for example, an automatic phase interpolation circuit 12, and a second control means, for example, a pulse width control circuit 13, instead of the conventional automatic phase interpolation circuit 6. ing.

The reference oscillator 2 is a TCXO (Temperature
Compensated Crystal Oscillator, temperature-compensated crystal oscillator) and other high-precision oscillators are used. The reference oscillator 2 divides the output of the TCXO to generate a reference frequency signal S1 having an accurate period, and supplies this reference frequency signal S1 to a phase difference detecting means, for example, a phase comparator 3. The phase comparator 3 uses the reference frequency signal S of the reference oscillator 2.
1 and the frequency division means, for example, the frequency division output of the frequency divider 4, for example, the phase of the frequency division signal S2 is compared to detect the phase difference, and the detection output is a rectangular wave whose period is different according to the detected phase difference. , For example, the error signal S3 is given to the adding means, for example, the adder 5.

On the other hand, the reference oscillator 2 supplies the pulse width control circuit 13 with the reference frequency signal S11 generated by dividing the output of the TCXO. The pulse width control circuit 13 has a logic circuit configuration, generates a pulse width control signal S12 having an accurate width (that is, a period) by the reference frequency signal S11, and supplies it to the automatic phase interpolation circuit 12. Automatic phase interpolation circuit 1
2 generates a rectangular wave correction output, for example, a correction signal S13, whose magnitude is set by the control signal S10 and whose correction period is accurately set by the pulse width control signal S12. S13 is given to the adder 5.

The adder 5 receives the error signal S3 from the phase comparator 3.
And the interpolation signal S13 of the automatic phase interpolation circuit 12 are added, and the addition output, for example, the error signal S14 is added to the filter means,
For example, it is given to the low-pass filter 7. The low-pass filter 7 removes the harmonic component of the error signal S14 of the adder 5 and supplies the low-frequency component signal S6 to the voltage controlled oscillator 9. This low pass filter 7 determines the response of the PLL.

The first control means, for example, the frequency dividing control circuit 10, to which the oscillation output of the voltage controlled oscillator 9, for example, the oscillation signal S8 is given, is composed of an adder and a latch. The frequency division control circuit 10 gives the control signal S10 to the automatic phase interpolation circuit 12 so as to eliminate the phase fluctuation of the oscillation signal S8 due to the decimal point frequency division method. As a result, in the fractional-N system synthesizer 11, the PLL repeatedly corrects the phase shift in a short period of time to synchronize the phase of the oscillation signal S8 at high speed.

Here, for example, as shown in FIG. 2, the reference oscillator 2 oscillates at 19.2 [MHz] and divides this by 1.2.
[MHz] reference frequency signal S1 and reference frequency signal S1
1 is generated respectively. The pulse width control circuit 13 gives an output obtained by dividing the reference frequency signal S11 by the counter 16 to the AND circuit 17, and 1 / (1.2 [MHz]) at 1 /
Pulse width control signal S12 having a period of (9.6 [MHz])
To generate. The phase comparator 3 is composed of a NAND gate. The output of the NAND gate is given to the first selection circuit 18 and the second selection circuit 19, and the selection circuit 18 is supplied.
And 19 for controlling the error signal charge pump 20.

The error signal charge pump 20 has a series circuit composed of a charging current source and a charging switch inserted between the first power source and the output terminal, and between the output terminal and the second power source. It is composed of a series circuit including a discharging current source and a discharging switch which are inserted. The error signal charge pump 20 opens and closes the charging switch or the discharging switch by the selection circuit 18 or 19 for a period corresponding to the output of the phase comparator 3 to generate a rectangular wave current, and the rectangular wave current is output as the error signal S3. Is output to the output terminal.

The frequency division control circuit 10 generates a control signal S10 by the latch 21, the adder 22 and the latch 23, and supplies this control signal S10 to the automatic phase interpolation circuit 12. The automatic phase interpolation circuit 12 generates a correction signal having a magnitude corresponding to the control signal S10 and outputs the correction signal to the adder 5 as a correction signal S13 to generate an error signal S3 that causes a phase fluctuation.
To offset. The automatic phase interpolation circuit 12 sets the magnitude of this correction signal by the two correction charge pumps 24 and 25.

Two systems of correction charge pumps 24 and 2
Reference numeral 5 denotes a series circuit including a charge pump current source and a charge pump switch inserted between the first power source and the output terminal, and a charge pump current inserted between the output terminal and the second power source. And a series circuit composed of a switch for a charge pump and a charge pump. One correction charge pump 25 is the other correction charge pump 24.
Input / output a current twice as large as that of.

The adder 5 is an error signal charge pump 2
0 and the currents output from the correction charge pumps 24 and 25 are wire-added and given to the low-pass filter 7. For the low-pass filter 7, a passive circuit or an active circuit is arbitrarily selected. The voltage controlled oscillator 9 is controlled so as to oscillate in the 1.6 [GHz] band. The automatic phase interpolation circuit 12 resets each circuit by the reset circuit 32.

Incidentally, the charge switch and the discharge switch of the error signal charge pump 20 are converted into a passive circuit or an active circuit arbitrarily selected by the low-pass filter 7 by the first and second selection circuits 18 and 19. One switch is used accordingly. Similarly, the correction charge pump 24
The input switch and the output switch of 25 are the third and fourth switches controlled by AND circuits 26 and 27, respectively.
One of the switches is used by the selection circuits 28 and 29 of 1) depending on a passive circuit or an active circuit arbitrarily selected by the low-pass filter 7.

In the above configuration, the frequency divider 4 is set to, for example, 2744 as the integer N of the frequency division count number, and the oscillation signal S8 is frequency-divided by N + (1/4) and N + (1/2), respectively. , N
+ (3/4) frequency division and N + (0/4) frequency division, voltage controlled oscillator 9
It is assumed that the oscillation frequency of is locked by the PLL according to each frequency division ratio and is stable.

First, in the case of dividing by N + (1/4), FIG.
As shown in, at time t ₀ , the reference frequency signal S1
When the phase of the divided signal S2 and the phase of the divided signal S2 match, the error signal S3 of the phase comparator 3 becomes zero. Further, as shown in FIG. 3B, in the automatic phase interpolation circuit 12, the correction charge pumps 24 and 25 are opened, and the correction signal S13 is set to 0. Further, as shown in FIG. 3C, at this time t ₀ , the frequency division count value is switched from N + 1 to N.

Next, from time t ₀ , the period 1 / (1.2 [MHz
]) At the time t ₁ that has elapsed only, the desired N + (1 /
4) Since the frequency divider 4 finishes counting 1/4 frequency earlier than the frequency division, a phase shift of 1/4 frequency occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 1/4 frequency division. As shown in FIG. 3 (A), the error signal S3 at this time is displayed as a rectangle having an area A ₁ in which the magnitude and duration of the current correspond to the height and width on the paper surface, respectively.

On the other hand, just before time t ₁ , the automatic phase interpolation circuit 12 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 24. The correction period by the correction signal S13 is 1 / centered around the time t _1.
(9.6 [MHz]). As shown in FIG. 3B, the correction signal S13 at this time is the magnitude of the current and the duration 1 /
(9.6 [MHz]) is displayed as a rectangle of area A ₁ corresponding to the height and width on the paper. This error signal S
Add 3 and the correction signal S13 to obtain 1 / (9.6 [MHz])
The error signal S14 during the period is substantially 0, and N +
(1/4) It means that the PLL is locked in the divided state.

Then, from time t ₁ , the period 1 / (1.2 [MHz
]) At time t ₂ has elapsed only by 1/2-divided partial fast divider 4 has finished counting, 1/2 frequency division of the phase shift occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a square wave error signal S3 corresponding to the shift of 1/2 frequency division. As shown in FIG.
The error signal S3 at this time is displayed as a rectangle having an area of 2A ₁ .

On the other hand, just before time t ₂ , the automatic phase interpolation circuit 12 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 25. The correction period by the correction signal S13 is 1 / centered around the time t _2.
(9.6 [MHz]). As shown in FIG. 3B, the correction signal S13 at this time is displayed as a rectangle having an area of 2A ₁ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz]) becomes
It becomes substantially zero.

Then, from time t ₂ , the period 1 / (1.2 [MHz
]) At time t ₃ when has elapsed, 3/4 min rotations of fast frequency divider 4 by finishes counting, 3/4 frequency division of the phase shift occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 3/4 frequency division. As shown in FIG.
The error signal S3 at this time is displayed as a rectangle having an area of 3A ₁ . Further, as shown in FIG. 3C, this time t ₃
In, the frequency division count value is switched from N to N + 1.

On the other hand, shortly before time t ₃ , the automatic phase interpolation circuit 12 has the size of the correction charge pumps 24 and 2 for correction.
The correction signal S13 having a rectangular wave determined by 5 is output. The correction period by the correction signal S13 is about the time t ₃
It becomes 1 / (9.6 [MHz]). As shown in FIG. 3B, the correction signal S13 at this time is displayed as a rectangle having an area of 3A ₁ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Is substantially 0.

Then, from time t ₃ , the period 1 / (1.2 [MHz
]) At time t ₄ , the phases of the reference frequency signal S1 and the frequency-divided signal S2 match, the error signal S3 of the phase comparator 3 becomes 0, and the error signal S14 becomes equal to that at time t _0. It becomes 0. Thus the period 1 / (1.2
[MHz]) 4 times the period, that is, period 1 / (300 [KHz])
The above operation is repeated with 1 cycle as the cycle, and the voltage controlled oscillator 9 can output the oscillation signal S8 which is PLL locked to a frequency higher by 300 [KHZ] than the center frequency. Further, the waveform areas of the error signal S3 and the correction signal S13 are set to be the same and cancel each other, and the timings of canceling each other are substantially the same, so that generation of an unnecessary wave applied to the voltage controlled oscillator 9 can be further reduced.

Next, when dividing by N + (1/2),
As shown in (D), when the phases of the reference frequency signal S1 and the divided signal S2 match at time t ₀ , the phase comparator 3
The error signal S3 of is 0. Further, as shown in FIG. 3 (E), the automatic phase interpolation circuit 12 includes a correction charge pump 2
5 is released and the correction signal S13 is set to 0. Further, as shown in FIG. 3 (F), at this time t ₀ , the frequency division count value is switched from N + 1 to N.

Then, at time t ₁ , desired N +
(1/2) When the frequency divider 4 finishes counting by 1/2 the division earlier than the division, a phase shift of 1/2 division occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a square wave error signal S3 corresponding to the shift of 1/2 frequency division. As shown in FIG. 3D, the error signal S3 at this time is displayed as a rectangle having an area of 2A ₂ . Further, as shown in FIG. 3 (F), at this time t ₁ , the frequency division count value is switched from N to N + 1.

On the other hand, just before time t ₁ , the automatic phase interpolation circuit 12 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 25. The correction period by the correction signal S13 is 1 / centered around the time t _1.
(9.6 [MHz]). As shown in FIG. 3E, the correction signal S13 at this time is displayed as a rectangle with an area of 2A ₂ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Becomes 0, and PL is divided by N + (1/2).
It means that you have locked L.

Then, at time t ₂ , the phases of the reference frequency signal S1 and the frequency-divided signal S2 are combined, and the phase comparator 3
The error signal S3 of is 0. As a result, the PLL is locked in the state of being divided by N + (1/2). Further, as shown in FIG. 3 (F), at this time t ₂ , the frequency division count value is switched from N + 1 to N.

Subsequently, the operation at time t ₃ is the same as at time t ₁ described above. Subsequently, the operation at time t ₄ is the same as at time t ₀ described above. As a result, the PLL is locked in the state of being divided by N + (1/2). Thus the period 1 / (1.2
The above-described operation is repeated with a period of twice [MHz]) as one cycle, and the voltage controlled oscillator 9 causes the oscillation signal S8 which is PLL locked to a frequency higher by 600 [KHz] than the center frequency. Can be output.

Next, when dividing by N + (3/4),
As shown in (A), when the phases of the reference frequency signal S1 and the divided signal S2 match at time t ₀ , the phase comparator 3
The error signal S3 of is 0. Further, as shown in FIG. 4 (B), the automatic phase interpolation circuit 12 includes a correction charge pump 2
4 and 25 are opened, and the correction signal S13 is set to 0.
Further, as shown in FIG. 4C, at this time t ₀ , the frequency division count value is switched from N + 1 to N.

Then, at time t ₁ , the desired N +
(3/4) When the frequency divider 4 finishes counting 3/4 earlier than the frequency division, a phase shift of 3/4 frequency division occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 3/4 frequency division. As shown in FIG. 4A, the error signal S3 at this time is displayed as a rectangle having an area of 3A ₃ . Further, as shown in FIG. 4C, at this time t ₁ , the frequency division count value is switched from N to N + 1.

On the other hand, shortly before the time t ₁ , the automatic phase interpolation circuit 12 has the size of the correction charge pumps 24 and 2.
The correction signal S13 having a rectangular wave determined by 5 is output. The correction period based on the correction signal S13 is centered on the time t _1.
It becomes 1 / (9.6 [MHz]). As shown in FIG. 4B, the correction signal S13 at this time is displayed as a rectangle having an area of 3A ₃ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Becomes 0, and PL is divided by N + (3/4).
It means that you have locked L.

Subsequently, at time t ₂ , the frequency divider 4 finishes counting earlier by ½ frequency division, resulting in a phase shift of ½ frequency division. Therefore, the phase comparator 3 detects this phase shift and outputs a square wave error signal S3 corresponding to the shift of 1/2 frequency division. As shown in FIG. 4A, the error signal S3 at this time is displayed as a rectangle with an area of 2A ₃ .

On the other hand, just before time t ₂ , the automatic phase interpolation circuit 12 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 25. The correction period by the correction signal S13 is 1 / centered around the time t _2.
(9.6 [MHz]). As shown in FIG. 4B, the correction signal S13 at this time is displayed as a rectangle having an area of 2A ₃ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Is substantially 0.

Then, at time t ₃ , the frequency divider 4 finishes counting 1/4 frequency earlier, and a phase shift of 1/4 frequency occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 1/4 frequency division. As shown in FIG. 4 (A), the error signal S3 at this time is displayed as a rectangular area A _3.

On the other hand, just before time t ₃ , the automatic phase interpolation circuit 12 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 24. The correction period by the correction signal S13 is 1 about the time t ₃ /
(9.6 [MHz]). As shown in FIG. 4B, the correction signal S13 at this time is displayed as a rectangle having an area A ₁ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Is substantially 0.

Then, from time t ₃ , the period 1 / (1.2 [MHz
]) At time t ₄ , the phases of the reference frequency signal S1 and the frequency-divided signal S2 match, the error signal S3 of the phase comparator 3 becomes 0, and the error signal S14 becomes equal to that at time t _0. It becomes 0. Thus the period 1 / (1.2
The above operation is repeated with a period of four times [MHz]) as one cycle, and the voltage controlled oscillator 9 generates the oscillation signal S8 which is PLL locked to a frequency higher by 900 [KHZ] than the center frequency. Can be output.

Next, when dividing by N + (0/4),
As shown in (D) to (F), by dividing by the integer N, the error signal S3 of the phase comparator 3 becomes zero. As a result, the voltage-controlled oscillator 9 has a frequency P that is a multiple of the integer N.
It is possible to output the LL-locked oscillation signal S8.

In this way, the reference frequency signal S11 having an accurate period is used to generate the correction signal S13 in which the correction period is accurately set every period 1 / (1.2 [MHz]), and the error signal S3 can be corrected more accurately. As a result, the generation of unwanted waves can be effectively reduced. Also, a period that is one cycle common to N + (1/4) division, N + (1/2) division, N + (3/4) division and N + (0/4) division, 1 / (300 [KH
z]) detects and corrects the phase error and locks the PLL, in addition to the 1/4 period 1 / (1.2 [MHz])
It is possible to detect and correct the phase error by adjusting the correction timing for each and to lock the PLL. As a result, when the oscillation signals S8 of a plurality of channels are switched at high speed, the frequencies of the respective channels can be PLL-locked at a much higher speed and output.

According to the above configuration, the pulse width control circuit 1
By accurately controlling the correction period by the correction signal S13 in accordance with the highly accurate oscillation output of the reference oscillator 2 according to 3, the error signal S3 of the phase comparator 3 is accurately corrected within this correction period, When high-frequency signals of a plurality of channels are switched and output at high speed, it is possible to suppress the generation of unnecessary waves with a simple configuration and to lock the respective frequencies at high-speed PLL lock.

Further, the automatic phase interpolation circuit 12 can be simply constructed. Further, the sample and hold circuit 8 is not necessary, and the whole structure can be simplified.

In the above embodiment, the case where a high frequency signal for a carrier frequency of a communication device is generated for a plurality of channels has been described, but the present invention is not limited to this, and a signal for an arbitrary frequency is generated for a plurality of channels. It can be widely applied when Also in this case, the same effect as described above can be obtained.

Further, in the above-mentioned embodiment, the case where the frequency between the multiples of N is divided into four has been described, but the present invention is not limited to this, and the frequency between the multiples of N is divided into three. It can also be applied to the case where the frequency is divided into five or less or five or more.

Further, in the above-mentioned embodiment, when setting the magnitude of the correction signal according to the error signal generated by the error signal charge pump 20, the case where two systems of the correction charge pumps 24 and 25 are combined has been described. However, the present invention is not limited to this, and can be applied to the case of performing correction by combining three or more correction charge pumps.

Further, in the above-described embodiment, the case where the timing when the error signal S3 rises and the center of the period of the correction signal S13 coincide with each other regardless of the period of the error signal S3 has been described, but the present invention is not limited to this. Without the error signal S
The center of the period of the correction signal S13 may be adjusted according to the period of 3.

[0057]

As described above, according to the present invention, the second control means accurately controls the correction period by the correction output according to the frequency signal of the reference signal generation means, and the phase difference detection means operates. By accurately correcting the detection output within this correction period, when switching and outputting the oscillating outputs of multiple frequencies at high speed, the generation of unnecessary waves is suppressed with a simple configuration, and each frequency is locked by the PLL lock at high speed. The obtained frequency synthesizer and frequency synthesis method can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fractional-N synthesizer according to one embodiment of a frequency synthesizer and a frequency synthesizer method according to the present invention.

FIG. 2 is a connection diagram showing a detailed configuration of a fractional-N type synthesizer.

FIG. 3 shows the error signal of the phase comparator, the correction signal of the automatic phase interpolation circuit, and the switching of the count number of the frequency divider for N + (1/4) frequency division and N + (1/2) frequency division. It is a timing diagram which shows a timing.

FIG. 4 shows the error signal of the phase comparator, the correction signal of the automatic phase interpolation circuit, and the switching of the count number of the frequency divider for N + (1/4) frequency division and N + (1/2) frequency division. It is a timing diagram which shows a timing.

FIG. 5 is a block diagram showing a conventional fractional-N type synthesizer.

[Explanation of symbols]

1, 11 ... Fractional N-type synthesizer, 2
...... Reference oscillator, 3 ... Phase comparator, 4 ... Frequency divider,
5, 22 ... Adder, 6, 12 ... Automatic phase interpolation circuit,
7 ... Low-pass filter, 8 ... Sample-hold circuit, 9
...... Voltage control oscillator, 10 ...... Division control circuit, 13 ......
Pulse width control circuit, 15, 16 ... Counter, 17, 2
6, 27 ... AND circuit, 18, 19, 28, 29 ...
Selection circuit, 20 ... Charge pump for error signal, 21,
23 ... Latch, 24,25 ... Compensation charge pump, 32 ... Reset circuit.

Claims (5)

(57) [Claims] 1.Generates multiple channels of signals of any frequency
In the frequency synthesizer A voltage controlled oscillator, Dividing ratio 1 / N or 1 / (N + 1) where N is an arbitrary integer
By dividing the oscillation output of the voltage controlled oscillator by
A round means, A reference signal generating means for generating a reference frequency signal, The phase difference between the frequency signal and the frequency division output of the frequency division means
Phase difference detecting means for detecting, The detection output is in the opposite phase to the detection output of the phase difference detection means.
Correction output generation means for generating a correction output for correcting The frequency division ratio of the frequency dividing means is periodically 1 / N or 1
First control means for controlling to / (N + 1), Adding means for adding the detection output and the correction output, The added output of the adding means is converted into a direct current and the voltage controlled oscillation is performed.
Filter means to give to the vessel, The correction period by the above correction output is set according to the above frequency signal.
Second control means for controlling Perimeter characterized by including
Wave number synthesizer. 2. The frequency synthesizer according to claim 1, wherein the first control means periodically controls the magnitude of the correction output in accordance with the control of the frequency division ratio. 3. The frequency synthesizer according to claim 1, wherein the second control means controls the correction timing by the correction output according to the frequency signal. 4. The correction output generating means has a plurality of current sources having different current values, and selects the current source according to the control of the frequency division ratio to generate the correction output. The frequency synthesizer according to claim 1. 5.Generates multiple channels of signals of any frequency
In the frequency synthesizer Dividing ratios 1 / N and 1 / (N + 1) where N is an arbitrary integer
To periodically divide the oscillation output of the voltage-controlled oscillator.
Frequency division step The reference frequency signal and the frequency division output obtained by the frequency division processing
Phase difference detection step for detecting the phase difference of In the phase opposite to the detection output obtained in the phase difference detection step,
Compensation output generation switch that generates compensation output that compensates detection output
With a tape Addition step for adding the detection output and the correction output
When, According to the addition output obtained in the addition step, the voltage control
Generates a DC component that controls the frequency of the oscillator output
DC conversion step Compensation period by the above compensation output
Control according to Frequency synthesizer characterized by
Method.