GB2107142A - Frequency synthesisers - Google Patents

Abstract

A frequency synthesiser comprises a phase lock loop (3), which includes a frequency divider (5) arranged to divide the output frequency by the divisor value N. To achieve small frequency steps in the output value, the frequency divider is arranged to simulate a required division ratio N, x, where N is an integer and x is a fractional value, by repetitively changing the division factor by a constant integer value of at least two (eg from N-1 to N+2) to provide fractional division factors. Since the effective required divisor value lies between N and N+1, it is possible to arrange that switching between the two actual divisor values of N-1 and N+2 can occur very rapidly. The technique of fractional -N frequency synthesis inevitably introduces phase modulation within the phase lock loop at the output of the frequency divider, which, if allowed to remain, would introduce quite unacceptable noise in the output signal and in order to compensate for this, a phase modulator (6) is included in the loop. The required switching of the division factor is achieved by an accumulator (9) which also provides the correction signal fed to the modulator (6). <IMAGE>

Description

SPECIFICATION Frequency synthesisers This invention relates to frequency synthesisers. A frequency synthesiser is capable of generating an output frequency with an accuracy which is determined by that of a stable frequency reference source. Often a variable frequency oscillator is coupled to the reference source by means of a phase lock loop in which the output frequency f0 is related to the reference frequency fr by the relationship f0=N . frr where N is a divisor by which the output frequency is divided before it is compared with reference value.Conveniently, the factor N is produced at a frequency divider and it is clear that if N is an integer, the smallest increment in output frequency value is necessarily equal to the magnitude of the reference frequency fr itself. This means that for frequency synthesisers requiring fine resolution between its different possible output frequencies, a very low value reference frequency is needed, but this in turn requires a long settling time constant for the phase lock loop.

It has been proposed to overcome this difficulty by using various expedients, particularly involving the use of a number of individual phase locked loops which are interrelated with each other, but these cause spectrally impure output signals which are unsatisfactory for many applications.

Additionally, the expense and complexity of multi-loop frequency synthesisers is a severe disadvantage.

An alternative solution is to adopt non-integral values of N in the relationship given above so that a relatively high value reference frequency can be used to generate output frequencies of fine resolution, whilst needing only a single phase lock loop to achieve them. Such a technique is often called fractional-N synthesis or sometimes called side step programming. In practice, frequency dividers divide only by integral values, and fractional division is simulated by altering the integral value itself during the course of a division cycle.Thus the non-integer division ratios are simulated by dividing by, say N+1 instead of N on a proportion x of the cycles giving an average division ratio which approximates closely to n, x where N is the integer portion and x is the fractional portion of the average value: e.g. if the average division ratio is, say 123.45 then N is 123 and x is 0.45.

Switching between different values of N results in undesirable phase modulation or "jitter" and it has been proposed to negate its effect by generating a correction signal in step with the changes which occur in the value of N so as to cancel the phase modulation which would otherwise appear as spurious sidebands in the synthesised output frequency signal.

Although in principle the periodic switching of a frequency divider between two adjacent integer values of N to simulate a fractional value lying between them is sound, it has proved very difficult, in practice, for certain ranges of fractional values to achieve satisfactory operation of the synthesiser and cancellation of the undesirable phase modulation.

The unsatisfactory operation is particularly apparent when the fractional value differs from one of the adjacent integer values by only a very small amount. In such a case, the period of any phase modulation will inevitably be relatively great, and long periods (of the order of a second or so) can elapse before automatic correction can be accurately applied. Under extreme circumstances this can mean that the frequency synthesiser suffers from relatively long settling times, before a pure spectral output is obtained.

According to a first aspect of this invention, a method of operating a frequency synthesiser which comprises a controllable oscillator; and a frequency divider and a phase comparator in a feedback loop arranged to control the oscillator to produce an output frequency which is related to a reference frequency by the effective divisor value of the frequency divider, includes the steps of selecting two integer divisor values which differ from each other by an integer value of at least two and which are chosen so that the effective divisor value lies between them; repetitively changing the divisor from one selected integer value to the other when the accumulated sum of a periodically occurring first quantity amounts to or exceeds a predetermined second quantity so as to simulate the required effective divisor value which relates the oscillator frequency to the reference frequency; and deriving from said sum as it is accumulated a jitter compensation signal which is used to suppress phase jitter in the oscillator control signal that would otherwise result from periodic changes of said integral factor.

According to a second aspect of this invention, a frequency synthesiser includes a controllable oscillator; a frequency divider and a phase comparator in a feedback loop arranged to control the oscillator to produce a frequency which is related to a reference frequency by the effective divisor value of the frequency divider which includes or consists of a controllable integral factor which is changed periodically by a constant integer value of at least two when the accumulated sum of a periodically occurring first quantity amounts to or exceeds a predetermined second quantity so as to produce in effect the required effective divisor value which relates the oscillator frequency to the reference frequency; and means for deriving from said sum as it is accumulated a jitter compensation signal which is used to suppress phase jitter in the oscillator control signal that would otherwise result from periodic changes of said integral factor.

Preferably, the controllable integral factor is changed repetitively by an integer value of 3; that is to say, if a required fractional value lies between adjacent integer values of N and N+ 1 , the controllable integral factor is periodically changed from a value of N-1 to N+2. This ensures that any correcting phase modulation signal has a relatively high frequency component, and that the settling time of the phase lock loop is acceptably short. In certain cases for which the fractional value lies very close to an adjacent integral value, it is acceptable to change the controllable integral factor by an integer value of only two.For example, if the required fractional value is only slightly greater than the integral value N, it may be acceptable to change the controllable integral factor between the values of N-1 and N+1, since the required fractional value will lie at least approximately mid-way between these two values, and this causes the resulting phase modulation to have an acceptably higher frequency.

In general the required effective divisor value is N, x where N is an integer and x is a fraction, but for certain cases x can be zero. For example, if the required effective divisor value is exactly N, it can be simulated by switching alternately between N-i and N+2, such that there are twice as many divisions at the N-i value as there are at the N+2 value.

The invention is further described by way of example with reference to the accompanying drawings, in which Figure 1 illustrates in diagrammatic form a frequency synthesiser in accordance with the present invention, Figures 2 and 3 are explanatory diagrams and Figure 4 shows part of the system in greater detail.

Referring to Figure 1, the frequency synthesiser includes a variable frequency oscillator 1 , which is controiled so as to provide the required synthesised output frequency at an output terminal 2. The oscillator 1 forms part of a phase lock loop 3 which is operative to generate a control signal which constrains the oscillator to provide the correct value output. The phase lock loop 3 locks the output signal to a multiple (integral or fractional) of the frequency fr provided by a stable frequency reference source 4.

The output of the oscillator 1 is also fed via a variable ratio frequency divider 5 and a time delay phase modulator 6 to one input of a phase comparator 7, where it is combined with the reference frequency fr Any difference in frequency between the two signals which are applied to the phase comparator 7 results in a control signal being fed via a low pass filter 8 to the oscillator 1 to control its frequency.

As so far described, the phase lock loop is well known and forms a part of many frequency synthesisers. Assuming for the moment that the frequency divider 5 produces an integral divisor N, then the output frequency f0 produced at terminal 2 is given by the relationship f0=N . fr The output frequency fc can be very accurately locked to the reference frequency f,, but clearly it can only take values which are integral multiples of the reference frequency, and, of course, the multiple is determined by the choice of value N.A frequency synthesiser of this kind suffers from many disadvantages, the most important being that if a range of available output frequencies are required which differ from each other by only a small frequency interval or "step" then this frequency interval determines the value of the reference frequency since it must be equal to it. It is becoming increasingly common for the required interval between adjacent variable frequencies to be as low as 1 Hz, and the consequence of this requirement is that if N can take only integral values, then in theory the reference frequency must be 1 Hz-this follows directly from the above relationship.Reference frequencies of such a low value are not practicable, as they cannot provide stable oscillator outputs and, in any event, the settling time of the phase lock loop would inevitably be very long, i.e. of the order of many seconds.

Accordingly, it has been proposed to obtain output frequencies having relatively small step intervals from a reference frequency having an acceptably high frequency, by periodically altering the value of N during a single division cycle to simulate a fractional value. Such a process is known as fractional-N frequency synthesis, and in general if a required average division ratio has a value N, x where N is the integer portion and x is the fractional portion, then the value of N is switched repetitively between the values of N and N+ 1, with the proportion of the division cycle at each value determining the fractional value x.Periodic switching of the value of N inevitably results in unwanted phase modulation in the signal which is applied to the phase comparator, and its effect is removed by controlling the time delay phase modulator 6 so as to cancel this undesirable phase modulation. If this phase modulation were not removed, the output frequency on terminal 2 would be correct but would contain unwanted spurious components. Instead of using the phase modulator 7 to cancel the phase modulation, the same effect can be achieved by adding a corresponding correction signal to the output of the phase comparator, so as to cancel amplitude fluctuations in it.

The output fd of the frequency divider 5 is fed to the clock input of an accumulator 9. The accumulator 9 is fed by a digital adder 10 which adds the fractional information x to a fixed number, which is chosen in relation to the reference frequency value and the spacing between the two integer values which operate the frequency divider 5. The result of this addition is fed to the accumulator 9, where it is added to the existing contents of the accumulator on the occurrence of each clock pulse from the output of the frequency divider 5. The cumulative contents of the accumulator 9 is representative of the undesired phase shift occurring in the frequency fd and a knowledge of this cumulative sum is used to correct for this undesirable phase modulation.

The cumulative sum of the accumulator 9 is fed to a digital-to-analogue converter 11 and the resulting analogue signal is used to operate the phase modulator 6, so as to exactly cancel the phase jitter which would otherwise be present. In order to achieve this exact cancellation, the scaling factor of the converter 11 is important-the amplitude of the analogue signal which is produced from a given digital value must be adjusted to provide the required degree of gain which achieves exact cancellation.

In order to ensure that the scaling factor of the converter 11 is correct, the output of the phase comparator 7 is monitored by a correction circuit 1 2. If the operation of the phase modulator 6 is exactly correct, then the output of the phase comparator 7 will be smooth and will contain no abrupt signal amplitude transitions. The control circuit 12 is therefore arranged to determine whether transitions occur, and if so, to adjust the scaling factor of the converter 11, so as to eliminate them. The signal level transitions, if present, will occur in step with changes in the divisor value of the frequency divider 5.This divisor value is arranged to change from one selected integer value to the other selected integer value whenever the contents of the accumulator 9 over-flows so as to cause corrected operation of the phase lock loop to achieve fractional division and this occurrence is also used by the correction circuit 12 in order to synchronise its operation with the expected time of occurrence of any signal level transitions which represent phase jitter. The operation of a similar correction circuit is described in more detail in our co-pending Patent Applicaton 8112357.

The difficulty which arises with known frequency synthesisers, in which the divisor value of the variable frequency divider 5 is changed between adjacent integer values of N and N+ 1 is illustrated by way of example as follows. Considering a practical example in which the reference frequency fr is 100 kHz and the output frequency is selected to be just 1 Hz above an integer harmonic of this reference frequency, then the average divisor value N, x is given by N . 00001. In order to achieve an average division ratio equal to this value, the synthesiser is arranged such that in each period of one second, the variable frequency divider 5 operates to divide by N for 99999 cycles of the reference frequency fr and by N+ 1 for only one reference cycle before the sequence repeats.As a result of this there must be a very gradual build up in phase difference between the reference frequency fr and the divided frequency fd which is generated by the frequency divider 5. Consequently a sawtooth waveform having a repetition period of one second appears at the output of the phase comparator 7, and in order to prevent unwanted phase modulation of the oscillator 1, this sawtooth waveform must be exactly cancelled by the phase modulator 6 in response to a signal produced by the accumulator 9 and converter 11. Cancellation of such a slow waveform is extremely difficult to achieve and maintain precisely over a long period, yet the ultimate purity of the output signal f0 is dependent upon it.

Therefore, the present invention differs from previous proposals by arranging that the divisor value of the variable frequency divider 5 alternates between two integral values of N which differ from each other by at least 2. In a preferred example, the integral difference value is 3 and the mode of operation of such a frequency synthesiser is as follows. As before, let the reference frequency fr be 100 kHz, and assume that the oscillator 1 is required to cover the frequency range 70 MHz to 100 MHz in 1 Hz increments.In this case the fixed number applied to the digital adder 10 will be 100,0(30 (this represents a 1 cycle delay of the reference frequency for). The accumulator 9 is provided with a capacity such that it over-flows whenever the cumulative value exceeds 300,000-this ensures that the longest possible time interval between successive over-flow events is only three cycles of the reference frequency fr Thus the capacity of the accumulator corresponds to the integer difference between the two selected integer division values, i.e. in this example the difference between N-i and N+2 is "3".

By way of example, assume that the required output frequency f0 of the oscillator 1 is 88600001 Hz. Consequently, the integer N is 886, giving the value of N-i as 885 and that of N+2 as 888 and the fractional information x is .00001. The number fed to the accumulator 9 from the digital adder 10 each time the accumulator is clocked is therefore 100001 (ignoring the decimal point). The operation of the synthesiser shown in Figure 1 is to produce fractional divisor values lying between integer values of N and N+1 by switching between integer values of N-1 and N+2. This is illustrated diagrammatically in Figure 2, and the cross-hatched region identifies the available frequency range which is achieved in this way.The following table shows how the value 100001 is accumulated on the occurrence of each lock pulse from the variable frequency divider 5 for the first ten reference cycles.

Accumulator Accumulator Division clock pulse Accumulated over-flow ratio of no. value signal divider 5 1 100001 "0" N-i 2 200002 "0" N-i 3 000003 "1" N+2 4 100004 "0" N-i 5 200005 "0" N-i 6 000006 "1" N+2 7 100007 "0" N-i 8 200008 "0" N-i 9 000009 "1" N+2 10 100010 ~1. "0" N-i It can be seen that whenever the value of 300000 is exceeded, the accumulator over-flow signal is switched from a logic 0 to a logic 1, with any remainder being left in the accumulator. These processes are also illustrated in lines a and b respectively of Figure 3. The over-flow signal, as represented by line b of Figure 3, is used to switch the division ratio of the divider 5 from N-i to N+2 as is illustrated in line c of Figure 3. Line a of Figure 3 simply shows more clearly how the accumulated value varies as clock pulses of fd are applied to it. A waveform having an identical staircase shape appears at the output of the digital-to-analogue converter 11, and is used to control the phase modulator 6.It can be seen that the staircase waveform is not a sawtooth of very long duration (as would be the case if integer values of N and N+1 were used), but it has a relatively high frequency as the accumulator is arranged to overflow very rapidlyon average it over-flows every third clock pulse from the frequency divider 5, i.e. on every third cycle of the frequency fd.

Although a low frequency will inevitably exist in this waveform over a period of time, this is effectively masked by the high frequency components superimposed upon it. It is important to note that the number of divisions by N-i and by N+2 is of a similar order, and in this example in a period of three seconds, the divider 5 will divide by 885 for 199999 reference cycles and by 888 for 100001 reference cycles. As previously described, the high frequency analogue output signal of the digital-toanalogue converter 11 is fed to the control input of the time delay phase modulator 6, such that the residual content of the accumulator 9 determines the amount of delay.

Because the division ratio of the frequency divider 5, alters between N-i and N+2, the stream of pulses which it provides as an output signal are not regularly spaced even though on average they have a frequency fd The action of the phase modulator 6 is to selectively delay slightly each of these pulses in a controlled manner such that the stream of pulses which is applied to the phase comparator are exactly spaced apart from each other by precisely the same time interval. Thus all unwanted phase modulation is removed from this signal so that it consists solely of frequency fd.

The time delay phase modulator 6 can take any convenient form. It is operative to delay the edge (leading or trailing) of an input pulse by an amount determined by a control signal. One simple form consisting of a ramp generator followed by a comparator is shown in Figure 4. The ramp generator 40 is tugged by an input pulse received at terminal 41 from the frequency divider 5 and the comparator 42 switches when the ramp level exceeds the value of the control signal at terminal 43 received from the digital-to-analogue converter 11. Thus the output pulse at the output 44 of the comparator 42 is delayed relative to the input pulse by the required amount.

The required amount of scaling of the output of the digital-to-analogue converter voltage necessary to achieve this exact removal of the phase modulation is not a constant, but varies with the selected output frequency, and the correction circuit 12 is operative to adjust the scaling factor as necessary. This circuit also provides compensation for factors such as temperature changes and component ageing etc., and as previously mentioned, it can take the form shown in our eariier Patent Application 8112357.

Claims (6)

Claims

1. A method of operating a frequency synthesiser which comprises a controllable oscillator; and a frequency divider and a phase comparator in a feedback loop arranged to control the oscillator to produce an output frequency which is related to a reference frequency by the effective divisor value of the frequency divider, including the steps of selecting two integer divisor values which differ from each other by an integer value of at least two and which are chosen so that the effective divisor value lies between them; repetitively changing the divisor from one selected integer value to the other when the accumulated sum of a periodically occurring first quantity amounts to or exceeds a predetermined second quantity so as to simulate the required effective divisor value which relates the oscillator frequency to the reference frequency; and deriving from said sum as it is accumulated a jitter compensation signal which is used to suppress phase jitter in the oscillator control signal that would otherwise result from periodic changes of said integral factor.

2. A method as claimed in Claim 1 and wherein, to achieve a given output frequency, the controllable integral division factor of the frequency divider is changed repetitively by an integer value of three such that a division frequency ratio is simulated which differs from each of the two selected integers by an amount which is greater than unity.

3. A method as claimed in Claim 1 or 2 and wherein the capacity of the accumulator is chosen in dependence on the value of the reference frequency, the difference in magnitude of the two selected integer divisor values, and on the magnitude of the said periodically occurring first quantity.

4. A method as claimed in Claim 3 and wherein the accumulator is arranged to over-flow at intervals not greater than the number of periods of the reference frequency which corresponds to the difference in magnitude of the two selected integer divisor values.

5. A frequency synthesiser including a controllable oscillator; a frequency divider and a phase comparator in a feedback loop arranged to control the oscillator to produce a frequency which is related to a reference frequency by the effective divisor value of the frequency divider, the actual division ratio of the divider including a controllable integral factor which is changed periodically by a constant integer value of at least two when the accumulated sum of a periodically occurring first quantity amounts to or exceeds a predetermined second quantity so as to produce in effect the required effective divisor value which relates the oscillator frequency to the reference frequency; and means for deriving from said sum as it is accumulated a jitter compensation signal which is used to suppress phase jitter in the oscillator control signal that would otherwise result from periodic changes of said integral factor.

6. A frequency synthesiser substantially as illustrated in and described with reference to Figure 1 of the accompanying drawings.