JP2511657B2 - Frequency synthesizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital direct synthesis frequency synthesizer capable of switching frequencies faster than a phase lock loop frequency synthesizer.

(Prior Art and Problems Thereof) A conventional device of this type is constructed as in the first embodiment shown in FIG. In FIG. 7, 1 is a frequency setting circuit, 2 is a phase accumulator, 3 is a sine waveform ROM, and 4 is D.
A / A converter, 5 is a low-pass filter, and 6 is a reference oscillator.
Here, the phase accumulator 2 includes full adders 21, 22, 23 and D type flip-flops 24, 25, as shown in FIG.
Consists of 26, has the function of a digital integrator cumulatively added for each oscillation period 1 / f _r of the reference oscillator 6 given frequency setting value Fi by the frequency setting circuit 1. FIG. 8A is a diagrammatic representation of the operation of the phase accumulator 2, where the horizontal axis represents time and the vertical axis represents the cumulative addition value of the phase accumulator 2. FIG. 8A shows that the cumulative addition value increases with the passage of time.

The output of the phase accumulator 2 is connected to the address input of the sine waveform ROM 3, and the triangular wave-like change of the input data is converted into a sine wave-like change and output.
This state is represented as shown in FIG. Next, the digital value output from the sine waveform ROM3 is converted to the D / A converter 4
The waveform of FIG. 8C is obtained by changing to an analog value with. Therefore, when the output of the D / A converter 4 is applied to the low-pass filter 5, it is possible to obtain a sinusoidal output signal having the waveform shown in FIG. Then, when the cumulative addition value of the phase accumulator 2 reaches the total capacitance value, an overflow signal is generated and the cumulative addition operation is repeated, so that a continuous sine wave output can be obtained from the low-pass filter 5.

For applications that do not necessarily require a sine wave as the output of the frequency synthesizer, the second one shown in FIG.
It is also possible to use the frequency setting circuit 1, the phase accumulator 2 and the reference oscillator 6 as in the prior art example 1, and use the overflow signal of the phase accumulator 2 as a pulse waveform.

Also in this case, similarly to the first conventional embodiment, a frequency proportional to the frequency setting value (digital information) set by the frequency setting circuit 1 can be generated. Now, in FIG. 9 (c), the frequency setting value of the frequency setting circuit 1 is Fi, the total capacitance value of the phase accumulator 2 is Nt,
If the reference frequency of the reference oscillator 6 is f _r , the output frequency f ₀
Is f ₀ = f _r × Fi / Nt.

For example, if _fr = 1MHz, Fi = 1, Nt = 10, the output frequency f
₀ becomes f ₀ = 100 kHz, and the operation in this case is equivalent to the result of dividing the reference frequency f _r by 1/10 using a decade counter.

By changing the set value Fi as described above, F
It is possible to generate the output frequency f ₀ proportional to i, but the ratio of the reference frequency f _r to the output frequency f _{0 is} f _r / f ₀ ,
In other words, the ratio Nt / Fi of the total capacity value Nt and the frequency setting value Fi
When is an integer, the output signal does not include phase jitter in principle.

FIG. 9A shows an operation example when Nt / Fi = 5, where the horizontal axis represents time and the vertical axis represents the cumulative addition value of the phase accumulator 2. Drawing, accumulated sum is increased every reference period 1 / f _r, It shows a state in which an overflow signal (indicated by Δ in the figure) is regularly generated in each cycle.

However, if the ratio of Nt to Fi is not an integer, the output signal will include phase jitter.

Although FIG. 9 (b) is an example of what happens when a Nt / Fi = 10/3, and if the period for generating an overflow signal is 4 / f _r
There are cases of 3 / f _r , and they are not evenly spaced. In the figure, 4 / _fr is 1
Times, 3 / f _r indicates a dividing sequential table at a rate of 2 times. Therefore, the frequency spectrum of the output signal is not a line spectrum, but a frequency spectrum containing unwanted sideband noise.

As a countermeasure, various methods such as the following have been conventionally taken.

(A) In FIG. 7, the cutoff frequency of the low-pass filter 5 is switched according to the output frequency to average the phase jitter, and (b) the output frequency f ₀ compared to the reference frequency f _r.
Is small enough, in other words, the area where the ratio of Nt / Fi is large enough, that is, the method used only in the area where the phase jitter appears relatively infrequently, (c) The output signal is divided to reduce the phase jitter. How to use after doing,
(D) A method of adding the output signal to the phase-locked oscillator and averaging the phase jitter with a low-pass filter in the phase-locked loop has been attempted.

However, the conventional methods described above have drawbacks such that the effect of reducing the phase jitter is not sufficient, and the high-speed response characteristic originally of the direct synthesizer frequency synthesizer is lost.

(Means for Solving Problems) In order to solve these drawbacks, the present invention extracts and stores residual data when the phase accumulator overflows in addition to a reference oscillator, a phase accumulator, and a frequency setting circuit. A residual data memory and a first data conversion unit for converting the residual data into a voltage inversely proportional to its magnitude.
A D / A converter, a second D / A converter for converting the set value of the frequency setting circuit into a voltage proportional to its magnitude, and an overflow signal of the phase accumulator synchronized with the output of the reference oscillator. A pulse synchronizer that removes fluctuations contained in the signal and outputs a signal having a constant pulse width, and a delay to the output signal of the pulse synchronizer using the output voltages of the first and second D / A converters as control voltages. The voltage control phase shifter is composed of a voltage control phase shifter for applying the output signal and a frequency divider for inputting the output signal. The voltage control phase shifter supplies an electric current to the integrating circuit which rises by the output signal of the pulse synchronizer and the current. The value is the second
A constant current source controlled by the output voltage of the D / A converter, and a comparator for comparing the output voltage of the first D / A converter with the output voltage of the integrating circuit. The following is a detailed description with reference to the drawings.

(Embodiment) FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. In the figure, 4A is the first D / A converter and 4B
Is a second D / A converter, 7 is a pulse synchronizer, 8 is a residual data memory, 9 is a voltage controlled phase shifter, and 10 is a frequency divider. Here, the output frequency f _r of the reference oscillator 6 is, for example, 20 MHz.
z, the total capacity value Nt of the phase accumulator 2 is 1,000,000,
A frequency division number Nd of the frequency divider 10 2, per example to obtain an output frequency f _d = 200.01kHz from the output frequency _{f d = f r · Fi /} Nt · Nd i.e. f _d = 10Fi the frequency setting value Fi as 20,001 Proceed with the explanation. Phase accumulator 2 returns puppet cumulatively added for each reference period 1 / f _r from the initial state zero, when the overflow signal occurs, when the store to residual data memory 8 extracts residual data of phase accumulator 2, the data is , As shown in FIG. 3 (a), it changes with the passage of time. The process is as described below. In this example, the ratio of Nt and Fi
Nt / Fi is 49.9975 not an integer, the reference period 1 / f _r 4 of
It is only necessary that the overflow signals be generated at equal intervals every 9.9975 times as shown in FIG. 2 (a), but since the phase accumulator 2 actually performs the digital calculation, the overflow signals are generated every 50 times the reference period. The phase of the overflow signal is delayed as shown in FIG. By the way, the phase delay Δt at this time is 1 / f _r × 50−1 / f _r × Nt / Fi =
It is 0.125 × 10 ^-9 (seconds). Then, when the overflow signal occurs next time, the phase delays further, and the phase delay becomes 2Δt as shown in FIG. Similarly, the next phase delay is 3Δt. In this way, the phase delay is accumulated,
When attempting to exceed the reference cycle 1 / _fr = 50 × 10 ^-9 (seconds), the overflow cycle that has occurred every 50 times the reference cycle until now becomes 49 times the reference cycle. Then, the overflow signal is generated again every 50 cycles and the above operation is repeated.

After all, 399 times overflow signal every 50 times the reference period 1 / f _r is generated, because once overflow signal at 49 times the period of the reference period 1 / f _r is generated, the apparent on average reference Periodic An overflow signal is generated every time. (The average frequency at this time is 400.02kHz).

Now, the magnitude of the residual data when the phase accumulator 2 generates an overflow signal is proportional to the magnitude of the phase shift as described above.
In the converter 4A, as shown in Fig. 3 (a), when the residual data is large, the output voltage of the D / A converter 4A is reduced, and when the residual data is small, the output voltage is increased so that the residual data becomes large. The circuit is configured to output a voltage that is inversely proportional.

On the other hand, when the phase accumulator 2 performs cumulative addition to the overflow signal, as shown in FIG.
When 21,22,23 are cascaded, fluctuations are included due to fluctuations in the operating time, etc. Therefore, the pulse synchronizer 7 absorbs fluctuations of the overflow signal by synchronizing with the reference signal. At the same time, it operates with the function of converting the waveform of the output signal into a waveform convenient as an input to the voltage control phase shifter 9 in the next stage.

The next voltage control phase shifter 9 is composed of an electronic switch 91, a constant current source 92, an integrating capacitor 93, and an ultrahigh-speed precision comparator 94 as shown in FIG. Now, assuming that the output signal of the pulse synchronizer 7 is the signal shown in FIG. 5 (a), the high level pulse of the signal turns on the electronic switch 91 to discharge the integrating capacitor 93, and the output signal of the pulse synchronizer 7 is output. Becomes low, the electronic switch 91 is turned off and the integrating capacitor 93 is charged with the current i from the constant current source 92.

Therefore, if the capacitance of the integrating capacitor 93 is C and the elapsed time is t, the potential of the integrating capacitor 93 linearly rises with a function of (i / c) t as is well known. The potential is the first
When the output voltage of the D / A converter 4A (shown by the broken line in FIG. 5 (a)) is exceeded, the output of the ultra-high-speed precision comparator 94 has the output potential up to now as shown in FIG. 5 (c). If it was at a low level, it switches to a high level. In the next cycle, the first D / A converter 4 as shown by the broken line in FIG.
When the output voltage of A decreases, the delay time td2 from when the pulse synchronizer 7 gives a high level pulse to when the output potential of the ultra-high-speed precision comparator 94 switches is
It becomes smaller than the previous delay time td1. That is, when the output voltage of the first D / A converter 4A as the control input is low, the delay amount of the voltage control phase shifter 9 is small, and when the output voltage is high, the delay amount is large. It becomes a relative relationship like (a) and (c). Returning to FIG. 2 again, the overflow signal of the phase accumulator 2 shown in (a) appears as an output signal of the pulse synchronizer 7 as shown in FIG. 2 (c) after being synchronized by the pulse synchronizer 7. The amount of delay given to the output signal of the pulse synchronizer 7 is large when the residual data when the overflow signal occurs is small, and small when the residual data is large. Therefore, the output of the voltage control phase shifter 9 is small. The signal is
It becomes as shown in FIG. Here, if the delay amount when the residual data is zero is td0, then td1 = td0- △ t, td2 = td0-
2Δt, td3 = td0−3Δt The relation between the control voltage applied to the voltage control phase shifter 9 and the delay amount, that is, the control sensitivity of the voltage control phase shifter 9 is set to cause an overflow of the phase accumulator 2. The phase jitter contained in the signal is canceled. In the detailed description up to now, the frequency setting value Fi is constant, but when Fi is changed, the control sensitivity of the voltage control phase shifter 9 is low when Fi is large, and the control sensitivity is low when Fi is small. First to make it higher
As shown in the figure, the frequency setting value Fi is D / A converted by the second D / A converter 4B.
The converted result is added to the other control input of the voltage control phase shifter 9. The output voltage of the second D / A converter 4B controls the constant current source 92 as shown in FIG. 4, and changes the current i in proportion to the frequency setting value Fi. That is, the integration gradient of the integration circuit of the capacitor 93 is controlled according to the frequency setting value to change the delay amount given to the overflow signal. Therefore, when the charging gradient shown in FIG. 5 (a) is large, Fi becomes steep and the control sensitivity becomes low (td is small, that is, the delay amount given to the overflow signal is small), and conversely, When Fi is small, the circuit operates so that the gradient during charging is gentle and the control sensitivity is high (td is large, that is, the amount of delay given is large).

Next, as shown in FIG. 1, the output of the voltage controlled phase shifter 9 is connected to the frequency divider 10. The output waveform of the voltage control phase shifter 9 is shown in FIG. 5 (c). In this example, if the frequency divider 10 operates at the rising edge and the frequency division ratio Nd is 2, FIG. A waveform with a duty cycle of 50% is obtained. At this stage, the final output frequency f _d is represented by f _d = f _r · f _i / Nt · Nd as described above. Finally, the low-pass filter 5 removes harmonic components to obtain the output signal of this frequency synthesizer.

(Effect of the Invention) As described above, according to the present invention, the fluctuation and the phase jitter included in the overflow signal of the phase accumulator are removed by the pulse synchronizer, and the phase jitter is converted into the residual data and the frequency set value. Accordingly, the circuit operates so as to change the delay amount of the pulse synchronizer output signal and cancel the phase jitter, so that the high-speed response characteristic, which is the original feature of the direct synthesizer frequency synthesizer, is not lost, and the noise is low. A frequency synthesizer can be realized. That is, the low-pass filter shown in FIG. 7 is an inevitable constituent element for removing the reference frequency component and reducing the phase jitter, and the response speed when the frequency is switched is mainly determined by the characteristics of the low-pass filter. Will be done,
In the present invention, since the output of the frequency divider does not include the reference frequency component in principle, and the phase jitter has already been canceled, the low pass filter is not always necessary. FIG. 6 shows an example of the result of comparison between the case where the phase jitter is canceled and the case where the phase jitter is not cancelled. In the figure, the horizontal axis represents frequency, the vertical axis represents amplitude in decibels, the central peak represents the spectrum of the main component of the output signal, and the peaks on both sides of the main component represent the unwanted sideband component. For "no phase jitter cancellation" of the unwanted sideband component, disconnect the line of the voltage applied from the D / A converter 4A to the voltage control phase shifter 9 in Fig. 1 and apply a fixed DC voltage instead. The “phase jitter cancellation” is measured by adding the output of the D / A converter 4A to the voltage controlled phase shifter 9. With this, it was confirmed that the improvement effect of about 27.5 dB appears by canceling the phase jitter.

[Brief description of drawings]

FIG. 1 is an embodiment of the present invention, FIGS. 2 to 5 are explanatory views of the operation of FIG. 1, FIG. 6 is an example of data showing the effect of the present invention, and FIG. 7 is a frequency of a conventional direct synthesis system. A synthesizer, FIG. 8 shows the operation waveforms of FIG. 7, FIG. 9 shows a second example of a conventional direct synthesis frequency synthesizer, and FIG. 10 shows a concrete example of a phase accumulator. 1 ... Frequency setting circuit, 2 ... Phase accumulator, 4
...... D / A converter, 4A, 4B ...... First and second D / A converters, 5 ...... Low pass filter, 6 ...... Reference oscillator, 7 ...... Pulse synchronizer, 8 ...... Residual data memory, 9 ... Voltage control phase shifter, 10 ... Divider ,.

Claims (1)

(57) [Claims] 1. A reference oscillator, a phase accumulator that cumulatively adds phase information for each cycle of the oscillation output, a residual data memory that extracts and stores residual data when the phase accumulator overflows, and the residual data. A first D / A converter for converting the voltage to a voltage inversely proportional to the magnitude, a frequency setting circuit for setting the output frequency to a desired value, and a second D / A converter for converting the setting value to a voltage proportional to the magnitude.
A D / A converter, a pulse synchronizer that synchronizes the overflow signal with the output of the reference oscillator, removes fluctuations contained in the signal, and outputs a signal having a constant pulse width, and the first and second A voltage control phase shifter for delaying the output signal of the pulse synchronizer using the output voltage of the D / A converter as a control voltage, and a frequency divider for inputting the output signal, the voltage control phase shifter, An integrating circuit that rises with the output signal of the pulse synchronizer, and a current is supplied to the integrating circuit, and the current value is the second value.
A constant current source controlled by the output voltage of the D / A converter, and a comparator for comparing the output voltage of the first D / A converter with the output voltage of the integrating circuit, and the frequency setting value The frequency synthesizer is configured to control the integration slope of the integration circuit of the voltage control phase shifter according to the above, and change the delay amount given to the overflow signal of the phase accumulator according to the residual data.